4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 #include "libqos/libqos-pc.h"
33 #include "libqos/ahci.h"
34 #include "libqos/pci-pc.h"
35 #include "libqos/malloc-pc.h"
37 #include "qemu-common.h"
38 #include "qemu/host-utils.h"
40 #include "hw/pci/pci_ids.h"
41 #include "hw/pci/pci_regs.h"
43 /* Test-specific defines. */
44 #define TEST_IMAGE_SIZE (64 * 1024 * 1024)
47 static QGuestAllocator
*guest_malloc
;
48 static QPCIBus
*pcibus
;
49 static char tmp_path
[] = "/tmp/qtest.XXXXXX";
50 static bool ahci_pedantic
;
52 /*** IO macros for the AHCI memory registers. ***/
53 #define AHCI_READ(OFST) qpci_io_readl(ahci->dev, ahci->hba_base + (OFST))
54 #define AHCI_WRITE(OFST, VAL) qpci_io_writel(ahci->dev, \
55 ahci->hba_base + (OFST), (VAL))
56 #define AHCI_RREG(regno) AHCI_READ(4 * (regno))
57 #define AHCI_WREG(regno, val) AHCI_WRITE(4 * (regno), (val))
58 #define AHCI_SET(regno, mask) AHCI_WREG((regno), AHCI_RREG(regno) | (mask))
59 #define AHCI_CLR(regno, mask) AHCI_WREG((regno), AHCI_RREG(regno) & ~(mask))
61 /*** IO macros for port-specific offsets inside of AHCI memory. ***/
62 #define PX_OFST(port, regno) (HBA_PORT_NUM_REG * (port) + AHCI_PORTS + (regno))
63 #define PX_RREG(port, regno) AHCI_RREG(PX_OFST((port), (regno)))
64 #define PX_WREG(port, regno, val) AHCI_WREG(PX_OFST((port), (regno)), (val))
65 #define PX_SET(port, reg, mask) PX_WREG((port), (reg), \
66 PX_RREG((port), (reg)) | (mask));
67 #define PX_CLR(port, reg, mask) PX_WREG((port), (reg), \
68 PX_RREG((port), (reg)) & ~(mask));
70 /*** Function Declarations ***/
71 static QPCIDevice
*get_ahci_device(uint32_t *fingerprint
);
72 static void start_ahci_device(AHCIQState
*ahci
);
73 static void free_ahci_device(QPCIDevice
*dev
);
75 static void ahci_test_port_spec(AHCIQState
*ahci
, uint8_t port
);
76 static void ahci_test_pci_spec(AHCIQState
*ahci
);
77 static void ahci_test_pci_caps(AHCIQState
*ahci
, uint16_t header
,
79 static void ahci_test_satacap(AHCIQState
*ahci
, uint8_t offset
);
80 static void ahci_test_msicap(AHCIQState
*ahci
, uint8_t offset
);
81 static void ahci_test_pmcap(AHCIQState
*ahci
, uint8_t offset
);
85 static void string_bswap16(uint16_t *s
, size_t bytes
)
87 g_assert_cmphex((bytes
& 1), ==, 0);
97 * Locate, verify, and return a handle to the AHCI device.
99 static QPCIDevice
*get_ahci_device(uint32_t *fingerprint
)
102 uint32_t ahci_fingerprint
;
104 pcibus
= qpci_init_pc();
106 /* Find the AHCI PCI device and verify it's the right one. */
107 ahci
= qpci_device_find(pcibus
, QPCI_DEVFN(0x1F, 0x02));
108 g_assert(ahci
!= NULL
);
110 ahci_fingerprint
= qpci_config_readl(ahci
, PCI_VENDOR_ID
);
112 switch (ahci_fingerprint
) {
113 case AHCI_INTEL_ICH9
:
116 /* Unknown device. */
117 g_assert_not_reached();
121 *fingerprint
= ahci_fingerprint
;
126 static void free_ahci_device(QPCIDevice
*ahci
)
128 /* libqos doesn't have a function for this, so free it manually */
132 qpci_free_pc(pcibus
);
137 /*** Test Setup & Teardown ***/
140 * Start a Q35 machine and bookmark a handle to the AHCI device.
142 static AHCIQState
*ahci_boot(void)
147 s
= g_malloc0(sizeof(AHCIQState
));
149 cli
= "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
152 "-device ide-hd,drive=drive0 "
153 "-global ide-hd.ver=%s";
154 s
->parent
= qtest_pc_boot(cli
, tmp_path
, "testdisk", "version");
156 /* Verify that we have an AHCI device present. */
157 s
->dev
= get_ahci_device(&s
->fingerprint
);
159 /* Stopgap: Copy the allocator reference */
160 guest_malloc
= s
->parent
->alloc
;
166 * Clean up the PCI device, then terminate the QEMU instance.
168 static void ahci_shutdown(AHCIQState
*ahci
)
170 QOSState
*qs
= ahci
->parent
;
171 free_ahci_device(ahci
->dev
);
176 /*** Logical Device Initialization ***/
179 * Start the PCI device and sanity-check default operation.
181 static void ahci_pci_enable(AHCIQState
*ahci
)
185 start_ahci_device(ahci
);
187 switch (ahci
->fingerprint
) {
188 case AHCI_INTEL_ICH9
:
189 /* ICH9 has a register at PCI 0x92 that
190 * acts as a master port enabler mask. */
191 reg
= qpci_config_readb(ahci
->dev
, 0x92);
193 qpci_config_writeb(ahci
->dev
, 0x92, reg
);
194 /* 0...0111111b -- bit significant, ports 0-5 enabled. */
195 ASSERT_BIT_SET(qpci_config_readb(ahci
->dev
, 0x92), 0x3F);
202 * Map BAR5/ABAR, and engage the PCI device.
204 static void start_ahci_device(AHCIQState
*ahci
)
206 /* Map AHCI's ABAR (BAR5) */
207 ahci
->hba_base
= qpci_iomap(ahci
->dev
, 5, &ahci
->barsize
);
209 /* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */
210 qpci_device_enable(ahci
->dev
);
214 * Test and initialize the AHCI's HBA memory areas.
215 * Initialize and start any ports with devices attached.
216 * Bring the HBA into the idle state.
218 static void ahci_hba_enable(AHCIQState
*ahci
)
220 /* Bits of interest in this section:
221 * GHC.AE Global Host Control / AHCI Enable
222 * PxCMD.ST Port Command: Start
223 * PxCMD.SUD "Spin Up Device"
224 * PxCMD.POD "Power On Device"
225 * PxCMD.FRE "FIS Receive Enable"
226 * PxCMD.FR "FIS Receive Running"
227 * PxCMD.CR "Command List Running"
229 uint32_t reg
, ports_impl
, clb
, fb
;
231 uint8_t num_cmd_slots
;
233 g_assert(ahci
!= NULL
);
235 /* Set GHC.AE to 1 */
236 AHCI_SET(AHCI_GHC
, AHCI_GHC_AE
);
237 reg
= AHCI_RREG(AHCI_GHC
);
238 ASSERT_BIT_SET(reg
, AHCI_GHC_AE
);
240 /* Cache CAP and CAP2. */
241 ahci
->cap
= AHCI_RREG(AHCI_CAP
);
242 ahci
->cap2
= AHCI_RREG(AHCI_CAP2
);
244 /* Read CAP.NCS, how many command slots do we have? */
245 num_cmd_slots
= ((ahci
->cap
& AHCI_CAP_NCS
) >> ctzl(AHCI_CAP_NCS
)) + 1;
246 g_test_message("Number of Command Slots: %u", num_cmd_slots
);
248 /* Determine which ports are implemented. */
249 ports_impl
= AHCI_RREG(AHCI_PI
);
251 for (i
= 0; ports_impl
; ports_impl
>>= 1, ++i
) {
252 if (!(ports_impl
& 0x01)) {
256 g_test_message("Initializing port %u", i
);
258 reg
= PX_RREG(i
, AHCI_PX_CMD
);
259 if (BITCLR(reg
, AHCI_PX_CMD_ST
| AHCI_PX_CMD_CR
|
260 AHCI_PX_CMD_FRE
| AHCI_PX_CMD_FR
)) {
261 g_test_message("port is idle");
263 g_test_message("port needs to be idled");
264 PX_CLR(i
, AHCI_PX_CMD
, (AHCI_PX_CMD_ST
| AHCI_PX_CMD_FRE
));
265 /* The port has 500ms to disengage. */
267 reg
= PX_RREG(i
, AHCI_PX_CMD
);
268 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CR
);
269 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FR
);
270 g_test_message("port is now idle");
271 /* The spec does allow for possibly needing a PORT RESET
272 * or HBA reset if we fail to idle the port. */
275 /* Allocate Memory for the Command List Buffer & FIS Buffer */
276 /* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */
277 clb
= guest_alloc(guest_malloc
, num_cmd_slots
* 0x20);
278 g_test_message("CLB: 0x%08x", clb
);
279 PX_WREG(i
, AHCI_PX_CLB
, clb
);
280 g_assert_cmphex(clb
, ==, PX_RREG(i
, AHCI_PX_CLB
));
282 /* PxFB space ... 0x100, as in 4.2.1 p 35 */
283 fb
= guest_alloc(guest_malloc
, 0x100);
284 g_test_message("FB: 0x%08x", fb
);
285 PX_WREG(i
, AHCI_PX_FB
, fb
);
286 g_assert_cmphex(fb
, ==, PX_RREG(i
, AHCI_PX_FB
));
288 /* Clear PxSERR, PxIS, then IS.IPS[x] by writing '1's. */
289 PX_WREG(i
, AHCI_PX_SERR
, 0xFFFFFFFF);
290 PX_WREG(i
, AHCI_PX_IS
, 0xFFFFFFFF);
291 AHCI_WREG(AHCI_IS
, (1 << i
));
293 /* Verify Interrupts Cleared */
294 reg
= PX_RREG(i
, AHCI_PX_SERR
);
295 g_assert_cmphex(reg
, ==, 0);
297 reg
= PX_RREG(i
, AHCI_PX_IS
);
298 g_assert_cmphex(reg
, ==, 0);
300 reg
= AHCI_RREG(AHCI_IS
);
301 ASSERT_BIT_CLEAR(reg
, (1 << i
));
303 /* Enable All Interrupts: */
304 PX_WREG(i
, AHCI_PX_IE
, 0xFFFFFFFF);
305 reg
= PX_RREG(i
, AHCI_PX_IE
);
306 g_assert_cmphex(reg
, ==, ~((uint32_t)AHCI_PX_IE_RESERVED
));
308 /* Enable the FIS Receive Engine. */
309 PX_SET(i
, AHCI_PX_CMD
, AHCI_PX_CMD_FRE
);
310 reg
= PX_RREG(i
, AHCI_PX_CMD
);
311 ASSERT_BIT_SET(reg
, AHCI_PX_CMD_FR
);
313 /* AHCI 1.3 spec: if !STS.BSY, !STS.DRQ and PxSSTS.DET indicates
314 * physical presence, a device is present and may be started. However,
315 * PxSERR.DIAG.X /may/ need to be cleared a priori. */
316 reg
= PX_RREG(i
, AHCI_PX_SERR
);
317 if (BITSET(reg
, AHCI_PX_SERR_DIAG_X
)) {
318 PX_SET(i
, AHCI_PX_SERR
, AHCI_PX_SERR_DIAG_X
);
321 reg
= PX_RREG(i
, AHCI_PX_TFD
);
322 if (BITCLR(reg
, AHCI_PX_TFD_STS_BSY
| AHCI_PX_TFD_STS_DRQ
)) {
323 reg
= PX_RREG(i
, AHCI_PX_SSTS
);
324 if ((reg
& AHCI_PX_SSTS_DET
) == SSTS_DET_ESTABLISHED
) {
325 /* Device Found: set PxCMD.ST := 1 */
326 PX_SET(i
, AHCI_PX_CMD
, AHCI_PX_CMD_ST
);
327 ASSERT_BIT_SET(PX_RREG(i
, AHCI_PX_CMD
), AHCI_PX_CMD_CR
);
328 g_test_message("Started Device %u", i
);
329 } else if ((reg
& AHCI_PX_SSTS_DET
)) {
330 /* Device present, but in some unknown state. */
331 g_assert_not_reached();
337 AHCI_SET(AHCI_GHC
, AHCI_GHC_IE
);
338 reg
= AHCI_RREG(AHCI_GHC
);
339 ASSERT_BIT_SET(reg
, AHCI_GHC_IE
);
341 /* TODO: The device should now be idling and waiting for commands.
342 * In the future, a small test-case to inspect the Register D2H FIS
343 * and clear the initial interrupts might be good. */
346 /*** Specification Adherence Tests ***/
349 * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
351 static void ahci_test_pci_spec(AHCIQState
*ahci
)
357 /* Most of these bits should start cleared until we turn them on. */
358 data
= qpci_config_readw(ahci
->dev
, PCI_COMMAND
);
359 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MEMORY
);
360 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MASTER
);
361 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SPECIAL
); /* Reserved */
362 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_VGA_PALETTE
); /* Reserved */
363 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_PARITY
);
364 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_WAIT
); /* Reserved */
365 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SERR
);
366 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_FAST_BACK
);
367 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_INTX_DISABLE
);
368 ASSERT_BIT_CLEAR(data
, 0xF800); /* Reserved */
370 data
= qpci_config_readw(ahci
->dev
, PCI_STATUS
);
371 ASSERT_BIT_CLEAR(data
, 0x01 | 0x02 | 0x04); /* Reserved */
372 ASSERT_BIT_CLEAR(data
, PCI_STATUS_INTERRUPT
);
373 ASSERT_BIT_SET(data
, PCI_STATUS_CAP_LIST
); /* must be set */
374 ASSERT_BIT_CLEAR(data
, PCI_STATUS_UDF
); /* Reserved */
375 ASSERT_BIT_CLEAR(data
, PCI_STATUS_PARITY
);
376 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_TARGET_ABORT
);
377 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_TARGET_ABORT
);
378 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_MASTER_ABORT
);
379 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_SYSTEM_ERROR
);
380 ASSERT_BIT_CLEAR(data
, PCI_STATUS_DETECTED_PARITY
);
382 /* RID occupies the low byte, CCs occupy the high three. */
383 datal
= qpci_config_readl(ahci
->dev
, PCI_CLASS_REVISION
);
385 /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
386 * Though in practice this is likely seldom true. */
387 ASSERT_BIT_CLEAR(datal
, 0xFF);
390 /* BCC *must* equal 0x01. */
391 g_assert_cmphex(PCI_BCC(datal
), ==, 0x01);
392 if (PCI_SCC(datal
) == 0x01) {
394 ASSERT_BIT_SET(0x80000000, datal
);
395 ASSERT_BIT_CLEAR(0x60000000, datal
);
396 } else if (PCI_SCC(datal
) == 0x04) {
398 g_assert_cmphex(PCI_PI(datal
), ==, 0);
399 } else if (PCI_SCC(datal
) == 0x06) {
401 g_assert_cmphex(PCI_PI(datal
), ==, 0x01);
403 g_assert_not_reached();
406 datab
= qpci_config_readb(ahci
->dev
, PCI_CACHE_LINE_SIZE
);
407 g_assert_cmphex(datab
, ==, 0);
409 datab
= qpci_config_readb(ahci
->dev
, PCI_LATENCY_TIMER
);
410 g_assert_cmphex(datab
, ==, 0);
412 /* Only the bottom 7 bits must be off. */
413 datab
= qpci_config_readb(ahci
->dev
, PCI_HEADER_TYPE
);
414 ASSERT_BIT_CLEAR(datab
, 0x7F);
416 /* BIST is optional, but the low 7 bits must always start off regardless. */
417 datab
= qpci_config_readb(ahci
->dev
, PCI_BIST
);
418 ASSERT_BIT_CLEAR(datab
, 0x7F);
420 /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
421 datal
= qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
422 g_assert_cmphex(datal
, ==, 0);
424 qpci_config_writel(ahci
->dev
, PCI_BASE_ADDRESS_5
, 0xFFFFFFFF);
425 datal
= qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
426 /* ABAR must be 32-bit, memory mapped, non-prefetchable and
427 * must be >= 512 bytes. To that end, bits 0-8 must be off. */
428 ASSERT_BIT_CLEAR(datal
, 0xFF);
430 /* Capability list MUST be present, */
431 datal
= qpci_config_readl(ahci
->dev
, PCI_CAPABILITY_LIST
);
432 /* But these bits are reserved. */
433 ASSERT_BIT_CLEAR(datal
, ~0xFF);
434 g_assert_cmphex(datal
, !=, 0);
436 /* Check specification adherence for capability extenstions. */
437 data
= qpci_config_readw(ahci
->dev
, datal
);
439 switch (ahci
->fingerprint
) {
440 case AHCI_INTEL_ICH9
:
441 /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
442 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_MSI
);
445 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
446 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_PM
);
449 ahci_test_pci_caps(ahci
, data
, (uint8_t)datal
);
452 datal
= qpci_config_readl(ahci
->dev
, PCI_CAPABILITY_LIST
+ 4);
453 g_assert_cmphex(datal
, ==, 0);
455 /* IPIN might vary, but ILINE must be off. */
456 datab
= qpci_config_readb(ahci
->dev
, PCI_INTERRUPT_LINE
);
457 g_assert_cmphex(datab
, ==, 0);
461 * Test PCI capabilities for AHCI specification adherence.
463 static void ahci_test_pci_caps(AHCIQState
*ahci
, uint16_t header
,
466 uint8_t cid
= header
& 0xFF;
467 uint8_t next
= header
>> 8;
469 g_test_message("CID: %02x; next: %02x", cid
, next
);
473 ahci_test_pmcap(ahci
, offset
);
476 ahci_test_msicap(ahci
, offset
);
478 case PCI_CAP_ID_SATA
:
479 ahci_test_satacap(ahci
, offset
);
483 g_test_message("Unknown CAP 0x%02x", cid
);
487 ahci_test_pci_caps(ahci
, qpci_config_readw(ahci
->dev
, next
), next
);
492 * Test SATA PCI capabilitity for AHCI specification adherence.
494 static void ahci_test_satacap(AHCIQState
*ahci
, uint8_t offset
)
499 g_test_message("Verifying SATACAP");
501 /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
502 dataw
= qpci_config_readw(ahci
->dev
, offset
+ 2);
503 g_assert_cmphex(dataw
, ==, 0x10);
505 /* Grab the SATACR1 register. */
506 datal
= qpci_config_readw(ahci
->dev
, offset
+ 4);
508 switch (datal
& 0x0F) {
509 case 0x04: /* BAR0 */
510 case 0x05: /* BAR1 */
514 case 0x09: /* BAR5 */
515 case 0x0F: /* Immediately following SATACR1 in PCI config space. */
518 /* Invalid BARLOC for the Index Data Pair. */
519 g_assert_not_reached();
523 g_assert_cmphex((datal
>> 24), ==, 0x00);
527 * Test MSI PCI capability for AHCI specification adherence.
529 static void ahci_test_msicap(AHCIQState
*ahci
, uint8_t offset
)
534 g_test_message("Verifying MSICAP");
536 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_FLAGS
);
537 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_ENABLE
);
538 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_QSIZE
);
539 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_RESERVED
);
541 datal
= qpci_config_readl(ahci
->dev
, offset
+ PCI_MSI_ADDRESS_LO
);
542 g_assert_cmphex(datal
, ==, 0);
544 if (dataw
& PCI_MSI_FLAGS_64BIT
) {
545 g_test_message("MSICAP is 64bit");
546 datal
= qpci_config_readl(ahci
->dev
, offset
+ PCI_MSI_ADDRESS_HI
);
547 g_assert_cmphex(datal
, ==, 0);
548 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_DATA_64
);
549 g_assert_cmphex(dataw
, ==, 0);
551 g_test_message("MSICAP is 32bit");
552 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_DATA_32
);
553 g_assert_cmphex(dataw
, ==, 0);
558 * Test Power Management PCI capability for AHCI specification adherence.
560 static void ahci_test_pmcap(AHCIQState
*ahci
, uint8_t offset
)
564 g_test_message("Verifying PMCAP");
566 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_PM_PMC
);
567 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_PME_CLOCK
);
568 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_RESERVED
);
569 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D1
);
570 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D2
);
572 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_PM_CTRL
);
573 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_STATE_MASK
);
574 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_RESERVED
);
575 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SEL_MASK
);
576 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SCALE_MASK
);
579 static void ahci_test_hba_spec(AHCIQState
*ahci
)
587 g_assert(ahci
!= NULL
);
590 * Note that the AHCI spec does expect the BIOS to set up a few things:
591 * CAP.SSS - Support for staggered spin-up (t/f)
592 * CAP.SMPS - Support for mechanical presence switches (t/f)
593 * PI - Ports Implemented (1-32)
594 * PxCMD.HPCP - Hot Plug Capable Port
595 * PxCMD.MPSP - Mechanical Presence Switch Present
596 * PxCMD.CPD - Cold Presence Detection support
598 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
599 * Foreach Port Implemented:
600 * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
601 * -PxCLB/U and PxFB/U are set to valid regions in memory
602 * -PxSUD is set to 1.
603 * -PxSSTS.DET is polled for presence; if detected, we continue:
604 * -PxSERR is cleared with 1's.
605 * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
606 * the device is ready.
609 /* 1 CAP - Capabilities Register */
610 ahci
->cap
= AHCI_RREG(AHCI_CAP
);
611 ASSERT_BIT_CLEAR(ahci
->cap
, AHCI_CAP_RESERVED
);
613 /* 2 GHC - Global Host Control */
614 reg
= AHCI_RREG(AHCI_GHC
);
615 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_HR
);
616 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_IE
);
617 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_MRSM
);
618 if (BITSET(ahci
->cap
, AHCI_CAP_SAM
)) {
619 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
620 ASSERT_BIT_SET(reg
, AHCI_GHC_AE
);
622 g_test_message("Supports AHCI/Legacy mix.");
623 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_AE
);
626 /* 3 IS - Interrupt Status */
627 reg
= AHCI_RREG(AHCI_IS
);
628 g_assert_cmphex(reg
, ==, 0);
630 /* 4 PI - Ports Implemented */
631 ports
= AHCI_RREG(AHCI_PI
);
632 /* Ports Implemented must be non-zero. */
633 g_assert_cmphex(ports
, !=, 0);
634 /* Ports Implemented must be <= Number of Ports. */
635 nports_impl
= ctpopl(ports
);
636 g_assert_cmpuint(((AHCI_CAP_NP
& ahci
->cap
) + 1), >=, nports_impl
);
638 /* Ports must be within the proper range. Given a mapping of SIZE,
639 * 256 bytes are used for global HBA control, and the rest is used
640 * for ports data, at 0x80 bytes each. */
641 g_assert_cmphex(ahci
->barsize
, >, 0);
642 maxports
= (ahci
->barsize
- HBA_DATA_REGION_SIZE
) / HBA_PORT_DATA_SIZE
;
643 /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
644 g_assert_cmphex((reg
>> maxports
), ==, 0);
647 reg
= AHCI_RREG(AHCI_VS
);
649 case AHCI_VERSION_0_95
:
650 case AHCI_VERSION_1_0
:
651 case AHCI_VERSION_1_1
:
652 case AHCI_VERSION_1_2
:
653 case AHCI_VERSION_1_3
:
656 g_assert_not_reached();
659 /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
660 reg
= AHCI_RREG(AHCI_CCCCTL
);
661 if (BITSET(ahci
->cap
, AHCI_CAP_CCCS
)) {
662 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_EN
);
663 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_RESERVED
);
664 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_CC
);
665 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_TV
);
667 g_assert_cmphex(reg
, ==, 0);
671 reg
= AHCI_RREG(AHCI_CCCPORTS
);
672 /* Must be zeroes initially regardless of CAP.CCCS */
673 g_assert_cmphex(reg
, ==, 0);
676 reg
= AHCI_RREG(AHCI_EMLOC
);
677 if (BITCLR(ahci
->cap
, AHCI_CAP_EMS
)) {
678 g_assert_cmphex(reg
, ==, 0);
682 reg
= AHCI_RREG(AHCI_EMCTL
);
683 if (BITSET(ahci
->cap
, AHCI_CAP_EMS
)) {
684 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_STSMR
);
685 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLTM
);
686 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLRST
);
687 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_RESERVED
);
689 g_assert_cmphex(reg
, ==, 0);
692 /* 10 CAP2 -- Capabilities Extended */
693 ahci
->cap2
= AHCI_RREG(AHCI_CAP2
);
694 ASSERT_BIT_CLEAR(ahci
->cap2
, AHCI_CAP2_RESERVED
);
696 /* 11 BOHC -- Bios/OS Handoff Control */
697 reg
= AHCI_RREG(AHCI_BOHC
);
698 g_assert_cmphex(reg
, ==, 0);
700 /* 12 -- 23: Reserved */
701 g_test_message("Verifying HBA reserved area is empty.");
702 for (i
= AHCI_RESERVED
; i
< AHCI_NVMHCI
; ++i
) {
704 g_assert_cmphex(reg
, ==, 0);
707 /* 24 -- 39: NVMHCI */
708 if (BITCLR(ahci
->cap2
, AHCI_CAP2_NVMP
)) {
709 g_test_message("Verifying HBA/NVMHCI area is empty.");
710 for (i
= AHCI_NVMHCI
; i
< AHCI_VENDOR
; ++i
) {
712 g_assert_cmphex(reg
, ==, 0);
716 /* 40 -- 63: Vendor */
717 g_test_message("Verifying HBA/Vendor area is empty.");
718 for (i
= AHCI_VENDOR
; i
< AHCI_PORTS
; ++i
) {
720 g_assert_cmphex(reg
, ==, 0);
723 /* 64 -- XX: Port Space */
724 for (i
= 0; ports
|| (i
< maxports
); ports
>>= 1, ++i
) {
725 if (BITSET(ports
, 0x1)) {
726 g_test_message("Testing port %u for spec", i
);
727 ahci_test_port_spec(ahci
, i
);
730 uint16_t low
= AHCI_PORTS
+ (32 * i
);
731 uint16_t high
= AHCI_PORTS
+ (32 * (i
+ 1));
732 g_test_message("Asserting unimplemented port %u "
733 "(reg [%u-%u]) is empty.",
735 for (j
= low
; j
< high
; ++j
) {
737 g_assert_cmphex(reg
, ==, 0);
744 * Test the memory space for one port for specification adherence.
746 static void ahci_test_port_spec(AHCIQState
*ahci
, uint8_t port
)
752 reg
= PX_RREG(port
, AHCI_PX_CLB
);
753 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CLB_RESERVED
);
756 if (BITCLR(ahci
->cap
, AHCI_CAP_S64A
)) {
757 reg
= PX_RREG(port
, AHCI_PX_CLBU
);
758 g_assert_cmphex(reg
, ==, 0);
762 reg
= PX_RREG(port
, AHCI_PX_FB
);
763 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FB_RESERVED
);
766 if (BITCLR(ahci
->cap
, AHCI_CAP_S64A
)) {
767 reg
= PX_RREG(port
, AHCI_PX_FBU
);
768 g_assert_cmphex(reg
, ==, 0);
772 reg
= PX_RREG(port
, AHCI_PX_IS
);
773 g_assert_cmphex(reg
, ==, 0);
776 reg
= PX_RREG(port
, AHCI_PX_IE
);
777 g_assert_cmphex(reg
, ==, 0);
780 reg
= PX_RREG(port
, AHCI_PX_CMD
);
781 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FRE
);
782 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_RESERVED
);
783 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CCS
);
784 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FR
);
785 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CR
);
786 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_PMA
); /* And RW only if CAP.SPM */
787 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_APSTE
); /* RW only if CAP2.APST */
788 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ATAPI
);
789 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_DLAE
);
790 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ALPE
); /* RW only if CAP.SALP */
791 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ASP
); /* RW only if CAP.SALP */
792 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ICC
);
793 /* If CPDetect support does not exist, CPState must be off. */
794 if (BITCLR(reg
, AHCI_PX_CMD_CPD
)) {
795 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CPS
);
797 /* If MPSPresence is not set, MPSState must be off. */
798 if (BITCLR(reg
, AHCI_PX_CMD_MPSP
)) {
799 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
801 /* If we do not support MPS, MPSS and MPSP must be off. */
802 if (BITCLR(ahci
->cap
, AHCI_CAP_SMPS
)) {
803 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
804 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSP
);
806 /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
807 if (BITANY(reg
, AHCI_PX_CMD_CPD
|| AHCI_PX_CMD_MPSP
)) {
808 ASSERT_BIT_SET(reg
, AHCI_PX_CMD_HPCP
);
810 /* HPCP and ESP cannot both be active. */
811 g_assert(!BITSET(reg
, AHCI_PX_CMD_HPCP
| AHCI_PX_CMD_ESP
));
812 /* If CAP.FBSS is not set, FBSCP must not be set. */
813 if (BITCLR(ahci
->cap
, AHCI_CAP_FBSS
)) {
814 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FBSCP
);
818 reg
= PX_RREG(port
, AHCI_PX_RES1
);
819 g_assert_cmphex(reg
, ==, 0);
822 reg
= PX_RREG(port
, AHCI_PX_TFD
);
823 /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
824 * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
825 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_ERR
);
826 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS1
);
827 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_DRQ
);
828 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS2
);
829 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_STS_BSY
);
830 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_ERR
);
831 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_RESERVED
);
834 /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
835 * Even when GHC.ST is zero, the AHCI HBA may receive the initial
836 * D2H register FIS and update the signature asynchronously,
837 * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
839 /* (10) SSTS / SCR0: SStatus */
840 reg
= PX_RREG(port
, AHCI_PX_SSTS
);
841 ASSERT_BIT_CLEAR(reg
, AHCI_PX_SSTS_RESERVED
);
842 /* Even though the register should be 0 at boot, it is asynchronous and
843 * prone to change, so we cannot test any well known value. */
845 /* (11) SCTL / SCR2: SControl */
846 reg
= PX_RREG(port
, AHCI_PX_SCTL
);
847 g_assert_cmphex(reg
, ==, 0);
849 /* (12) SERR / SCR1: SError */
850 reg
= PX_RREG(port
, AHCI_PX_SERR
);
851 g_assert_cmphex(reg
, ==, 0);
853 /* (13) SACT / SCR3: SActive */
854 reg
= PX_RREG(port
, AHCI_PX_SACT
);
855 g_assert_cmphex(reg
, ==, 0);
858 reg
= PX_RREG(port
, AHCI_PX_CI
);
859 g_assert_cmphex(reg
, ==, 0);
862 reg
= PX_RREG(port
, AHCI_PX_SNTF
);
863 g_assert_cmphex(reg
, ==, 0);
866 reg
= PX_RREG(port
, AHCI_PX_FBS
);
867 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_EN
);
868 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEC
);
869 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_SDE
);
870 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEV
);
871 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DWE
);
872 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_RESERVED
);
873 if (BITSET(ahci
->cap
, AHCI_CAP_FBSS
)) {
874 /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
875 g_assert((reg
& AHCI_PX_FBS_ADO
) >> ctzl(AHCI_PX_FBS_ADO
) >= 2);
878 /* [17 -- 27] RESERVED */
879 for (i
= AHCI_PX_RES2
; i
< AHCI_PX_VS
; ++i
) {
880 reg
= PX_RREG(port
, i
);
881 g_assert_cmphex(reg
, ==, 0);
884 /* [28 -- 31] Vendor-Specific */
885 for (i
= AHCI_PX_VS
; i
< 32; ++i
) {
886 reg
= PX_RREG(port
, i
);
888 g_test_message("INFO: Vendor register %u non-empty", i
);
894 * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
895 * device we see, then read and check the response.
897 static void ahci_test_identify(AHCIQState
*ahci
)
899 RegD2HFIS
*d2h
= g_malloc0(0x20);
900 RegD2HFIS
*pio
= g_malloc0(0x20);
904 uint32_t ports
, reg
, clb
, table
, fb
, data_ptr
;
909 g_assert(ahci
!= NULL
);
912 * (1) Create a Command Table Buffer and update the Command List Slot #0
913 * to point to this buffer.
914 * (2) Construct an FIS host-to-device command structure, and write it to
915 * the top of the command table buffer.
916 * (3) Create a data buffer for the IDENTIFY response to be sent to
917 * (4) Create a Physical Region Descriptor that points to the data buffer,
918 * and write it to the bottom (offset 0x80) of the command table.
919 * (5) Now, PxCLB points to the command list, command 0 points to
920 * our table, and our table contains an FIS instruction and a
921 * PRD that points to our rx buffer.
922 * (6) We inform the HBA via PxCI that there is a command ready in slot #0.
925 /* Pick the first implemented and running port */
926 ports
= AHCI_RREG(AHCI_PI
);
927 for (i
= 0; i
< 32; ports
>>= 1, ++i
) {
932 if (!(ports
& 0x01)) {
936 reg
= PX_RREG(i
, AHCI_PX_CMD
);
937 if (BITSET(reg
, AHCI_PX_CMD_ST
)) {
941 g_assert_cmphex(i
, <, 32);
942 g_test_message("Selected port %u for test", i
);
944 /* Clear out this port's interrupts (ignore the init register d2h fis) */
945 reg
= PX_RREG(i
, AHCI_PX_IS
);
946 PX_WREG(i
, AHCI_PX_IS
, reg
);
947 g_assert_cmphex(PX_RREG(i
, AHCI_PX_IS
), ==, 0);
949 /* Wipe the FIS-Receive Buffer */
950 fb
= PX_RREG(i
, AHCI_PX_FB
);
951 g_assert_cmphex(fb
, !=, 0);
952 qmemset(fb
, 0x00, 0x100);
954 /* Create a Command Table buffer. 0x80 is the smallest with a PRDTL of 0. */
955 /* We need at least one PRD, so round up to the nearest 0x80 multiple. */
956 table
= guest_alloc(guest_malloc
, CMD_TBL_SIZ(1));
958 ASSERT_BIT_CLEAR(table
, 0x7F);
960 /* Create a data buffer ... where we will dump the IDENTIFY data to. */
961 data_ptr
= guest_alloc(guest_malloc
, 512);
964 /* Grab the Command List Buffer pointer */
965 clb
= PX_RREG(i
, AHCI_PX_CLB
);
968 /* Copy the existing Command #0 structure from the CLB into local memory,
969 * and build a new command #0. */
970 memread(clb
, &cmd
, sizeof(cmd
));
971 cmd
.b1
= 5; /* reg_h2d_fis is 5 double-words long */
972 cmd
.b2
= 0x04; /* clear PxTFD.STS.BSY when done */
973 cmd
.prdtl
= cpu_to_le16(1); /* One PRD table entry. */
975 cmd
.ctba
= cpu_to_le32(table
);
978 /* Construct our PRD, noting that DBC is 0-indexed. */
979 prd
.dba
= cpu_to_le32(data_ptr
);
982 /* 511+1 bytes, request DPS interrupt */
983 prd
.dbc
= cpu_to_le32(511 | 0x80000000);
985 /* Construct our Command FIS, Based on http://wiki.osdev.org/AHCI */
986 memset(&fis
, 0x00, sizeof(fis
));
987 fis
.fis_type
= 0x27; /* Register Host-to-Device FIS */
988 fis
.command
= 0xEC; /* IDENTIFY */
990 fis
.flags
= 0x80; /* Indicate this is a command FIS */
992 /* We've committed nothing yet, no interrupts should be posted yet. */
993 g_assert_cmphex(PX_RREG(i
, AHCI_PX_IS
), ==, 0);
995 /* Commit the Command FIS to the Command Table */
996 memwrite(table
, &fis
, sizeof(fis
));
998 /* Commit the PRD entry to the Command Table */
999 memwrite(table
+ 0x80, &prd
, sizeof(prd
));
1001 /* Commit Command #0, pointing to the Table, to the Command List Buffer. */
1002 memwrite(clb
, &cmd
, sizeof(cmd
));
1004 /* Everything is in place, but we haven't given the go-ahead yet. */
1005 g_assert_cmphex(PX_RREG(i
, AHCI_PX_IS
), ==, 0);
1007 /* Issue Command #0 via PxCI */
1008 PX_WREG(i
, AHCI_PX_CI
, (1 << 0));
1009 while (BITSET(PX_RREG(i
, AHCI_PX_TFD
), AHCI_PX_TFD_STS_BSY
)) {
1013 /* Check for expected interrupts */
1014 reg
= PX_RREG(i
, AHCI_PX_IS
);
1015 ASSERT_BIT_SET(reg
, AHCI_PX_IS_DHRS
);
1016 ASSERT_BIT_SET(reg
, AHCI_PX_IS_PSS
);
1017 /* BUG: we expect AHCI_PX_IS_DPS to be set. */
1018 ASSERT_BIT_CLEAR(reg
, AHCI_PX_IS_DPS
);
1020 /* Clear expected interrupts and assert all interrupts now cleared. */
1021 PX_WREG(i
, AHCI_PX_IS
, AHCI_PX_IS_DHRS
| AHCI_PX_IS_PSS
| AHCI_PX_IS_DPS
);
1022 g_assert_cmphex(PX_RREG(i
, AHCI_PX_IS
), ==, 0);
1024 /* Check for errors. */
1025 reg
= PX_RREG(i
, AHCI_PX_SERR
);
1026 g_assert_cmphex(reg
, ==, 0);
1027 reg
= PX_RREG(i
, AHCI_PX_TFD
);
1028 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_STS_ERR
);
1029 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_ERR
);
1031 /* Investigate CMD #0, assert that we read 512 bytes */
1032 memread(clb
, &cmd
, sizeof(cmd
));
1033 g_assert_cmphex(512, ==, le32_to_cpu(cmd
.prdbc
));
1035 /* Investigate FIS responses */
1036 memread(fb
+ 0x20, pio
, 0x20);
1037 memread(fb
+ 0x40, d2h
, 0x20);
1038 g_assert_cmphex(pio
->fis_type
, ==, 0x5f);
1039 g_assert_cmphex(d2h
->fis_type
, ==, 0x34);
1040 g_assert_cmphex(pio
->flags
, ==, d2h
->flags
);
1041 g_assert_cmphex(pio
->status
, ==, d2h
->status
);
1042 g_assert_cmphex(pio
->error
, ==, d2h
->error
);
1044 reg
= PX_RREG(i
, AHCI_PX_TFD
);
1045 g_assert_cmphex((reg
& AHCI_PX_TFD_ERR
), ==, pio
->error
);
1046 g_assert_cmphex((reg
& AHCI_PX_TFD_STS
), ==, pio
->status
);
1047 /* The PIO Setup FIS contains a "bytes read" field, which is a
1048 * 16-bit value. The Physical Region Descriptor Byte Count is
1049 * 32-bit, but for small transfers using one PRD, it should match. */
1050 g_assert_cmphex(le16_to_cpu(pio
->res4
), ==, le32_to_cpu(cmd
.prdbc
));
1052 /* Last, but not least: Investigate the IDENTIFY response data. */
1053 memread(data_ptr
, &buff
, 512);
1055 /* Check serial number/version in the buffer */
1056 /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
1057 * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
1058 * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
1059 * as a consequence, only needs to unchunk the data on LE machines. */
1060 string_bswap16(&buff
[10], 20);
1061 rc
= memcmp(&buff
[10], "testdisk ", 20);
1062 g_assert_cmphex(rc
, ==, 0);
1064 string_bswap16(&buff
[23], 8);
1065 rc
= memcmp(&buff
[23], "version ", 8);
1066 g_assert_cmphex(rc
, ==, 0);
1072 /******************************************************************************/
1073 /* Test Interfaces */
1074 /******************************************************************************/
1077 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
1079 static void test_sanity(void)
1083 ahci_shutdown(ahci
);
1087 * Ensure that the PCI configuration space for the AHCI device is in-line with
1088 * the AHCI 1.3 specification for initial values.
1090 static void test_pci_spec(void)
1094 ahci_test_pci_spec(ahci
);
1095 ahci_shutdown(ahci
);
1099 * Engage the PCI AHCI device and sanity check the response.
1100 * Perform additional PCI config space bringup for the HBA.
1102 static void test_pci_enable(void)
1107 ahci_pci_enable(ahci
);
1108 ahci_shutdown(ahci
);
1112 * Investigate the memory mapped regions of the HBA,
1113 * and test them for AHCI specification adherence.
1115 static void test_hba_spec(void)
1120 ahci_pci_enable(ahci
);
1121 ahci_test_hba_spec(ahci
);
1122 ahci_shutdown(ahci
);
1126 * Engage the HBA functionality of the AHCI PCI device,
1127 * and bring it into a functional idle state.
1129 static void test_hba_enable(void)
1134 ahci_pci_enable(ahci
);
1135 ahci_hba_enable(ahci
);
1136 ahci_shutdown(ahci
);
1140 * Bring up the device and issue an IDENTIFY command.
1141 * Inspect the state of the HBA device and the data returned.
1143 static void test_identify(void)
1148 ahci_pci_enable(ahci
);
1149 ahci_hba_enable(ahci
);
1150 ahci_test_identify(ahci
);
1151 ahci_shutdown(ahci
);
1154 /******************************************************************************/
1156 int main(int argc
, char **argv
)
1163 static struct option long_options
[] = {
1164 {"pedantic", no_argument
, 0, 'p' },
1168 /* Should be first to utilize g_test functionality, So we can see errors. */
1169 g_test_init(&argc
, &argv
, NULL
);
1172 c
= getopt_long(argc
, argv
, "", long_options
, NULL
);
1183 fprintf(stderr
, "Unrecognized ahci_test option.\n");
1184 g_assert_not_reached();
1188 /* Check architecture */
1189 arch
= qtest_get_arch();
1190 if (strcmp(arch
, "i386") && strcmp(arch
, "x86_64")) {
1191 g_test_message("Skipping test for non-x86");
1195 /* Create a temporary raw image */
1196 fd
= mkstemp(tmp_path
);
1198 ret
= ftruncate(fd
, TEST_IMAGE_SIZE
);
1203 qtest_add_func("/ahci/sanity", test_sanity
);
1204 qtest_add_func("/ahci/pci_spec", test_pci_spec
);
1205 qtest_add_func("/ahci/pci_enable", test_pci_enable
);
1206 qtest_add_func("/ahci/hba_spec", test_hba_spec
);
1207 qtest_add_func("/ahci/hba_enable", test_hba_enable
);
1208 qtest_add_func("/ahci/identify", test_identify
);