4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 #include "libqos/libqos-pc.h"
33 #include "libqos/ahci.h"
34 #include "libqos/pci-pc.h"
35 #include "libqos/malloc-pc.h"
37 #include "qemu-common.h"
38 #include "qemu/host-utils.h"
40 #include "hw/pci/pci_ids.h"
41 #include "hw/pci/pci_regs.h"
43 /* Test-specific defines. */
44 #define TEST_IMAGE_SIZE (64 * 1024 * 1024)
47 static QGuestAllocator
*guest_malloc
;
48 static QPCIBus
*pcibus
;
49 static uint64_t barsize
;
50 static char tmp_path
[] = "/tmp/qtest.XXXXXX";
51 static bool ahci_pedantic
;
52 static uint32_t ahci_fingerprint
;
54 /*** IO macros for the AHCI memory registers. ***/
55 #define AHCI_READ(OFST) qpci_io_readl(ahci, hba_base + (OFST))
56 #define AHCI_WRITE(OFST, VAL) qpci_io_writel(ahci, hba_base + (OFST), (VAL))
57 #define AHCI_RREG(regno) AHCI_READ(4 * (regno))
58 #define AHCI_WREG(regno, val) AHCI_WRITE(4 * (regno), (val))
59 #define AHCI_SET(regno, mask) AHCI_WREG((regno), AHCI_RREG(regno) | (mask))
60 #define AHCI_CLR(regno, mask) AHCI_WREG((regno), AHCI_RREG(regno) & ~(mask))
62 /*** IO macros for port-specific offsets inside of AHCI memory. ***/
63 #define PX_OFST(port, regno) (HBA_PORT_NUM_REG * (port) + AHCI_PORTS + (regno))
64 #define PX_RREG(port, regno) AHCI_RREG(PX_OFST((port), (regno)))
65 #define PX_WREG(port, regno, val) AHCI_WREG(PX_OFST((port), (regno)), (val))
66 #define PX_SET(port, reg, mask) PX_WREG((port), (reg), \
67 PX_RREG((port), (reg)) | (mask));
68 #define PX_CLR(port, reg, mask) PX_WREG((port), (reg), \
69 PX_RREG((port), (reg)) & ~(mask));
71 /*** Function Declarations ***/
72 static QPCIDevice
*get_ahci_device(void);
73 static QPCIDevice
*start_ahci_device(QPCIDevice
*dev
, void **hba_base
);
74 static void free_ahci_device(QPCIDevice
*dev
);
75 static void ahci_test_port_spec(QPCIDevice
*ahci
, void *hba_base
,
76 HBACap
*hcap
, uint8_t port
);
77 static void ahci_test_pci_spec(QPCIDevice
*ahci
);
78 static void ahci_test_pci_caps(QPCIDevice
*ahci
, uint16_t header
,
80 static void ahci_test_satacap(QPCIDevice
*ahci
, uint8_t offset
);
81 static void ahci_test_msicap(QPCIDevice
*ahci
, uint8_t offset
);
82 static void ahci_test_pmcap(QPCIDevice
*ahci
, uint8_t offset
);
86 static void string_bswap16(uint16_t *s
, size_t bytes
)
88 g_assert_cmphex((bytes
& 1), ==, 0);
98 * Locate, verify, and return a handle to the AHCI device.
100 static QPCIDevice
*get_ahci_device(void)
104 pcibus
= qpci_init_pc();
106 /* Find the AHCI PCI device and verify it's the right one. */
107 ahci
= qpci_device_find(pcibus
, QPCI_DEVFN(0x1F, 0x02));
108 g_assert(ahci
!= NULL
);
110 ahci_fingerprint
= qpci_config_readl(ahci
, PCI_VENDOR_ID
);
112 switch (ahci_fingerprint
) {
113 case AHCI_INTEL_ICH9
:
116 /* Unknown device. */
117 g_assert_not_reached();
123 static void free_ahci_device(QPCIDevice
*ahci
)
125 /* libqos doesn't have a function for this, so free it manually */
129 qpci_free_pc(pcibus
);
133 /* Clear our cached barsize information. */
137 /*** Test Setup & Teardown ***/
140 * Start a Q35 machine and bookmark a handle to the AHCI device.
142 static AHCIQState
*ahci_boot(void)
147 s
= g_malloc0(sizeof(AHCIQState
));
149 cli
= "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
152 "-device ide-hd,drive=drive0 "
153 "-global ide-hd.ver=%s";
154 s
->parent
= qtest_pc_boot(cli
, tmp_path
, "testdisk", "version");
156 /* Verify that we have an AHCI device present. */
157 s
->dev
= get_ahci_device();
159 /* Stopgap: Copy the allocator reference */
160 guest_malloc
= s
->parent
->alloc
;
166 * Clean up the PCI device, then terminate the QEMU instance.
168 static void ahci_shutdown(AHCIQState
*ahci
)
170 QOSState
*qs
= ahci
->parent
;
171 free_ahci_device(ahci
->dev
);
176 /*** Logical Device Initialization ***/
179 * Start the PCI device and sanity-check default operation.
181 static void ahci_pci_enable(QPCIDevice
*ahci
, void **hba_base
)
185 start_ahci_device(ahci
, hba_base
);
187 switch (ahci_fingerprint
) {
188 case AHCI_INTEL_ICH9
:
189 /* ICH9 has a register at PCI 0x92 that
190 * acts as a master port enabler mask. */
191 reg
= qpci_config_readb(ahci
, 0x92);
193 qpci_config_writeb(ahci
, 0x92, reg
);
194 /* 0...0111111b -- bit significant, ports 0-5 enabled. */
195 ASSERT_BIT_SET(qpci_config_readb(ahci
, 0x92), 0x3F);
202 * Map BAR5/ABAR, and engage the PCI device.
204 static QPCIDevice
*start_ahci_device(QPCIDevice
*ahci
, void **hba_base
)
206 /* Map AHCI's ABAR (BAR5) */
207 *hba_base
= qpci_iomap(ahci
, 5, &barsize
);
209 /* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */
210 qpci_device_enable(ahci
);
216 * Test and initialize the AHCI's HBA memory areas.
217 * Initialize and start any ports with devices attached.
218 * Bring the HBA into the idle state.
220 static void ahci_hba_enable(QPCIDevice
*ahci
, void *hba_base
)
222 /* Bits of interest in this section:
223 * GHC.AE Global Host Control / AHCI Enable
224 * PxCMD.ST Port Command: Start
225 * PxCMD.SUD "Spin Up Device"
226 * PxCMD.POD "Power On Device"
227 * PxCMD.FRE "FIS Receive Enable"
228 * PxCMD.FR "FIS Receive Running"
229 * PxCMD.CR "Command List Running"
232 g_assert(ahci
!= NULL
);
233 g_assert(hba_base
!= NULL
);
235 uint32_t reg
, ports_impl
, clb
, fb
;
237 uint8_t num_cmd_slots
;
239 g_assert(hba_base
!= 0);
241 /* Set GHC.AE to 1 */
242 AHCI_SET(AHCI_GHC
, AHCI_GHC_AE
);
243 reg
= AHCI_RREG(AHCI_GHC
);
244 ASSERT_BIT_SET(reg
, AHCI_GHC_AE
);
246 /* Read CAP.NCS, how many command slots do we have? */
247 reg
= AHCI_RREG(AHCI_CAP
);
248 num_cmd_slots
= ((reg
& AHCI_CAP_NCS
) >> ctzl(AHCI_CAP_NCS
)) + 1;
249 g_test_message("Number of Command Slots: %u", num_cmd_slots
);
251 /* Determine which ports are implemented. */
252 ports_impl
= AHCI_RREG(AHCI_PI
);
254 for (i
= 0; ports_impl
; ports_impl
>>= 1, ++i
) {
255 if (!(ports_impl
& 0x01)) {
259 g_test_message("Initializing port %u", i
);
261 reg
= PX_RREG(i
, AHCI_PX_CMD
);
262 if (BITCLR(reg
, AHCI_PX_CMD_ST
| AHCI_PX_CMD_CR
|
263 AHCI_PX_CMD_FRE
| AHCI_PX_CMD_FR
)) {
264 g_test_message("port is idle");
266 g_test_message("port needs to be idled");
267 PX_CLR(i
, AHCI_PX_CMD
, (AHCI_PX_CMD_ST
| AHCI_PX_CMD_FRE
));
268 /* The port has 500ms to disengage. */
270 reg
= PX_RREG(i
, AHCI_PX_CMD
);
271 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CR
);
272 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FR
);
273 g_test_message("port is now idle");
274 /* The spec does allow for possibly needing a PORT RESET
275 * or HBA reset if we fail to idle the port. */
278 /* Allocate Memory for the Command List Buffer & FIS Buffer */
279 /* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */
280 clb
= guest_alloc(guest_malloc
, num_cmd_slots
* 0x20);
281 g_test_message("CLB: 0x%08x", clb
);
282 PX_WREG(i
, AHCI_PX_CLB
, clb
);
283 g_assert_cmphex(clb
, ==, PX_RREG(i
, AHCI_PX_CLB
));
285 /* PxFB space ... 0x100, as in 4.2.1 p 35 */
286 fb
= guest_alloc(guest_malloc
, 0x100);
287 g_test_message("FB: 0x%08x", fb
);
288 PX_WREG(i
, AHCI_PX_FB
, fb
);
289 g_assert_cmphex(fb
, ==, PX_RREG(i
, AHCI_PX_FB
));
291 /* Clear PxSERR, PxIS, then IS.IPS[x] by writing '1's. */
292 PX_WREG(i
, AHCI_PX_SERR
, 0xFFFFFFFF);
293 PX_WREG(i
, AHCI_PX_IS
, 0xFFFFFFFF);
294 AHCI_WREG(AHCI_IS
, (1 << i
));
296 /* Verify Interrupts Cleared */
297 reg
= PX_RREG(i
, AHCI_PX_SERR
);
298 g_assert_cmphex(reg
, ==, 0);
300 reg
= PX_RREG(i
, AHCI_PX_IS
);
301 g_assert_cmphex(reg
, ==, 0);
303 reg
= AHCI_RREG(AHCI_IS
);
304 ASSERT_BIT_CLEAR(reg
, (1 << i
));
306 /* Enable All Interrupts: */
307 PX_WREG(i
, AHCI_PX_IE
, 0xFFFFFFFF);
308 reg
= PX_RREG(i
, AHCI_PX_IE
);
309 g_assert_cmphex(reg
, ==, ~((uint32_t)AHCI_PX_IE_RESERVED
));
311 /* Enable the FIS Receive Engine. */
312 PX_SET(i
, AHCI_PX_CMD
, AHCI_PX_CMD_FRE
);
313 reg
= PX_RREG(i
, AHCI_PX_CMD
);
314 ASSERT_BIT_SET(reg
, AHCI_PX_CMD_FR
);
316 /* AHCI 1.3 spec: if !STS.BSY, !STS.DRQ and PxSSTS.DET indicates
317 * physical presence, a device is present and may be started. However,
318 * PxSERR.DIAG.X /may/ need to be cleared a priori. */
319 reg
= PX_RREG(i
, AHCI_PX_SERR
);
320 if (BITSET(reg
, AHCI_PX_SERR_DIAG_X
)) {
321 PX_SET(i
, AHCI_PX_SERR
, AHCI_PX_SERR_DIAG_X
);
324 reg
= PX_RREG(i
, AHCI_PX_TFD
);
325 if (BITCLR(reg
, AHCI_PX_TFD_STS_BSY
| AHCI_PX_TFD_STS_DRQ
)) {
326 reg
= PX_RREG(i
, AHCI_PX_SSTS
);
327 if ((reg
& AHCI_PX_SSTS_DET
) == SSTS_DET_ESTABLISHED
) {
328 /* Device Found: set PxCMD.ST := 1 */
329 PX_SET(i
, AHCI_PX_CMD
, AHCI_PX_CMD_ST
);
330 ASSERT_BIT_SET(PX_RREG(i
, AHCI_PX_CMD
), AHCI_PX_CMD_CR
);
331 g_test_message("Started Device %u", i
);
332 } else if ((reg
& AHCI_PX_SSTS_DET
)) {
333 /* Device present, but in some unknown state. */
334 g_assert_not_reached();
340 AHCI_SET(AHCI_GHC
, AHCI_GHC_IE
);
341 reg
= AHCI_RREG(AHCI_GHC
);
342 ASSERT_BIT_SET(reg
, AHCI_GHC_IE
);
344 /* TODO: The device should now be idling and waiting for commands.
345 * In the future, a small test-case to inspect the Register D2H FIS
346 * and clear the initial interrupts might be good. */
349 /*** Specification Adherence Tests ***/
352 * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
354 static void ahci_test_pci_spec(QPCIDevice
*ahci
)
360 /* Most of these bits should start cleared until we turn them on. */
361 data
= qpci_config_readw(ahci
, PCI_COMMAND
);
362 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MEMORY
);
363 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MASTER
);
364 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SPECIAL
); /* Reserved */
365 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_VGA_PALETTE
); /* Reserved */
366 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_PARITY
);
367 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_WAIT
); /* Reserved */
368 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SERR
);
369 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_FAST_BACK
);
370 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_INTX_DISABLE
);
371 ASSERT_BIT_CLEAR(data
, 0xF800); /* Reserved */
373 data
= qpci_config_readw(ahci
, PCI_STATUS
);
374 ASSERT_BIT_CLEAR(data
, 0x01 | 0x02 | 0x04); /* Reserved */
375 ASSERT_BIT_CLEAR(data
, PCI_STATUS_INTERRUPT
);
376 ASSERT_BIT_SET(data
, PCI_STATUS_CAP_LIST
); /* must be set */
377 ASSERT_BIT_CLEAR(data
, PCI_STATUS_UDF
); /* Reserved */
378 ASSERT_BIT_CLEAR(data
, PCI_STATUS_PARITY
);
379 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_TARGET_ABORT
);
380 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_TARGET_ABORT
);
381 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_MASTER_ABORT
);
382 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_SYSTEM_ERROR
);
383 ASSERT_BIT_CLEAR(data
, PCI_STATUS_DETECTED_PARITY
);
385 /* RID occupies the low byte, CCs occupy the high three. */
386 datal
= qpci_config_readl(ahci
, PCI_CLASS_REVISION
);
388 /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
389 * Though in practice this is likely seldom true. */
390 ASSERT_BIT_CLEAR(datal
, 0xFF);
393 /* BCC *must* equal 0x01. */
394 g_assert_cmphex(PCI_BCC(datal
), ==, 0x01);
395 if (PCI_SCC(datal
) == 0x01) {
397 ASSERT_BIT_SET(0x80000000, datal
);
398 ASSERT_BIT_CLEAR(0x60000000, datal
);
399 } else if (PCI_SCC(datal
) == 0x04) {
401 g_assert_cmphex(PCI_PI(datal
), ==, 0);
402 } else if (PCI_SCC(datal
) == 0x06) {
404 g_assert_cmphex(PCI_PI(datal
), ==, 0x01);
406 g_assert_not_reached();
409 datab
= qpci_config_readb(ahci
, PCI_CACHE_LINE_SIZE
);
410 g_assert_cmphex(datab
, ==, 0);
412 datab
= qpci_config_readb(ahci
, PCI_LATENCY_TIMER
);
413 g_assert_cmphex(datab
, ==, 0);
415 /* Only the bottom 7 bits must be off. */
416 datab
= qpci_config_readb(ahci
, PCI_HEADER_TYPE
);
417 ASSERT_BIT_CLEAR(datab
, 0x7F);
419 /* BIST is optional, but the low 7 bits must always start off regardless. */
420 datab
= qpci_config_readb(ahci
, PCI_BIST
);
421 ASSERT_BIT_CLEAR(datab
, 0x7F);
423 /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
424 datal
= qpci_config_readl(ahci
, PCI_BASE_ADDRESS_5
);
425 g_assert_cmphex(datal
, ==, 0);
427 qpci_config_writel(ahci
, PCI_BASE_ADDRESS_5
, 0xFFFFFFFF);
428 datal
= qpci_config_readl(ahci
, PCI_BASE_ADDRESS_5
);
429 /* ABAR must be 32-bit, memory mapped, non-prefetchable and
430 * must be >= 512 bytes. To that end, bits 0-8 must be off. */
431 ASSERT_BIT_CLEAR(datal
, 0xFF);
433 /* Capability list MUST be present, */
434 datal
= qpci_config_readl(ahci
, PCI_CAPABILITY_LIST
);
435 /* But these bits are reserved. */
436 ASSERT_BIT_CLEAR(datal
, ~0xFF);
437 g_assert_cmphex(datal
, !=, 0);
439 /* Check specification adherence for capability extenstions. */
440 data
= qpci_config_readw(ahci
, datal
);
442 switch (ahci_fingerprint
) {
443 case AHCI_INTEL_ICH9
:
444 /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
445 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_MSI
);
448 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
449 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_PM
);
452 ahci_test_pci_caps(ahci
, data
, (uint8_t)datal
);
455 datal
= qpci_config_readl(ahci
, PCI_CAPABILITY_LIST
+ 4);
456 g_assert_cmphex(datal
, ==, 0);
458 /* IPIN might vary, but ILINE must be off. */
459 datab
= qpci_config_readb(ahci
, PCI_INTERRUPT_LINE
);
460 g_assert_cmphex(datab
, ==, 0);
464 * Test PCI capabilities for AHCI specification adherence.
466 static void ahci_test_pci_caps(QPCIDevice
*ahci
, uint16_t header
,
469 uint8_t cid
= header
& 0xFF;
470 uint8_t next
= header
>> 8;
472 g_test_message("CID: %02x; next: %02x", cid
, next
);
476 ahci_test_pmcap(ahci
, offset
);
479 ahci_test_msicap(ahci
, offset
);
481 case PCI_CAP_ID_SATA
:
482 ahci_test_satacap(ahci
, offset
);
486 g_test_message("Unknown CAP 0x%02x", cid
);
490 ahci_test_pci_caps(ahci
, qpci_config_readw(ahci
, next
), next
);
495 * Test SATA PCI capabilitity for AHCI specification adherence.
497 static void ahci_test_satacap(QPCIDevice
*ahci
, uint8_t offset
)
502 g_test_message("Verifying SATACAP");
504 /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
505 dataw
= qpci_config_readw(ahci
, offset
+ 2);
506 g_assert_cmphex(dataw
, ==, 0x10);
508 /* Grab the SATACR1 register. */
509 datal
= qpci_config_readw(ahci
, offset
+ 4);
511 switch (datal
& 0x0F) {
512 case 0x04: /* BAR0 */
513 case 0x05: /* BAR1 */
517 case 0x09: /* BAR5 */
518 case 0x0F: /* Immediately following SATACR1 in PCI config space. */
521 /* Invalid BARLOC for the Index Data Pair. */
522 g_assert_not_reached();
526 g_assert_cmphex((datal
>> 24), ==, 0x00);
530 * Test MSI PCI capability for AHCI specification adherence.
532 static void ahci_test_msicap(QPCIDevice
*ahci
, uint8_t offset
)
537 g_test_message("Verifying MSICAP");
539 dataw
= qpci_config_readw(ahci
, offset
+ PCI_MSI_FLAGS
);
540 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_ENABLE
);
541 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_QSIZE
);
542 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_RESERVED
);
544 datal
= qpci_config_readl(ahci
, offset
+ PCI_MSI_ADDRESS_LO
);
545 g_assert_cmphex(datal
, ==, 0);
547 if (dataw
& PCI_MSI_FLAGS_64BIT
) {
548 g_test_message("MSICAP is 64bit");
549 datal
= qpci_config_readl(ahci
, offset
+ PCI_MSI_ADDRESS_HI
);
550 g_assert_cmphex(datal
, ==, 0);
551 dataw
= qpci_config_readw(ahci
, offset
+ PCI_MSI_DATA_64
);
552 g_assert_cmphex(dataw
, ==, 0);
554 g_test_message("MSICAP is 32bit");
555 dataw
= qpci_config_readw(ahci
, offset
+ PCI_MSI_DATA_32
);
556 g_assert_cmphex(dataw
, ==, 0);
561 * Test Power Management PCI capability for AHCI specification adherence.
563 static void ahci_test_pmcap(QPCIDevice
*ahci
, uint8_t offset
)
567 g_test_message("Verifying PMCAP");
569 dataw
= qpci_config_readw(ahci
, offset
+ PCI_PM_PMC
);
570 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_PME_CLOCK
);
571 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_RESERVED
);
572 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D1
);
573 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D2
);
575 dataw
= qpci_config_readw(ahci
, offset
+ PCI_PM_CTRL
);
576 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_STATE_MASK
);
577 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_RESERVED
);
578 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SEL_MASK
);
579 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SCALE_MASK
);
582 static void ahci_test_hba_spec(QPCIDevice
*ahci
, void *hba_base
)
586 uint32_t cap
, cap2
, reg
;
592 g_assert(hba_base
!= 0);
595 * Note that the AHCI spec does expect the BIOS to set up a few things:
596 * CAP.SSS - Support for staggered spin-up (t/f)
597 * CAP.SMPS - Support for mechanical presence switches (t/f)
598 * PI - Ports Implemented (1-32)
599 * PxCMD.HPCP - Hot Plug Capable Port
600 * PxCMD.MPSP - Mechanical Presence Switch Present
601 * PxCMD.CPD - Cold Presence Detection support
603 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
604 * Foreach Port Implemented:
605 * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
606 * -PxCLB/U and PxFB/U are set to valid regions in memory
607 * -PxSUD is set to 1.
608 * -PxSSTS.DET is polled for presence; if detected, we continue:
609 * -PxSERR is cleared with 1's.
610 * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
611 * the device is ready.
614 /* 1 CAP - Capabilities Register */
615 cap
= AHCI_RREG(AHCI_CAP
);
616 ASSERT_BIT_CLEAR(cap
, AHCI_CAP_RESERVED
);
618 /* 2 GHC - Global Host Control */
619 reg
= AHCI_RREG(AHCI_GHC
);
620 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_HR
);
621 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_IE
);
622 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_MRSM
);
623 if (BITSET(cap
, AHCI_CAP_SAM
)) {
624 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
625 ASSERT_BIT_SET(reg
, AHCI_GHC_AE
);
627 g_test_message("Supports AHCI/Legacy mix.");
628 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_AE
);
631 /* 3 IS - Interrupt Status */
632 reg
= AHCI_RREG(AHCI_IS
);
633 g_assert_cmphex(reg
, ==, 0);
635 /* 4 PI - Ports Implemented */
636 ports
= AHCI_RREG(AHCI_PI
);
637 /* Ports Implemented must be non-zero. */
638 g_assert_cmphex(ports
, !=, 0);
639 /* Ports Implemented must be <= Number of Ports. */
640 nports_impl
= ctpopl(ports
);
641 g_assert_cmpuint(((AHCI_CAP_NP
& cap
) + 1), >=, nports_impl
);
643 g_assert_cmphex(barsize
, >, 0);
644 /* Ports must be within the proper range. Given a mapping of SIZE,
645 * 256 bytes are used for global HBA control, and the rest is used
646 * for ports data, at 0x80 bytes each. */
647 maxports
= (barsize
- HBA_DATA_REGION_SIZE
) / HBA_PORT_DATA_SIZE
;
648 /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
649 g_assert_cmphex((reg
>> maxports
), ==, 0);
652 reg
= AHCI_RREG(AHCI_VS
);
654 case AHCI_VERSION_0_95
:
655 case AHCI_VERSION_1_0
:
656 case AHCI_VERSION_1_1
:
657 case AHCI_VERSION_1_2
:
658 case AHCI_VERSION_1_3
:
661 g_assert_not_reached();
664 /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
665 reg
= AHCI_RREG(AHCI_CCCCTL
);
666 if (BITSET(cap
, AHCI_CAP_CCCS
)) {
667 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_EN
);
668 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_RESERVED
);
669 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_CC
);
670 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_TV
);
672 g_assert_cmphex(reg
, ==, 0);
676 reg
= AHCI_RREG(AHCI_CCCPORTS
);
677 /* Must be zeroes initially regardless of CAP.CCCS */
678 g_assert_cmphex(reg
, ==, 0);
681 reg
= AHCI_RREG(AHCI_EMLOC
);
682 if (BITCLR(cap
, AHCI_CAP_EMS
)) {
683 g_assert_cmphex(reg
, ==, 0);
687 reg
= AHCI_RREG(AHCI_EMCTL
);
688 if (BITSET(cap
, AHCI_CAP_EMS
)) {
689 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_STSMR
);
690 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLTM
);
691 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLRST
);
692 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_RESERVED
);
694 g_assert_cmphex(reg
, ==, 0);
697 /* 10 CAP2 -- Capabilities Extended */
698 cap2
= AHCI_RREG(AHCI_CAP2
);
699 ASSERT_BIT_CLEAR(cap2
, AHCI_CAP2_RESERVED
);
701 /* 11 BOHC -- Bios/OS Handoff Control */
702 reg
= AHCI_RREG(AHCI_BOHC
);
703 g_assert_cmphex(reg
, ==, 0);
705 /* 12 -- 23: Reserved */
706 g_test_message("Verifying HBA reserved area is empty.");
707 for (i
= AHCI_RESERVED
; i
< AHCI_NVMHCI
; ++i
) {
709 g_assert_cmphex(reg
, ==, 0);
712 /* 24 -- 39: NVMHCI */
713 if (BITCLR(cap2
, AHCI_CAP2_NVMP
)) {
714 g_test_message("Verifying HBA/NVMHCI area is empty.");
715 for (i
= AHCI_NVMHCI
; i
< AHCI_VENDOR
; ++i
) {
717 g_assert_cmphex(reg
, ==, 0);
721 /* 40 -- 63: Vendor */
722 g_test_message("Verifying HBA/Vendor area is empty.");
723 for (i
= AHCI_VENDOR
; i
< AHCI_PORTS
; ++i
) {
725 g_assert_cmphex(reg
, ==, 0);
728 /* 64 -- XX: Port Space */
731 for (i
= 0; ports
|| (i
< maxports
); ports
>>= 1, ++i
) {
732 if (BITSET(ports
, 0x1)) {
733 g_test_message("Testing port %u for spec", i
);
734 ahci_test_port_spec(ahci
, hba_base
, &hcap
, i
);
737 uint16_t low
= AHCI_PORTS
+ (32 * i
);
738 uint16_t high
= AHCI_PORTS
+ (32 * (i
+ 1));
739 g_test_message("Asserting unimplemented port %u "
740 "(reg [%u-%u]) is empty.",
742 for (j
= low
; j
< high
; ++j
) {
744 g_assert_cmphex(reg
, ==, 0);
751 * Test the memory space for one port for specification adherence.
753 static void ahci_test_port_spec(QPCIDevice
*ahci
, void *hba_base
,
754 HBACap
*hcap
, uint8_t port
)
760 reg
= PX_RREG(port
, AHCI_PX_CLB
);
761 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CLB_RESERVED
);
764 if (BITCLR(hcap
->cap
, AHCI_CAP_S64A
)) {
765 reg
= PX_RREG(port
, AHCI_PX_CLBU
);
766 g_assert_cmphex(reg
, ==, 0);
770 reg
= PX_RREG(port
, AHCI_PX_FB
);
771 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FB_RESERVED
);
774 if (BITCLR(hcap
->cap
, AHCI_CAP_S64A
)) {
775 reg
= PX_RREG(port
, AHCI_PX_FBU
);
776 g_assert_cmphex(reg
, ==, 0);
780 reg
= PX_RREG(port
, AHCI_PX_IS
);
781 g_assert_cmphex(reg
, ==, 0);
784 reg
= PX_RREG(port
, AHCI_PX_IE
);
785 g_assert_cmphex(reg
, ==, 0);
788 reg
= PX_RREG(port
, AHCI_PX_CMD
);
789 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FRE
);
790 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_RESERVED
);
791 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CCS
);
792 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FR
);
793 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CR
);
794 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_PMA
); /* And RW only if CAP.SPM */
795 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_APSTE
); /* RW only if CAP2.APST */
796 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ATAPI
);
797 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_DLAE
);
798 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ALPE
); /* RW only if CAP.SALP */
799 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ASP
); /* RW only if CAP.SALP */
800 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ICC
);
801 /* If CPDetect support does not exist, CPState must be off. */
802 if (BITCLR(reg
, AHCI_PX_CMD_CPD
)) {
803 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CPS
);
805 /* If MPSPresence is not set, MPSState must be off. */
806 if (BITCLR(reg
, AHCI_PX_CMD_MPSP
)) {
807 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
809 /* If we do not support MPS, MPSS and MPSP must be off. */
810 if (BITCLR(hcap
->cap
, AHCI_CAP_SMPS
)) {
811 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
812 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSP
);
814 /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
815 if (BITANY(reg
, AHCI_PX_CMD_CPD
|| AHCI_PX_CMD_MPSP
)) {
816 ASSERT_BIT_SET(reg
, AHCI_PX_CMD_HPCP
);
818 /* HPCP and ESP cannot both be active. */
819 g_assert(!BITSET(reg
, AHCI_PX_CMD_HPCP
| AHCI_PX_CMD_ESP
));
820 /* If CAP.FBSS is not set, FBSCP must not be set. */
821 if (BITCLR(hcap
->cap
, AHCI_CAP_FBSS
)) {
822 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FBSCP
);
826 reg
= PX_RREG(port
, AHCI_PX_RES1
);
827 g_assert_cmphex(reg
, ==, 0);
830 reg
= PX_RREG(port
, AHCI_PX_TFD
);
831 /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
832 * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
833 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_ERR
);
834 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS1
);
835 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_DRQ
);
836 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS2
);
837 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_STS_BSY
);
838 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_ERR
);
839 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_RESERVED
);
842 /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
843 * Even when GHC.ST is zero, the AHCI HBA may receive the initial
844 * D2H register FIS and update the signature asynchronously,
845 * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
847 /* (10) SSTS / SCR0: SStatus */
848 reg
= PX_RREG(port
, AHCI_PX_SSTS
);
849 ASSERT_BIT_CLEAR(reg
, AHCI_PX_SSTS_RESERVED
);
850 /* Even though the register should be 0 at boot, it is asynchronous and
851 * prone to change, so we cannot test any well known value. */
853 /* (11) SCTL / SCR2: SControl */
854 reg
= PX_RREG(port
, AHCI_PX_SCTL
);
855 g_assert_cmphex(reg
, ==, 0);
857 /* (12) SERR / SCR1: SError */
858 reg
= PX_RREG(port
, AHCI_PX_SERR
);
859 g_assert_cmphex(reg
, ==, 0);
861 /* (13) SACT / SCR3: SActive */
862 reg
= PX_RREG(port
, AHCI_PX_SACT
);
863 g_assert_cmphex(reg
, ==, 0);
866 reg
= PX_RREG(port
, AHCI_PX_CI
);
867 g_assert_cmphex(reg
, ==, 0);
870 reg
= PX_RREG(port
, AHCI_PX_SNTF
);
871 g_assert_cmphex(reg
, ==, 0);
874 reg
= PX_RREG(port
, AHCI_PX_FBS
);
875 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_EN
);
876 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEC
);
877 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_SDE
);
878 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEV
);
879 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DWE
);
880 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_RESERVED
);
881 if (BITSET(hcap
->cap
, AHCI_CAP_FBSS
)) {
882 /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
883 g_assert((reg
& AHCI_PX_FBS_ADO
) >> ctzl(AHCI_PX_FBS_ADO
) >= 2);
886 /* [17 -- 27] RESERVED */
887 for (i
= AHCI_PX_RES2
; i
< AHCI_PX_VS
; ++i
) {
888 reg
= PX_RREG(port
, i
);
889 g_assert_cmphex(reg
, ==, 0);
892 /* [28 -- 31] Vendor-Specific */
893 for (i
= AHCI_PX_VS
; i
< 32; ++i
) {
894 reg
= PX_RREG(port
, i
);
896 g_test_message("INFO: Vendor register %u non-empty", i
);
902 * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
903 * device we see, then read and check the response.
905 static void ahci_test_identify(QPCIDevice
*ahci
, void *hba_base
)
907 RegD2HFIS
*d2h
= g_malloc0(0x20);
908 RegD2HFIS
*pio
= g_malloc0(0x20);
912 uint32_t ports
, reg
, clb
, table
, fb
, data_ptr
;
917 g_assert(ahci
!= NULL
);
918 g_assert(hba_base
!= NULL
);
921 * (1) Create a Command Table Buffer and update the Command List Slot #0
922 * to point to this buffer.
923 * (2) Construct an FIS host-to-device command structure, and write it to
924 * the top of the command table buffer.
925 * (3) Create a data buffer for the IDENTIFY response to be sent to
926 * (4) Create a Physical Region Descriptor that points to the data buffer,
927 * and write it to the bottom (offset 0x80) of the command table.
928 * (5) Now, PxCLB points to the command list, command 0 points to
929 * our table, and our table contains an FIS instruction and a
930 * PRD that points to our rx buffer.
931 * (6) We inform the HBA via PxCI that there is a command ready in slot #0.
934 /* Pick the first implemented and running port */
935 ports
= AHCI_RREG(AHCI_PI
);
936 for (i
= 0; i
< 32; ports
>>= 1, ++i
) {
941 if (!(ports
& 0x01)) {
945 reg
= PX_RREG(i
, AHCI_PX_CMD
);
946 if (BITSET(reg
, AHCI_PX_CMD_ST
)) {
950 g_assert_cmphex(i
, <, 32);
951 g_test_message("Selected port %u for test", i
);
953 /* Clear out this port's interrupts (ignore the init register d2h fis) */
954 reg
= PX_RREG(i
, AHCI_PX_IS
);
955 PX_WREG(i
, AHCI_PX_IS
, reg
);
956 g_assert_cmphex(PX_RREG(i
, AHCI_PX_IS
), ==, 0);
958 /* Wipe the FIS-Receive Buffer */
959 fb
= PX_RREG(i
, AHCI_PX_FB
);
960 g_assert_cmphex(fb
, !=, 0);
961 qmemset(fb
, 0x00, 0x100);
963 /* Create a Command Table buffer. 0x80 is the smallest with a PRDTL of 0. */
964 /* We need at least one PRD, so round up to the nearest 0x80 multiple. */
965 table
= guest_alloc(guest_malloc
, CMD_TBL_SIZ(1));
967 ASSERT_BIT_CLEAR(table
, 0x7F);
969 /* Create a data buffer ... where we will dump the IDENTIFY data to. */
970 data_ptr
= guest_alloc(guest_malloc
, 512);
973 /* Grab the Command List Buffer pointer */
974 clb
= PX_RREG(i
, AHCI_PX_CLB
);
977 /* Copy the existing Command #0 structure from the CLB into local memory,
978 * and build a new command #0. */
979 memread(clb
, &cmd
, sizeof(cmd
));
980 cmd
.b1
= 5; /* reg_h2d_fis is 5 double-words long */
981 cmd
.b2
= 0x04; /* clear PxTFD.STS.BSY when done */
982 cmd
.prdtl
= cpu_to_le16(1); /* One PRD table entry. */
984 cmd
.ctba
= cpu_to_le32(table
);
987 /* Construct our PRD, noting that DBC is 0-indexed. */
988 prd
.dba
= cpu_to_le32(data_ptr
);
991 /* 511+1 bytes, request DPS interrupt */
992 prd
.dbc
= cpu_to_le32(511 | 0x80000000);
994 /* Construct our Command FIS, Based on http://wiki.osdev.org/AHCI */
995 memset(&fis
, 0x00, sizeof(fis
));
996 fis
.fis_type
= 0x27; /* Register Host-to-Device FIS */
997 fis
.command
= 0xEC; /* IDENTIFY */
999 fis
.flags
= 0x80; /* Indicate this is a command FIS */
1001 /* We've committed nothing yet, no interrupts should be posted yet. */
1002 g_assert_cmphex(PX_RREG(i
, AHCI_PX_IS
), ==, 0);
1004 /* Commit the Command FIS to the Command Table */
1005 memwrite(table
, &fis
, sizeof(fis
));
1007 /* Commit the PRD entry to the Command Table */
1008 memwrite(table
+ 0x80, &prd
, sizeof(prd
));
1010 /* Commit Command #0, pointing to the Table, to the Command List Buffer. */
1011 memwrite(clb
, &cmd
, sizeof(cmd
));
1013 /* Everything is in place, but we haven't given the go-ahead yet. */
1014 g_assert_cmphex(PX_RREG(i
, AHCI_PX_IS
), ==, 0);
1016 /* Issue Command #0 via PxCI */
1017 PX_WREG(i
, AHCI_PX_CI
, (1 << 0));
1018 while (BITSET(PX_RREG(i
, AHCI_PX_TFD
), AHCI_PX_TFD_STS_BSY
)) {
1022 /* Check for expected interrupts */
1023 reg
= PX_RREG(i
, AHCI_PX_IS
);
1024 ASSERT_BIT_SET(reg
, AHCI_PX_IS_DHRS
);
1025 ASSERT_BIT_SET(reg
, AHCI_PX_IS_PSS
);
1026 /* BUG: we expect AHCI_PX_IS_DPS to be set. */
1027 ASSERT_BIT_CLEAR(reg
, AHCI_PX_IS_DPS
);
1029 /* Clear expected interrupts and assert all interrupts now cleared. */
1030 PX_WREG(i
, AHCI_PX_IS
, AHCI_PX_IS_DHRS
| AHCI_PX_IS_PSS
| AHCI_PX_IS_DPS
);
1031 g_assert_cmphex(PX_RREG(i
, AHCI_PX_IS
), ==, 0);
1033 /* Check for errors. */
1034 reg
= PX_RREG(i
, AHCI_PX_SERR
);
1035 g_assert_cmphex(reg
, ==, 0);
1036 reg
= PX_RREG(i
, AHCI_PX_TFD
);
1037 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_STS_ERR
);
1038 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_ERR
);
1040 /* Investigate CMD #0, assert that we read 512 bytes */
1041 memread(clb
, &cmd
, sizeof(cmd
));
1042 g_assert_cmphex(512, ==, le32_to_cpu(cmd
.prdbc
));
1044 /* Investigate FIS responses */
1045 memread(fb
+ 0x20, pio
, 0x20);
1046 memread(fb
+ 0x40, d2h
, 0x20);
1047 g_assert_cmphex(pio
->fis_type
, ==, 0x5f);
1048 g_assert_cmphex(d2h
->fis_type
, ==, 0x34);
1049 g_assert_cmphex(pio
->flags
, ==, d2h
->flags
);
1050 g_assert_cmphex(pio
->status
, ==, d2h
->status
);
1051 g_assert_cmphex(pio
->error
, ==, d2h
->error
);
1053 reg
= PX_RREG(i
, AHCI_PX_TFD
);
1054 g_assert_cmphex((reg
& AHCI_PX_TFD_ERR
), ==, pio
->error
);
1055 g_assert_cmphex((reg
& AHCI_PX_TFD_STS
), ==, pio
->status
);
1056 /* The PIO Setup FIS contains a "bytes read" field, which is a
1057 * 16-bit value. The Physical Region Descriptor Byte Count is
1058 * 32-bit, but for small transfers using one PRD, it should match. */
1059 g_assert_cmphex(le16_to_cpu(pio
->res4
), ==, le32_to_cpu(cmd
.prdbc
));
1061 /* Last, but not least: Investigate the IDENTIFY response data. */
1062 memread(data_ptr
, &buff
, 512);
1064 /* Check serial number/version in the buffer */
1065 /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
1066 * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
1067 * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
1068 * as a consequence, only needs to unchunk the data on LE machines. */
1069 string_bswap16(&buff
[10], 20);
1070 rc
= memcmp(&buff
[10], "testdisk ", 20);
1071 g_assert_cmphex(rc
, ==, 0);
1073 string_bswap16(&buff
[23], 8);
1074 rc
= memcmp(&buff
[23], "version ", 8);
1075 g_assert_cmphex(rc
, ==, 0);
1081 /******************************************************************************/
1082 /* Test Interfaces */
1083 /******************************************************************************/
1086 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
1088 static void test_sanity(void)
1092 ahci_shutdown(ahci
);
1096 * Ensure that the PCI configuration space for the AHCI device is in-line with
1097 * the AHCI 1.3 specification for initial values.
1099 static void test_pci_spec(void)
1103 ahci_test_pci_spec(ahci
->dev
);
1104 ahci_shutdown(ahci
);
1108 * Engage the PCI AHCI device and sanity check the response.
1109 * Perform additional PCI config space bringup for the HBA.
1111 static void test_pci_enable(void)
1116 ahci_pci_enable(ahci
->dev
, &hba_base
);
1117 ahci_shutdown(ahci
);
1121 * Investigate the memory mapped regions of the HBA,
1122 * and test them for AHCI specification adherence.
1124 static void test_hba_spec(void)
1130 ahci_pci_enable(ahci
->dev
, &hba_base
);
1131 ahci_test_hba_spec(ahci
->dev
, hba_base
);
1132 ahci_shutdown(ahci
);
1136 * Engage the HBA functionality of the AHCI PCI device,
1137 * and bring it into a functional idle state.
1139 static void test_hba_enable(void)
1145 ahci_pci_enable(ahci
->dev
, &hba_base
);
1146 ahci_hba_enable(ahci
->dev
, hba_base
);
1147 ahci_shutdown(ahci
);
1151 * Bring up the device and issue an IDENTIFY command.
1152 * Inspect the state of the HBA device and the data returned.
1154 static void test_identify(void)
1160 ahci_pci_enable(ahci
->dev
, &hba_base
);
1161 ahci_hba_enable(ahci
->dev
, hba_base
);
1162 ahci_test_identify(ahci
->dev
, hba_base
);
1163 ahci_shutdown(ahci
);
1166 /******************************************************************************/
1168 int main(int argc
, char **argv
)
1175 static struct option long_options
[] = {
1176 {"pedantic", no_argument
, 0, 'p' },
1180 /* Should be first to utilize g_test functionality, So we can see errors. */
1181 g_test_init(&argc
, &argv
, NULL
);
1184 c
= getopt_long(argc
, argv
, "", long_options
, NULL
);
1195 fprintf(stderr
, "Unrecognized ahci_test option.\n");
1196 g_assert_not_reached();
1200 /* Check architecture */
1201 arch
= qtest_get_arch();
1202 if (strcmp(arch
, "i386") && strcmp(arch
, "x86_64")) {
1203 g_test_message("Skipping test for non-x86");
1207 /* Create a temporary raw image */
1208 fd
= mkstemp(tmp_path
);
1210 ret
= ftruncate(fd
, TEST_IMAGE_SIZE
);
1215 qtest_add_func("/ahci/sanity", test_sanity
);
1216 qtest_add_func("/ahci/pci_spec", test_pci_spec
);
1217 qtest_add_func("/ahci/pci_enable", test_pci_enable
);
1218 qtest_add_func("/ahci/hba_spec", test_hba_spec
);
1219 qtest_add_func("/ahci/hba_enable", test_hba_enable
);
1220 qtest_add_func("/ahci/identify", test_identify
);