4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 #include "libqos/libqos-pc.h"
33 #include "libqos/ahci.h"
34 #include "libqos/pci-pc.h"
36 #include "qemu-common.h"
37 #include "qemu/host-utils.h"
39 #include "hw/pci/pci_ids.h"
40 #include "hw/pci/pci_regs.h"
42 /* Test-specific defines -- in MiB */
43 #define TEST_IMAGE_SIZE_MB (200 * 1024)
44 #define TEST_IMAGE_SECTORS ((TEST_IMAGE_SIZE_MB / AHCI_SECTOR_SIZE) \
48 static char tmp_path
[] = "/tmp/qtest.XXXXXX";
49 static char debug_path
[] = "/tmp/qtest-blkdebug.XXXXXX";
50 static char mig_socket
[] = "/tmp/qtest-migration.XXXXXX";
51 static bool ahci_pedantic
;
52 static const char *imgfmt
;
54 /*** Function Declarations ***/
55 static void ahci_test_port_spec(AHCIQState
*ahci
, uint8_t port
);
56 static void ahci_test_pci_spec(AHCIQState
*ahci
);
57 static void ahci_test_pci_caps(AHCIQState
*ahci
, uint16_t header
,
59 static void ahci_test_satacap(AHCIQState
*ahci
, uint8_t offset
);
60 static void ahci_test_msicap(AHCIQState
*ahci
, uint8_t offset
);
61 static void ahci_test_pmcap(AHCIQState
*ahci
, uint8_t offset
);
65 static void string_bswap16(uint16_t *s
, size_t bytes
)
67 g_assert_cmphex((bytes
& 1), ==, 0);
77 * Verify that the transfer did not corrupt our state at all.
79 static void verify_state(AHCIQState
*ahci
)
82 uint32_t ahci_fingerprint
;
85 AHCICommandHeader cmd
;
87 ahci_fingerprint
= qpci_config_readl(ahci
->dev
, PCI_VENDOR_ID
);
88 g_assert_cmphex(ahci_fingerprint
, ==, ahci
->fingerprint
);
90 /* If we haven't initialized, this is as much as can be validated. */
91 if (!ahci
->hba_base
) {
95 hba_base
= (uint64_t)qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
96 hba_stored
= (uint64_t)(uintptr_t)ahci
->hba_base
;
97 g_assert_cmphex(hba_base
, ==, hba_stored
);
99 g_assert_cmphex(ahci_rreg(ahci
, AHCI_CAP
), ==, ahci
->cap
);
100 g_assert_cmphex(ahci_rreg(ahci
, AHCI_CAP2
), ==, ahci
->cap2
);
102 for (i
= 0; i
< 32; i
++) {
103 g_assert_cmphex(ahci_px_rreg(ahci
, i
, AHCI_PX_FB
), ==,
105 g_assert_cmphex(ahci_px_rreg(ahci
, i
, AHCI_PX_CLB
), ==,
107 for (j
= 0; j
< 32; j
++) {
108 ahci_get_command_header(ahci
, i
, j
, &cmd
);
109 g_assert_cmphex(cmd
.prdtl
, ==, ahci
->port
[i
].prdtl
[j
]);
110 g_assert_cmphex(cmd
.ctba
, ==, ahci
->port
[i
].ctba
[j
]);
115 static void ahci_migrate(AHCIQState
*from
, AHCIQState
*to
, const char *uri
)
117 QOSState
*tmp
= to
->parent
;
118 QPCIDevice
*dev
= to
->dev
;
119 char *uri_local
= NULL
;
122 uri_local
= g_strdup_printf("%s%s", "unix:", mig_socket
);
126 /* context will be 'to' after completion. */
127 migrate(from
->parent
, to
->parent
, uri
);
129 /* We'd like for the AHCIState objects to still point
130 * to information specific to its specific parent
131 * instance, but otherwise just inherit the new data. */
132 memcpy(to
, from
, sizeof(AHCIQState
));
138 memset(from
, 0x00, sizeof(AHCIQState
));
146 /*** Test Setup & Teardown ***/
149 * Start a Q35 machine and bookmark a handle to the AHCI device.
151 static AHCIQState
*ahci_vboot(const char *cli
, va_list ap
)
155 s
= g_malloc0(sizeof(AHCIQState
));
156 s
->parent
= qtest_pc_vboot(cli
, ap
);
157 alloc_set_flags(s
->parent
->alloc
, ALLOC_LEAK_ASSERT
);
159 /* Verify that we have an AHCI device present. */
160 s
->dev
= get_ahci_device(&s
->fingerprint
);
166 * Start a Q35 machine and bookmark a handle to the AHCI device.
168 static AHCIQState
*ahci_boot(const char *cli
, ...)
175 s
= ahci_vboot(cli
, ap
);
178 cli
= "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
181 "-device ide-hd,drive=drive0 "
182 "-global ide-hd.ver=%s";
183 s
= ahci_boot(cli
, tmp_path
, "testdisk", imgfmt
, "version");
190 * Clean up the PCI device, then terminate the QEMU instance.
192 static void ahci_shutdown(AHCIQState
*ahci
)
194 QOSState
*qs
= ahci
->parent
;
197 ahci_clean_mem(ahci
);
198 free_ahci_device(ahci
->dev
);
204 * Boot and fully enable the HBA device.
205 * @see ahci_boot, ahci_pci_enable and ahci_hba_enable.
207 static AHCIQState
*ahci_boot_and_enable(const char *cli
, ...)
216 ahci
= ahci_vboot(cli
, ap
);
219 ahci
= ahci_boot(NULL
);
222 ahci_pci_enable(ahci
);
223 ahci_hba_enable(ahci
);
224 /* Initialize test device */
225 port
= ahci_port_select(ahci
);
226 ahci_port_clear(ahci
, port
);
227 ahci_io(ahci
, port
, CMD_IDENTIFY
, &buff
, sizeof(buff
), 0);
232 /*** Specification Adherence Tests ***/
235 * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
237 static void ahci_test_pci_spec(AHCIQState
*ahci
)
243 /* Most of these bits should start cleared until we turn them on. */
244 data
= qpci_config_readw(ahci
->dev
, PCI_COMMAND
);
245 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MEMORY
);
246 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MASTER
);
247 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SPECIAL
); /* Reserved */
248 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_VGA_PALETTE
); /* Reserved */
249 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_PARITY
);
250 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_WAIT
); /* Reserved */
251 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SERR
);
252 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_FAST_BACK
);
253 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_INTX_DISABLE
);
254 ASSERT_BIT_CLEAR(data
, 0xF800); /* Reserved */
256 data
= qpci_config_readw(ahci
->dev
, PCI_STATUS
);
257 ASSERT_BIT_CLEAR(data
, 0x01 | 0x02 | 0x04); /* Reserved */
258 ASSERT_BIT_CLEAR(data
, PCI_STATUS_INTERRUPT
);
259 ASSERT_BIT_SET(data
, PCI_STATUS_CAP_LIST
); /* must be set */
260 ASSERT_BIT_CLEAR(data
, PCI_STATUS_UDF
); /* Reserved */
261 ASSERT_BIT_CLEAR(data
, PCI_STATUS_PARITY
);
262 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_TARGET_ABORT
);
263 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_TARGET_ABORT
);
264 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_MASTER_ABORT
);
265 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_SYSTEM_ERROR
);
266 ASSERT_BIT_CLEAR(data
, PCI_STATUS_DETECTED_PARITY
);
268 /* RID occupies the low byte, CCs occupy the high three. */
269 datal
= qpci_config_readl(ahci
->dev
, PCI_CLASS_REVISION
);
271 /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
272 * Though in practice this is likely seldom true. */
273 ASSERT_BIT_CLEAR(datal
, 0xFF);
276 /* BCC *must* equal 0x01. */
277 g_assert_cmphex(PCI_BCC(datal
), ==, 0x01);
278 if (PCI_SCC(datal
) == 0x01) {
280 ASSERT_BIT_SET(0x80000000, datal
);
281 ASSERT_BIT_CLEAR(0x60000000, datal
);
282 } else if (PCI_SCC(datal
) == 0x04) {
284 g_assert_cmphex(PCI_PI(datal
), ==, 0);
285 } else if (PCI_SCC(datal
) == 0x06) {
287 g_assert_cmphex(PCI_PI(datal
), ==, 0x01);
289 g_assert_not_reached();
292 datab
= qpci_config_readb(ahci
->dev
, PCI_CACHE_LINE_SIZE
);
293 g_assert_cmphex(datab
, ==, 0);
295 datab
= qpci_config_readb(ahci
->dev
, PCI_LATENCY_TIMER
);
296 g_assert_cmphex(datab
, ==, 0);
298 /* Only the bottom 7 bits must be off. */
299 datab
= qpci_config_readb(ahci
->dev
, PCI_HEADER_TYPE
);
300 ASSERT_BIT_CLEAR(datab
, 0x7F);
302 /* BIST is optional, but the low 7 bits must always start off regardless. */
303 datab
= qpci_config_readb(ahci
->dev
, PCI_BIST
);
304 ASSERT_BIT_CLEAR(datab
, 0x7F);
306 /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
307 datal
= qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
308 g_assert_cmphex(datal
, ==, 0);
310 qpci_config_writel(ahci
->dev
, PCI_BASE_ADDRESS_5
, 0xFFFFFFFF);
311 datal
= qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
312 /* ABAR must be 32-bit, memory mapped, non-prefetchable and
313 * must be >= 512 bytes. To that end, bits 0-8 must be off. */
314 ASSERT_BIT_CLEAR(datal
, 0xFF);
316 /* Capability list MUST be present, */
317 datal
= qpci_config_readl(ahci
->dev
, PCI_CAPABILITY_LIST
);
318 /* But these bits are reserved. */
319 ASSERT_BIT_CLEAR(datal
, ~0xFF);
320 g_assert_cmphex(datal
, !=, 0);
322 /* Check specification adherence for capability extenstions. */
323 data
= qpci_config_readw(ahci
->dev
, datal
);
325 switch (ahci
->fingerprint
) {
326 case AHCI_INTEL_ICH9
:
327 /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
328 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_MSI
);
331 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
332 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_PM
);
335 ahci_test_pci_caps(ahci
, data
, (uint8_t)datal
);
338 datal
= qpci_config_readl(ahci
->dev
, PCI_CAPABILITY_LIST
+ 4);
339 g_assert_cmphex(datal
, ==, 0);
341 /* IPIN might vary, but ILINE must be off. */
342 datab
= qpci_config_readb(ahci
->dev
, PCI_INTERRUPT_LINE
);
343 g_assert_cmphex(datab
, ==, 0);
347 * Test PCI capabilities for AHCI specification adherence.
349 static void ahci_test_pci_caps(AHCIQState
*ahci
, uint16_t header
,
352 uint8_t cid
= header
& 0xFF;
353 uint8_t next
= header
>> 8;
355 g_test_message("CID: %02x; next: %02x", cid
, next
);
359 ahci_test_pmcap(ahci
, offset
);
362 ahci_test_msicap(ahci
, offset
);
364 case PCI_CAP_ID_SATA
:
365 ahci_test_satacap(ahci
, offset
);
369 g_test_message("Unknown CAP 0x%02x", cid
);
373 ahci_test_pci_caps(ahci
, qpci_config_readw(ahci
->dev
, next
), next
);
378 * Test SATA PCI capabilitity for AHCI specification adherence.
380 static void ahci_test_satacap(AHCIQState
*ahci
, uint8_t offset
)
385 g_test_message("Verifying SATACAP");
387 /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
388 dataw
= qpci_config_readw(ahci
->dev
, offset
+ 2);
389 g_assert_cmphex(dataw
, ==, 0x10);
391 /* Grab the SATACR1 register. */
392 datal
= qpci_config_readw(ahci
->dev
, offset
+ 4);
394 switch (datal
& 0x0F) {
395 case 0x04: /* BAR0 */
396 case 0x05: /* BAR1 */
400 case 0x09: /* BAR5 */
401 case 0x0F: /* Immediately following SATACR1 in PCI config space. */
404 /* Invalid BARLOC for the Index Data Pair. */
405 g_assert_not_reached();
409 g_assert_cmphex((datal
>> 24), ==, 0x00);
413 * Test MSI PCI capability for AHCI specification adherence.
415 static void ahci_test_msicap(AHCIQState
*ahci
, uint8_t offset
)
420 g_test_message("Verifying MSICAP");
422 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_FLAGS
);
423 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_ENABLE
);
424 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_QSIZE
);
425 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_RESERVED
);
427 datal
= qpci_config_readl(ahci
->dev
, offset
+ PCI_MSI_ADDRESS_LO
);
428 g_assert_cmphex(datal
, ==, 0);
430 if (dataw
& PCI_MSI_FLAGS_64BIT
) {
431 g_test_message("MSICAP is 64bit");
432 datal
= qpci_config_readl(ahci
->dev
, offset
+ PCI_MSI_ADDRESS_HI
);
433 g_assert_cmphex(datal
, ==, 0);
434 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_DATA_64
);
435 g_assert_cmphex(dataw
, ==, 0);
437 g_test_message("MSICAP is 32bit");
438 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_DATA_32
);
439 g_assert_cmphex(dataw
, ==, 0);
444 * Test Power Management PCI capability for AHCI specification adherence.
446 static void ahci_test_pmcap(AHCIQState
*ahci
, uint8_t offset
)
450 g_test_message("Verifying PMCAP");
452 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_PM_PMC
);
453 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_PME_CLOCK
);
454 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_RESERVED
);
455 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D1
);
456 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D2
);
458 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_PM_CTRL
);
459 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_STATE_MASK
);
460 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_RESERVED
);
461 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SEL_MASK
);
462 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SCALE_MASK
);
465 static void ahci_test_hba_spec(AHCIQState
*ahci
)
473 g_assert(ahci
!= NULL
);
476 * Note that the AHCI spec does expect the BIOS to set up a few things:
477 * CAP.SSS - Support for staggered spin-up (t/f)
478 * CAP.SMPS - Support for mechanical presence switches (t/f)
479 * PI - Ports Implemented (1-32)
480 * PxCMD.HPCP - Hot Plug Capable Port
481 * PxCMD.MPSP - Mechanical Presence Switch Present
482 * PxCMD.CPD - Cold Presence Detection support
484 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
485 * Foreach Port Implemented:
486 * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
487 * -PxCLB/U and PxFB/U are set to valid regions in memory
488 * -PxSUD is set to 1.
489 * -PxSSTS.DET is polled for presence; if detected, we continue:
490 * -PxSERR is cleared with 1's.
491 * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
492 * the device is ready.
495 /* 1 CAP - Capabilities Register */
496 ahci
->cap
= ahci_rreg(ahci
, AHCI_CAP
);
497 ASSERT_BIT_CLEAR(ahci
->cap
, AHCI_CAP_RESERVED
);
499 /* 2 GHC - Global Host Control */
500 reg
= ahci_rreg(ahci
, AHCI_GHC
);
501 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_HR
);
502 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_IE
);
503 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_MRSM
);
504 if (BITSET(ahci
->cap
, AHCI_CAP_SAM
)) {
505 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
506 ASSERT_BIT_SET(reg
, AHCI_GHC_AE
);
508 g_test_message("Supports AHCI/Legacy mix.");
509 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_AE
);
512 /* 3 IS - Interrupt Status */
513 reg
= ahci_rreg(ahci
, AHCI_IS
);
514 g_assert_cmphex(reg
, ==, 0);
516 /* 4 PI - Ports Implemented */
517 ports
= ahci_rreg(ahci
, AHCI_PI
);
518 /* Ports Implemented must be non-zero. */
519 g_assert_cmphex(ports
, !=, 0);
520 /* Ports Implemented must be <= Number of Ports. */
521 nports_impl
= ctpopl(ports
);
522 g_assert_cmpuint(((AHCI_CAP_NP
& ahci
->cap
) + 1), >=, nports_impl
);
524 /* Ports must be within the proper range. Given a mapping of SIZE,
525 * 256 bytes are used for global HBA control, and the rest is used
526 * for ports data, at 0x80 bytes each. */
527 g_assert_cmphex(ahci
->barsize
, >, 0);
528 maxports
= (ahci
->barsize
- HBA_DATA_REGION_SIZE
) / HBA_PORT_DATA_SIZE
;
529 /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
530 g_assert_cmphex((reg
>> maxports
), ==, 0);
533 reg
= ahci_rreg(ahci
, AHCI_VS
);
535 case AHCI_VERSION_0_95
:
536 case AHCI_VERSION_1_0
:
537 case AHCI_VERSION_1_1
:
538 case AHCI_VERSION_1_2
:
539 case AHCI_VERSION_1_3
:
542 g_assert_not_reached();
545 /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
546 reg
= ahci_rreg(ahci
, AHCI_CCCCTL
);
547 if (BITSET(ahci
->cap
, AHCI_CAP_CCCS
)) {
548 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_EN
);
549 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_RESERVED
);
550 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_CC
);
551 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_TV
);
553 g_assert_cmphex(reg
, ==, 0);
557 reg
= ahci_rreg(ahci
, AHCI_CCCPORTS
);
558 /* Must be zeroes initially regardless of CAP.CCCS */
559 g_assert_cmphex(reg
, ==, 0);
562 reg
= ahci_rreg(ahci
, AHCI_EMLOC
);
563 if (BITCLR(ahci
->cap
, AHCI_CAP_EMS
)) {
564 g_assert_cmphex(reg
, ==, 0);
568 reg
= ahci_rreg(ahci
, AHCI_EMCTL
);
569 if (BITSET(ahci
->cap
, AHCI_CAP_EMS
)) {
570 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_STSMR
);
571 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLTM
);
572 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLRST
);
573 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_RESERVED
);
575 g_assert_cmphex(reg
, ==, 0);
578 /* 10 CAP2 -- Capabilities Extended */
579 ahci
->cap2
= ahci_rreg(ahci
, AHCI_CAP2
);
580 ASSERT_BIT_CLEAR(ahci
->cap2
, AHCI_CAP2_RESERVED
);
582 /* 11 BOHC -- Bios/OS Handoff Control */
583 reg
= ahci_rreg(ahci
, AHCI_BOHC
);
584 g_assert_cmphex(reg
, ==, 0);
586 /* 12 -- 23: Reserved */
587 g_test_message("Verifying HBA reserved area is empty.");
588 for (i
= AHCI_RESERVED
; i
< AHCI_NVMHCI
; ++i
) {
589 reg
= ahci_rreg(ahci
, i
);
590 g_assert_cmphex(reg
, ==, 0);
593 /* 24 -- 39: NVMHCI */
594 if (BITCLR(ahci
->cap2
, AHCI_CAP2_NVMP
)) {
595 g_test_message("Verifying HBA/NVMHCI area is empty.");
596 for (i
= AHCI_NVMHCI
; i
< AHCI_VENDOR
; ++i
) {
597 reg
= ahci_rreg(ahci
, i
);
598 g_assert_cmphex(reg
, ==, 0);
602 /* 40 -- 63: Vendor */
603 g_test_message("Verifying HBA/Vendor area is empty.");
604 for (i
= AHCI_VENDOR
; i
< AHCI_PORTS
; ++i
) {
605 reg
= ahci_rreg(ahci
, i
);
606 g_assert_cmphex(reg
, ==, 0);
609 /* 64 -- XX: Port Space */
610 for (i
= 0; ports
|| (i
< maxports
); ports
>>= 1, ++i
) {
611 if (BITSET(ports
, 0x1)) {
612 g_test_message("Testing port %u for spec", i
);
613 ahci_test_port_spec(ahci
, i
);
616 uint16_t low
= AHCI_PORTS
+ (32 * i
);
617 uint16_t high
= AHCI_PORTS
+ (32 * (i
+ 1));
618 g_test_message("Asserting unimplemented port %u "
619 "(reg [%u-%u]) is empty.",
621 for (j
= low
; j
< high
; ++j
) {
622 reg
= ahci_rreg(ahci
, j
);
623 g_assert_cmphex(reg
, ==, 0);
630 * Test the memory space for one port for specification adherence.
632 static void ahci_test_port_spec(AHCIQState
*ahci
, uint8_t port
)
638 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CLB
);
639 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CLB_RESERVED
);
642 if (BITCLR(ahci
->cap
, AHCI_CAP_S64A
)) {
643 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CLBU
);
644 g_assert_cmphex(reg
, ==, 0);
648 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FB
);
649 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FB_RESERVED
);
652 if (BITCLR(ahci
->cap
, AHCI_CAP_S64A
)) {
653 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FBU
);
654 g_assert_cmphex(reg
, ==, 0);
658 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_IS
);
659 g_assert_cmphex(reg
, ==, 0);
662 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_IE
);
663 g_assert_cmphex(reg
, ==, 0);
666 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CMD
);
667 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FRE
);
668 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_RESERVED
);
669 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CCS
);
670 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FR
);
671 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CR
);
672 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_PMA
); /* And RW only if CAP.SPM */
673 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_APSTE
); /* RW only if CAP2.APST */
674 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ATAPI
);
675 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_DLAE
);
676 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ALPE
); /* RW only if CAP.SALP */
677 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ASP
); /* RW only if CAP.SALP */
678 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ICC
);
679 /* If CPDetect support does not exist, CPState must be off. */
680 if (BITCLR(reg
, AHCI_PX_CMD_CPD
)) {
681 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CPS
);
683 /* If MPSPresence is not set, MPSState must be off. */
684 if (BITCLR(reg
, AHCI_PX_CMD_MPSP
)) {
685 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
687 /* If we do not support MPS, MPSS and MPSP must be off. */
688 if (BITCLR(ahci
->cap
, AHCI_CAP_SMPS
)) {
689 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
690 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSP
);
692 /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
693 if (BITANY(reg
, AHCI_PX_CMD_CPD
| AHCI_PX_CMD_MPSP
)) {
694 ASSERT_BIT_SET(reg
, AHCI_PX_CMD_HPCP
);
696 /* HPCP and ESP cannot both be active. */
697 g_assert(!BITSET(reg
, AHCI_PX_CMD_HPCP
| AHCI_PX_CMD_ESP
));
698 /* If CAP.FBSS is not set, FBSCP must not be set. */
699 if (BITCLR(ahci
->cap
, AHCI_CAP_FBSS
)) {
700 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FBSCP
);
704 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_RES1
);
705 g_assert_cmphex(reg
, ==, 0);
708 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_TFD
);
709 /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
710 * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
711 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_ERR
);
712 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS1
);
713 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_DRQ
);
714 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS2
);
715 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_STS_BSY
);
716 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_ERR
);
717 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_RESERVED
);
720 /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
721 * Even when GHC.ST is zero, the AHCI HBA may receive the initial
722 * D2H register FIS and update the signature asynchronously,
723 * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
725 /* (10) SSTS / SCR0: SStatus */
726 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SSTS
);
727 ASSERT_BIT_CLEAR(reg
, AHCI_PX_SSTS_RESERVED
);
728 /* Even though the register should be 0 at boot, it is asynchronous and
729 * prone to change, so we cannot test any well known value. */
731 /* (11) SCTL / SCR2: SControl */
732 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SCTL
);
733 g_assert_cmphex(reg
, ==, 0);
735 /* (12) SERR / SCR1: SError */
736 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SERR
);
737 g_assert_cmphex(reg
, ==, 0);
739 /* (13) SACT / SCR3: SActive */
740 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SACT
);
741 g_assert_cmphex(reg
, ==, 0);
744 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CI
);
745 g_assert_cmphex(reg
, ==, 0);
748 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SNTF
);
749 g_assert_cmphex(reg
, ==, 0);
752 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FBS
);
753 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_EN
);
754 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEC
);
755 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_SDE
);
756 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEV
);
757 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DWE
);
758 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_RESERVED
);
759 if (BITSET(ahci
->cap
, AHCI_CAP_FBSS
)) {
760 /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
761 g_assert((reg
& AHCI_PX_FBS_ADO
) >> ctzl(AHCI_PX_FBS_ADO
) >= 2);
764 /* [17 -- 27] RESERVED */
765 for (i
= AHCI_PX_RES2
; i
< AHCI_PX_VS
; ++i
) {
766 reg
= ahci_px_rreg(ahci
, port
, i
);
767 g_assert_cmphex(reg
, ==, 0);
770 /* [28 -- 31] Vendor-Specific */
771 for (i
= AHCI_PX_VS
; i
< 32; ++i
) {
772 reg
= ahci_px_rreg(ahci
, port
, i
);
774 g_test_message("INFO: Vendor register %u non-empty", i
);
780 * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
781 * device we see, then read and check the response.
783 static void ahci_test_identify(AHCIQState
*ahci
)
789 const size_t buffsize
= 512;
791 g_assert(ahci
!= NULL
);
794 * This serves as a bit of a tutorial on AHCI device programming:
796 * (1) Create a data buffer for the IDENTIFY response to be sent to
797 * (2) Create a Command Table buffer, where we will store the
798 * command and PRDT (Physical Region Descriptor Table)
799 * (3) Construct an FIS host-to-device command structure, and write it to
800 * the top of the Command Table buffer.
801 * (4) Create one or more Physical Region Descriptors (PRDs) that describe
802 * a location in memory where data may be stored/retrieved.
803 * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table.
804 * (6) Each AHCI port has up to 32 command slots. Each slot contains a
805 * header that points to a Command Table buffer. Pick an unused slot
806 * and update it to point to the Command Table we have built.
807 * (7) Now: Command #n points to our Command Table, and our Command Table
808 * contains the FIS (that describes our command) and the PRDTL, which
809 * describes our buffer.
810 * (8) We inform the HBA via PxCI (Command Issue) that the command in slot
811 * #n is ready for processing.
814 /* Pick the first implemented and running port */
815 px
= ahci_port_select(ahci
);
816 g_test_message("Selected port %u for test", px
);
818 /* Clear out the FIS Receive area and any pending interrupts. */
819 ahci_port_clear(ahci
, px
);
821 /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */
822 ahci_io(ahci
, px
, CMD_IDENTIFY
, &buff
, buffsize
, 0);
824 /* Check serial number/version in the buffer */
825 /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
826 * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
827 * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
828 * as a consequence, only needs to unchunk the data on LE machines. */
829 string_bswap16(&buff
[10], 20);
830 rc
= memcmp(&buff
[10], "testdisk ", 20);
831 g_assert_cmphex(rc
, ==, 0);
833 string_bswap16(&buff
[23], 8);
834 rc
= memcmp(&buff
[23], "version ", 8);
835 g_assert_cmphex(rc
, ==, 0);
837 sect_size
= le16_to_cpu(*((uint16_t *)(&buff
[5])));
838 g_assert_cmphex(sect_size
, ==, AHCI_SECTOR_SIZE
);
841 static void ahci_test_io_rw_simple(AHCIQState
*ahci
, unsigned bufsize
,
842 uint64_t sector
, uint8_t read_cmd
,
847 unsigned char *tx
= g_malloc(bufsize
);
848 unsigned char *rx
= g_malloc0(bufsize
);
850 g_assert(ahci
!= NULL
);
852 /* Pick the first running port and clear it. */
853 port
= ahci_port_select(ahci
);
854 ahci_port_clear(ahci
, port
);
856 /*** Create pattern and transfer to guest ***/
857 /* Data buffer in the guest */
858 ptr
= ahci_alloc(ahci
, bufsize
);
861 /* Write some indicative pattern to our buffer. */
862 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
863 bufwrite(ptr
, tx
, bufsize
);
865 /* Write this buffer to disk, then read it back to the DMA buffer. */
866 ahci_guest_io(ahci
, port
, write_cmd
, ptr
, bufsize
, sector
);
867 qmemset(ptr
, 0x00, bufsize
);
868 ahci_guest_io(ahci
, port
, read_cmd
, ptr
, bufsize
, sector
);
870 /*** Read back the Data ***/
871 bufread(ptr
, rx
, bufsize
);
872 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
874 ahci_free(ahci
, ptr
);
879 static uint8_t ahci_test_nondata(AHCIQState
*ahci
, uint8_t ide_cmd
)
885 port
= ahci_port_select(ahci
);
886 ahci_port_clear(ahci
, port
);
889 cmd
= ahci_command_create(ide_cmd
);
890 ahci_command_commit(ahci
, cmd
, port
);
891 ahci_command_issue(ahci
, cmd
);
892 ahci_command_verify(ahci
, cmd
);
893 ahci_command_free(cmd
);
898 static void ahci_test_flush(AHCIQState
*ahci
)
900 ahci_test_nondata(ahci
, CMD_FLUSH_CACHE
);
903 static void ahci_test_max(AHCIQState
*ahci
)
905 RegD2HFIS
*d2h
= g_malloc0(0x20);
909 uint64_t config_sect
= TEST_IMAGE_SECTORS
- 1;
911 if (config_sect
> 0xFFFFFF) {
912 cmd
= CMD_READ_MAX_EXT
;
917 port
= ahci_test_nondata(ahci
, cmd
);
918 memread(ahci
->port
[port
].fb
+ 0x40, d2h
, 0x20);
919 nsect
= (uint64_t)d2h
->lba_hi
[2] << 40 |
920 (uint64_t)d2h
->lba_hi
[1] << 32 |
921 (uint64_t)d2h
->lba_hi
[0] << 24 |
922 (uint64_t)d2h
->lba_lo
[2] << 16 |
923 (uint64_t)d2h
->lba_lo
[1] << 8 |
924 (uint64_t)d2h
->lba_lo
[0];
926 g_assert_cmphex(nsect
, ==, config_sect
);
931 /******************************************************************************/
932 /* Test Interfaces */
933 /******************************************************************************/
936 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
938 static void test_sanity(void)
941 ahci
= ahci_boot(NULL
);
946 * Ensure that the PCI configuration space for the AHCI device is in-line with
947 * the AHCI 1.3 specification for initial values.
949 static void test_pci_spec(void)
952 ahci
= ahci_boot(NULL
);
953 ahci_test_pci_spec(ahci
);
958 * Engage the PCI AHCI device and sanity check the response.
959 * Perform additional PCI config space bringup for the HBA.
961 static void test_pci_enable(void)
964 ahci
= ahci_boot(NULL
);
965 ahci_pci_enable(ahci
);
970 * Investigate the memory mapped regions of the HBA,
971 * and test them for AHCI specification adherence.
973 static void test_hba_spec(void)
977 ahci
= ahci_boot(NULL
);
978 ahci_pci_enable(ahci
);
979 ahci_test_hba_spec(ahci
);
984 * Engage the HBA functionality of the AHCI PCI device,
985 * and bring it into a functional idle state.
987 static void test_hba_enable(void)
991 ahci
= ahci_boot(NULL
);
992 ahci_pci_enable(ahci
);
993 ahci_hba_enable(ahci
);
998 * Bring up the device and issue an IDENTIFY command.
999 * Inspect the state of the HBA device and the data returned.
1001 static void test_identify(void)
1005 ahci
= ahci_boot_and_enable(NULL
);
1006 ahci_test_identify(ahci
);
1007 ahci_shutdown(ahci
);
1011 * Fragmented DMA test: Perform a standard 4K DMA read/write
1012 * test, but make sure the physical regions are fragmented to
1013 * be very small, each just 32 bytes, to see how AHCI performs
1014 * with chunks defined to be much less than a sector.
1016 static void test_dma_fragmented(void)
1021 size_t bufsize
= 4096;
1022 unsigned char *tx
= g_malloc(bufsize
);
1023 unsigned char *rx
= g_malloc0(bufsize
);
1026 ahci
= ahci_boot_and_enable(NULL
);
1027 px
= ahci_port_select(ahci
);
1028 ahci_port_clear(ahci
, px
);
1030 /* create pattern */
1031 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1033 /* Create a DMA buffer in guest memory, and write our pattern to it. */
1034 ptr
= guest_alloc(ahci
->parent
->alloc
, bufsize
);
1036 bufwrite(ptr
, tx
, bufsize
);
1038 cmd
= ahci_command_create(CMD_WRITE_DMA
);
1039 ahci_command_adjust(cmd
, 0, ptr
, bufsize
, 32);
1040 ahci_command_commit(ahci
, cmd
, px
);
1041 ahci_command_issue(ahci
, cmd
);
1042 ahci_command_verify(ahci
, cmd
);
1045 cmd
= ahci_command_create(CMD_READ_DMA
);
1046 ahci_command_adjust(cmd
, 0, ptr
, bufsize
, 32);
1047 ahci_command_commit(ahci
, cmd
, px
);
1048 ahci_command_issue(ahci
, cmd
);
1049 ahci_command_verify(ahci
, cmd
);
1052 /* Read back the guest's receive buffer into local memory */
1053 bufread(ptr
, rx
, bufsize
);
1054 guest_free(ahci
->parent
->alloc
, ptr
);
1056 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1058 ahci_shutdown(ahci
);
1064 static void test_flush(void)
1068 ahci
= ahci_boot_and_enable(NULL
);
1069 ahci_test_flush(ahci
);
1070 ahci_shutdown(ahci
);
1073 static void test_flush_retry(void)
1080 prepare_blkdebug_script(debug_path
, "flush_to_disk");
1081 ahci
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1082 "format=%s,cache=writeback,"
1083 "rerror=stop,werror=stop "
1085 "-device ide-hd,drive=drive0 ",
1089 /* Issue Flush Command and wait for error */
1090 port
= ahci_port_select(ahci
);
1091 ahci_port_clear(ahci
, port
);
1092 cmd
= ahci_command_create(CMD_FLUSH_CACHE
);
1093 ahci_command_commit(ahci
, cmd
, port
);
1094 ahci_command_issue_async(ahci
, cmd
);
1095 qmp_eventwait("STOP");
1097 /* Complete the command */
1098 s
= "{'execute':'cont' }";
1100 qmp_eventwait("RESUME");
1101 ahci_command_wait(ahci
, cmd
);
1102 ahci_command_verify(ahci
, cmd
);
1104 ahci_command_free(cmd
);
1105 ahci_shutdown(ahci
);
1109 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
1111 static void test_migrate_sanity(void)
1113 AHCIQState
*src
, *dst
;
1114 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1116 src
= ahci_boot("-m 1024 -M q35 "
1117 "-drive if=ide,file=%s,format=%s ", tmp_path
, imgfmt
);
1118 dst
= ahci_boot("-m 1024 -M q35 "
1119 "-drive if=ide,file=%s,format=%s "
1120 "-incoming %s", tmp_path
, imgfmt
, uri
);
1122 ahci_migrate(src
, dst
, uri
);
1130 * Simple migration test: Write a pattern, migrate, then read.
1132 static void ahci_migrate_simple(uint8_t cmd_read
, uint8_t cmd_write
)
1134 AHCIQState
*src
, *dst
;
1136 size_t bufsize
= 4096;
1137 unsigned char *tx
= g_malloc(bufsize
);
1138 unsigned char *rx
= g_malloc0(bufsize
);
1139 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1141 src
= ahci_boot_and_enable("-m 1024 -M q35 "
1142 "-drive if=ide,format=%s,file=%s ",
1144 dst
= ahci_boot("-m 1024 -M q35 "
1145 "-drive if=ide,format=%s,file=%s "
1146 "-incoming %s", imgfmt
, tmp_path
, uri
);
1148 set_context(src
->parent
);
1151 px
= ahci_port_select(src
);
1152 ahci_port_clear(src
, px
);
1154 /* create pattern */
1155 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1157 /* Write, migrate, then read. */
1158 ahci_io(src
, px
, cmd_write
, tx
, bufsize
, 0);
1159 ahci_migrate(src
, dst
, uri
);
1160 ahci_io(dst
, px
, cmd_read
, rx
, bufsize
, 0);
1162 /* Verify pattern */
1163 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1172 static void test_migrate_dma(void)
1174 ahci_migrate_simple(CMD_READ_DMA
, CMD_WRITE_DMA
);
1177 static void test_migrate_ncq(void)
1179 ahci_migrate_simple(READ_FPDMA_QUEUED
, WRITE_FPDMA_QUEUED
);
1183 * Halted IO Error Test
1185 * Simulate an error on first write, Try to write a pattern,
1186 * Confirm the VM has stopped, resume the VM, verify command
1187 * has completed, then read back the data and verify.
1189 static void ahci_halted_io_test(uint8_t cmd_read
, uint8_t cmd_write
)
1193 size_t bufsize
= 4096;
1194 unsigned char *tx
= g_malloc(bufsize
);
1195 unsigned char *rx
= g_malloc0(bufsize
);
1199 prepare_blkdebug_script(debug_path
, "write_aio");
1201 ahci
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1202 "format=%s,cache=writeback,"
1203 "rerror=stop,werror=stop "
1205 "-device ide-hd,drive=drive0 ",
1209 /* Initialize and prepare */
1210 port
= ahci_port_select(ahci
);
1211 ahci_port_clear(ahci
, port
);
1213 /* create DMA source buffer and write pattern */
1214 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1215 ptr
= ahci_alloc(ahci
, bufsize
);
1217 memwrite(ptr
, tx
, bufsize
);
1219 /* Attempt to write (and fail) */
1220 cmd
= ahci_guest_io_halt(ahci
, port
, cmd_write
,
1223 /* Attempt to resume the command */
1224 ahci_guest_io_resume(ahci
, cmd
);
1225 ahci_free(ahci
, ptr
);
1227 /* Read back and verify */
1228 ahci_io(ahci
, port
, cmd_read
, rx
, bufsize
, 0);
1229 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1231 /* Cleanup and go home */
1232 ahci_shutdown(ahci
);
1237 static void test_halted_dma(void)
1239 ahci_halted_io_test(CMD_READ_DMA
, CMD_WRITE_DMA
);
1242 static void test_halted_ncq(void)
1244 ahci_halted_io_test(READ_FPDMA_QUEUED
, WRITE_FPDMA_QUEUED
);
1248 * IO Error Migration Test
1250 * Simulate an error on first write, Try to write a pattern,
1251 * Confirm the VM has stopped, migrate, resume the VM,
1252 * verify command has completed, then read back the data and verify.
1254 static void ahci_migrate_halted_io(uint8_t cmd_read
, uint8_t cmd_write
)
1256 AHCIQState
*src
, *dst
;
1258 size_t bufsize
= 4096;
1259 unsigned char *tx
= g_malloc(bufsize
);
1260 unsigned char *rx
= g_malloc0(bufsize
);
1263 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1265 prepare_blkdebug_script(debug_path
, "write_aio");
1267 src
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1268 "format=%s,cache=writeback,"
1269 "rerror=stop,werror=stop "
1271 "-device ide-hd,drive=drive0 ",
1275 dst
= ahci_boot("-drive file=%s,if=none,id=drive0,"
1276 "format=%s,cache=writeback,"
1277 "rerror=stop,werror=stop "
1279 "-device ide-hd,drive=drive0 "
1281 tmp_path
, imgfmt
, uri
);
1283 set_context(src
->parent
);
1285 /* Initialize and prepare */
1286 port
= ahci_port_select(src
);
1287 ahci_port_clear(src
, port
);
1288 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1290 /* create DMA source buffer and write pattern */
1291 ptr
= ahci_alloc(src
, bufsize
);
1293 memwrite(ptr
, tx
, bufsize
);
1295 /* Write, trigger the VM to stop, migrate, then resume. */
1296 cmd
= ahci_guest_io_halt(src
, port
, cmd_write
,
1298 ahci_migrate(src
, dst
, uri
);
1299 ahci_guest_io_resume(dst
, cmd
);
1300 ahci_free(dst
, ptr
);
1303 ahci_io(dst
, port
, cmd_read
, rx
, bufsize
, 0);
1305 /* Verify TX and RX are identical */
1306 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1308 /* Cleanup and go home. */
1316 static void test_migrate_halted_dma(void)
1318 ahci_migrate_halted_io(CMD_READ_DMA
, CMD_WRITE_DMA
);
1321 static void test_migrate_halted_ncq(void)
1323 ahci_migrate_halted_io(READ_FPDMA_QUEUED
, WRITE_FPDMA_QUEUED
);
1327 * Migration test: Try to flush, migrate, then resume.
1329 static void test_flush_migrate(void)
1331 AHCIQState
*src
, *dst
;
1335 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1337 prepare_blkdebug_script(debug_path
, "flush_to_disk");
1339 src
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1340 "cache=writeback,rerror=stop,werror=stop,"
1343 "-device ide-hd,drive=drive0 ",
1344 debug_path
, tmp_path
, imgfmt
);
1345 dst
= ahci_boot("-drive file=%s,if=none,id=drive0,"
1346 "cache=writeback,rerror=stop,werror=stop,"
1349 "-device ide-hd,drive=drive0 "
1350 "-incoming %s", tmp_path
, imgfmt
, uri
);
1352 set_context(src
->parent
);
1354 /* Issue Flush Command */
1355 px
= ahci_port_select(src
);
1356 ahci_port_clear(src
, px
);
1357 cmd
= ahci_command_create(CMD_FLUSH_CACHE
);
1358 ahci_command_commit(src
, cmd
, px
);
1359 ahci_command_issue_async(src
, cmd
);
1360 qmp_eventwait("STOP");
1363 ahci_migrate(src
, dst
, uri
);
1365 /* Complete the command */
1366 s
= "{'execute':'cont' }";
1368 qmp_eventwait("RESUME");
1369 ahci_command_wait(dst
, cmd
);
1370 ahci_command_verify(dst
, cmd
);
1372 ahci_command_free(cmd
);
1378 static void test_max(void)
1382 ahci
= ahci_boot_and_enable(NULL
);
1383 ahci_test_max(ahci
);
1384 ahci_shutdown(ahci
);
1387 static void test_reset(void)
1392 ahci
= ahci_boot(NULL
);
1393 ahci_test_pci_spec(ahci
);
1394 ahci_pci_enable(ahci
);
1396 for (i
= 0; i
< 2; i
++) {
1397 ahci_test_hba_spec(ahci
);
1398 ahci_hba_enable(ahci
);
1399 ahci_test_identify(ahci
);
1400 ahci_test_io_rw_simple(ahci
, 4096, 0,
1403 ahci_set(ahci
, AHCI_GHC
, AHCI_GHC_HR
);
1404 ahci_clean_mem(ahci
);
1407 ahci_shutdown(ahci
);
1410 static void test_ncq_simple(void)
1414 ahci
= ahci_boot_and_enable(NULL
);
1415 ahci_test_io_rw_simple(ahci
, 4096, 0,
1417 WRITE_FPDMA_QUEUED
);
1418 ahci_shutdown(ahci
);
1421 /******************************************************************************/
1422 /* AHCI I/O Test Matrix Definitions */
1426 LEN_SIMPLE
= LEN_BEGIN
,
1433 static const char *buff_len_str
[NUM_LENGTHS
] = { "simple", "double",
1437 ADDR_MODE_BEGIN
= 0,
1438 ADDR_MODE_LBA28
= ADDR_MODE_BEGIN
,
1443 static const char *addr_mode_str
[NUM_ADDR_MODES
] = { "lba28", "lba48" };
1447 MODE_PIO
= MODE_BEGIN
,
1452 static const char *io_mode_str
[NUM_MODES
] = { "pio", "dma" };
1463 OFFSET_ZERO
= OFFSET_BEGIN
,
1469 static const char *offset_str
[NUM_OFFSETS
] = { "zero", "low", "high" };
1471 typedef struct AHCIIOTestOptions
{
1472 enum BuffLen length
;
1473 enum AddrMode address_type
;
1474 enum IOMode io_type
;
1475 enum OffsetType offset
;
1476 } AHCIIOTestOptions
;
1478 static uint64_t offset_sector(enum OffsetType ofst
,
1479 enum AddrMode addr_type
,
1491 ceil
= (addr_type
== ADDR_MODE_LBA28
) ? 0xfffffff : 0xffffffffffff;
1492 ceil
= MIN(ceil
, TEST_IMAGE_SECTORS
- 1);
1493 nsectors
= buffsize
/ AHCI_SECTOR_SIZE
;
1494 return ceil
- nsectors
+ 1;
1496 g_assert_not_reached();
1501 * Table of possible I/O ATA commands given a set of enumerations.
1503 static const uint8_t io_cmds
[NUM_MODES
][NUM_ADDR_MODES
][NUM_IO_OPS
] = {
1505 [ADDR_MODE_LBA28
] = {
1506 [IO_READ
] = CMD_READ_PIO
,
1507 [IO_WRITE
] = CMD_WRITE_PIO
},
1508 [ADDR_MODE_LBA48
] = {
1509 [IO_READ
] = CMD_READ_PIO_EXT
,
1510 [IO_WRITE
] = CMD_WRITE_PIO_EXT
}
1513 [ADDR_MODE_LBA28
] = {
1514 [IO_READ
] = CMD_READ_DMA
,
1515 [IO_WRITE
] = CMD_WRITE_DMA
},
1516 [ADDR_MODE_LBA48
] = {
1517 [IO_READ
] = CMD_READ_DMA_EXT
,
1518 [IO_WRITE
] = CMD_WRITE_DMA_EXT
}
1523 * Test a Read/Write pattern using various commands, addressing modes,
1524 * transfer modes, and buffer sizes.
1526 static void test_io_rw_interface(enum AddrMode lba48
, enum IOMode dma
,
1527 unsigned bufsize
, uint64_t sector
)
1531 ahci
= ahci_boot_and_enable(NULL
);
1532 ahci_test_io_rw_simple(ahci
, bufsize
, sector
,
1533 io_cmds
[dma
][lba48
][IO_READ
],
1534 io_cmds
[dma
][lba48
][IO_WRITE
]);
1535 ahci_shutdown(ahci
);
1539 * Demultiplex the test data and invoke the actual test routine.
1541 static void test_io_interface(gconstpointer opaque
)
1543 AHCIIOTestOptions
*opts
= (AHCIIOTestOptions
*)opaque
;
1547 switch (opts
->length
) {
1555 bufsize
= 4096 * 64;
1561 g_assert_not_reached();
1564 sector
= offset_sector(opts
->offset
, opts
->address_type
, bufsize
);
1565 test_io_rw_interface(opts
->address_type
, opts
->io_type
, bufsize
, sector
);
1570 static void create_ahci_io_test(enum IOMode type
, enum AddrMode addr
,
1571 enum BuffLen len
, enum OffsetType offset
)
1574 AHCIIOTestOptions
*opts
= g_malloc(sizeof(AHCIIOTestOptions
));
1577 opts
->address_type
= addr
;
1578 opts
->io_type
= type
;
1579 opts
->offset
= offset
;
1581 name
= g_strdup_printf("ahci/io/%s/%s/%s/%s",
1583 addr_mode_str
[addr
],
1585 offset_str
[offset
]);
1587 qtest_add_data_func(name
, opts
, test_io_interface
);
1591 /******************************************************************************/
1593 int main(int argc
, char **argv
)
1601 static struct option long_options
[] = {
1602 {"pedantic", no_argument
, 0, 'p' },
1606 /* Should be first to utilize g_test functionality, So we can see errors. */
1607 g_test_init(&argc
, &argv
, NULL
);
1610 c
= getopt_long(argc
, argv
, "", long_options
, NULL
);
1621 fprintf(stderr
, "Unrecognized ahci_test option.\n");
1622 g_assert_not_reached();
1626 /* Check architecture */
1627 arch
= qtest_get_arch();
1628 if (strcmp(arch
, "i386") && strcmp(arch
, "x86_64")) {
1629 g_test_message("Skipping test for non-x86");
1633 /* Create a temporary image */
1634 fd
= mkstemp(tmp_path
);
1637 mkqcow2(tmp_path
, TEST_IMAGE_SIZE_MB
);
1640 /* Create temporary blkdebug instructions */
1641 fd
= mkstemp(debug_path
);
1645 /* Reserve a hollow file to use as a socket for migration tests */
1646 fd
= mkstemp(mig_socket
);
1651 qtest_add_func("/ahci/sanity", test_sanity
);
1652 qtest_add_func("/ahci/pci_spec", test_pci_spec
);
1653 qtest_add_func("/ahci/pci_enable", test_pci_enable
);
1654 qtest_add_func("/ahci/hba_spec", test_hba_spec
);
1655 qtest_add_func("/ahci/hba_enable", test_hba_enable
);
1656 qtest_add_func("/ahci/identify", test_identify
);
1658 for (i
= MODE_BEGIN
; i
< NUM_MODES
; i
++) {
1659 for (j
= ADDR_MODE_BEGIN
; j
< NUM_ADDR_MODES
; j
++) {
1660 for (k
= LEN_BEGIN
; k
< NUM_LENGTHS
; k
++) {
1661 for (m
= OFFSET_BEGIN
; m
< NUM_OFFSETS
; m
++) {
1662 create_ahci_io_test(i
, j
, k
, m
);
1668 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented
);
1670 qtest_add_func("/ahci/flush/simple", test_flush
);
1671 qtest_add_func("/ahci/flush/retry", test_flush_retry
);
1672 qtest_add_func("/ahci/flush/migrate", test_flush_migrate
);
1674 qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity
);
1675 qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma
);
1676 qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma
);
1677 qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma
);
1679 qtest_add_func("/ahci/max", test_max
);
1680 qtest_add_func("/ahci/reset", test_reset
);
1682 qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple
);
1683 qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq
);
1684 qtest_add_func("/ahci/io/ncq/retry", test_halted_ncq
);
1685 qtest_add_func("/ahci/migrate/ncq/halted", test_migrate_halted_ncq
);