tests/i440fx-test.c

   1 /*
   2  * qtest I440FX test case
   3  *
   4  * Copyright IBM, Corp. 2012-2013
   5  * Copyright Red Hat, Inc. 2013
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *  Laszlo Ersek      <lersek@redhat.com>
  10  *
  11  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  12  * See the COPYING file in the top-level directory.
  13  */
  14
  15 #include "qemu/osdep.h"
  16 #include <glib.h>
  17 #include <string.h>
  18 #include <stdio.h>
  19 #include <unistd.h>
  20 #include <errno.h>
  21 #include <sys/mman.h>
  22 #include <stdlib.h>
  23
  24 #include "libqtest.h"
  25 #include "libqos/pci.h"
  26 #include "libqos/pci-pc.h"
  27 #include "hw/pci/pci_regs.h"
  28
  29 #define BROKEN 1
  30
  31 typedef struct TestData
  32 {
  33     int num_cpus;
  34 } TestData;
  35
  36 typedef struct FirmwareTestFixture {
  37     /* decides whether we're testing -bios or -pflash */
  38     bool is_bios;
  39 } FirmwareTestFixture;
  40
  41 static QPCIBus *test_start_get_bus(const TestData *s)
  42 {
  43     char *cmdline;
  44
  45     cmdline = g_strdup_printf("-smp %d", s->num_cpus);
  46     qtest_start(cmdline);
  47     g_free(cmdline);
  48     return qpci_init_pc();
  49 }
  50
  51 static void test_i440fx_defaults(gconstpointer opaque)
  52 {
  53     const TestData *s = opaque;
  54     QPCIBus *bus;
  55     QPCIDevice *dev;
  56     uint32_t value;
  57
  58     bus = test_start_get_bus(s);
  59     dev = qpci_device_find(bus, QPCI_DEVFN(0, 0));
  60     g_assert(dev != NULL);
  61
  62     /* 3.2.2 */
  63     g_assert_cmpint(qpci_config_readw(dev, PCI_VENDOR_ID), ==, 0x8086);
  64     /* 3.2.3 */
  65     g_assert_cmpint(qpci_config_readw(dev, PCI_DEVICE_ID), ==, 0x1237);
  66 #ifndef BROKEN
  67     /* 3.2.4 */
  68     g_assert_cmpint(qpci_config_readw(dev, PCI_COMMAND), ==, 0x0006);
  69     /* 3.2.5 */
  70     g_assert_cmpint(qpci_config_readw(dev, PCI_STATUS), ==, 0x0280);
  71 #endif
  72     /* 3.2.7 */
  73     g_assert_cmpint(qpci_config_readb(dev, PCI_CLASS_PROG), ==, 0x00);
  74     g_assert_cmpint(qpci_config_readw(dev, PCI_CLASS_DEVICE), ==, 0x0600);
  75     /* 3.2.8 */
  76     g_assert_cmpint(qpci_config_readb(dev, PCI_LATENCY_TIMER), ==, 0x00);
  77     /* 3.2.9 */
  78     g_assert_cmpint(qpci_config_readb(dev, PCI_HEADER_TYPE), ==, 0x00);
  79     /* 3.2.10 */
  80     g_assert_cmpint(qpci_config_readb(dev, PCI_BIST), ==, 0x00);
  81
  82     /* 3.2.11 */
  83     value = qpci_config_readw(dev, 0x50); /* PMCCFG */
  84     if (s->num_cpus == 1) { /* WPE */
  85         g_assert(!(value & (1 << 15)));
  86     } else {
  87         g_assert((value & (1 << 15)));
  88     }
  89
  90     g_assert(!(value & (1 << 6))); /* EPTE */
  91
  92     /* 3.2.12 */
  93     g_assert_cmpint(qpci_config_readb(dev, 0x52), ==, 0x00); /* DETURBO */
  94     /* 3.2.13 */
  95 #ifndef BROKEN
  96     g_assert_cmpint(qpci_config_readb(dev, 0x53), ==, 0x80); /* DBC */
  97 #endif
  98     /* 3.2.14 */
  99     g_assert_cmpint(qpci_config_readb(dev, 0x54), ==, 0x00); /* AXC */
 100     /* 3.2.15 */
 101     g_assert_cmpint(qpci_config_readw(dev, 0x55), ==, 0x0000); /* DRT */
 102 #ifndef BROKEN
 103     /* 3.2.16 */
 104     g_assert_cmpint(qpci_config_readb(dev, 0x57), ==, 0x01); /* DRAMC */
 105     /* 3.2.17 */
 106     g_assert_cmpint(qpci_config_readb(dev, 0x58), ==, 0x10); /* DRAMT */
 107 #endif
 108     /* 3.2.18 */
 109     g_assert_cmpint(qpci_config_readb(dev, 0x59), ==, 0x00); /* PAM0 */
 110     g_assert_cmpint(qpci_config_readb(dev, 0x5A), ==, 0x00); /* PAM1 */
 111     g_assert_cmpint(qpci_config_readb(dev, 0x5B), ==, 0x00); /* PAM2 */
 112     g_assert_cmpint(qpci_config_readb(dev, 0x5C), ==, 0x00); /* PAM3 */
 113     g_assert_cmpint(qpci_config_readb(dev, 0x5D), ==, 0x00); /* PAM4 */
 114     g_assert_cmpint(qpci_config_readb(dev, 0x5E), ==, 0x00); /* PAM5 */
 115     g_assert_cmpint(qpci_config_readb(dev, 0x5F), ==, 0x00); /* PAM6 */
 116 #ifndef BROKEN
 117     /* 3.2.19 */
 118     g_assert_cmpint(qpci_config_readb(dev, 0x60), ==, 0x01); /* DRB0 */
 119     g_assert_cmpint(qpci_config_readb(dev, 0x61), ==, 0x01); /* DRB1 */
 120     g_assert_cmpint(qpci_config_readb(dev, 0x62), ==, 0x01); /* DRB2 */
 121     g_assert_cmpint(qpci_config_readb(dev, 0x63), ==, 0x01); /* DRB3 */
 122     g_assert_cmpint(qpci_config_readb(dev, 0x64), ==, 0x01); /* DRB4 */
 123     g_assert_cmpint(qpci_config_readb(dev, 0x65), ==, 0x01); /* DRB5 */
 124     g_assert_cmpint(qpci_config_readb(dev, 0x66), ==, 0x01); /* DRB6 */
 125     g_assert_cmpint(qpci_config_readb(dev, 0x67), ==, 0x01); /* DRB7 */
 126 #endif
 127     /* 3.2.20 */
 128     g_assert_cmpint(qpci_config_readb(dev, 0x68), ==, 0x00); /* FDHC */
 129     /* 3.2.21 */
 130     g_assert_cmpint(qpci_config_readb(dev, 0x70), ==, 0x00); /* MTT */
 131 #ifndef BROKEN
 132     /* 3.2.22 */
 133     g_assert_cmpint(qpci_config_readb(dev, 0x71), ==, 0x10); /* CLT */
 134 #endif
 135     /* 3.2.23 */
 136     g_assert_cmpint(qpci_config_readb(dev, 0x72), ==, 0x02); /* SMRAM */
 137     /* 3.2.24 */
 138     g_assert_cmpint(qpci_config_readb(dev, 0x90), ==, 0x00); /* ERRCMD */
 139     /* 3.2.25 */
 140     g_assert_cmpint(qpci_config_readb(dev, 0x91), ==, 0x00); /* ERRSTS */
 141     /* 3.2.26 */
 142     g_assert_cmpint(qpci_config_readb(dev, 0x93), ==, 0x00); /* TRC */
 143
 144     qtest_end();
 145 }
 146
 147 #define PAM_RE 1
 148 #define PAM_WE 2
 149
 150 static void pam_set(QPCIDevice *dev, int index, int flags)
 151 {
 152     int regno = 0x59 + (index / 2);
 153     uint8_t reg;
 154
 155     reg = qpci_config_readb(dev, regno);
 156     if (index & 1) {
 157         reg = (reg & 0x0F) | (flags << 4);
 158     } else {
 159         reg = (reg & 0xF0) | flags;
 160     }
 161     qpci_config_writeb(dev, regno, reg);
 162 }
 163
 164 static gboolean verify_area(uint32_t start, uint32_t end, uint8_t value)
 165 {
 166     uint32_t size = end - start + 1;
 167     gboolean ret = TRUE;
 168     uint8_t *data;
 169     int i;
 170
 171     data = g_malloc0(size);
 172     memread(start, data, size);
 173
 174     g_test_message("verify_area: data[0] = 0x%x", data[0]);
 175
 176     for (i = 0; i < size; i++) {
 177         if (data[i] != value) {
 178             ret = FALSE;
 179             break;
 180         }
 181     }
 182
 183     g_free(data);
 184
 185     return ret;
 186 }
 187
 188 static void write_area(uint32_t start, uint32_t end, uint8_t value)
 189 {
 190     uint32_t size = end - start + 1;
 191     uint8_t *data;
 192
 193     data = g_malloc(size);
 194     memset(data, value, size);
 195     memwrite(start, data, size);
 196
 197     g_free(data);
 198 }
 199
 200 static void test_i440fx_pam(gconstpointer opaque)
 201 {
 202     const TestData *s = opaque;
 203     QPCIBus *bus;
 204     QPCIDevice *dev;
 205     int i;
 206     static struct {
 207         uint32_t start;
 208         uint32_t end;
 209     } pam_area[] = {
 210         { 0, 0 },             /* Reserved */
 211         { 0xF0000, 0xFFFFF }, /* BIOS Area */
 212         { 0xC0000, 0xC3FFF }, /* Option ROM */
 213         { 0xC4000, 0xC7FFF }, /* Option ROM */
 214         { 0xC8000, 0xCBFFF }, /* Option ROM */
 215         { 0xCC000, 0xCFFFF }, /* Option ROM */
 216         { 0xD0000, 0xD3FFF }, /* Option ROM */
 217         { 0xD4000, 0xD7FFF }, /* Option ROM */
 218         { 0xD8000, 0xDBFFF }, /* Option ROM */
 219         { 0xDC000, 0xDFFFF }, /* Option ROM */
 220         { 0xE0000, 0xE3FFF }, /* BIOS Extension */
 221         { 0xE4000, 0xE7FFF }, /* BIOS Extension */
 222         { 0xE8000, 0xEBFFF }, /* BIOS Extension */
 223         { 0xEC000, 0xEFFFF }, /* BIOS Extension */
 224     };
 225
 226     bus = test_start_get_bus(s);
 227     dev = qpci_device_find(bus, QPCI_DEVFN(0, 0));
 228     g_assert(dev != NULL);
 229
 230     for (i = 0; i < ARRAY_SIZE(pam_area); i++) {
 231         if (pam_area[i].start == pam_area[i].end) {
 232             continue;
 233         }
 234
 235         g_test_message("Checking area 0x%05x..0x%05x",
 236                        pam_area[i].start, pam_area[i].end);
 237         /* Switch to RE for the area */
 238         pam_set(dev, i, PAM_RE);
 239         /* Verify the RAM is all zeros */
 240         g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0));
 241
 242         /* Switch to WE for the area */
 243         pam_set(dev, i, PAM_RE | PAM_WE);
 244         /* Write out a non-zero mask to the full area */
 245         write_area(pam_area[i].start, pam_area[i].end, 0x42);
 246
 247 #ifndef BROKEN
 248         /* QEMU only supports a limited form of PAM */
 249
 250         /* Switch to !RE for the area */
 251         pam_set(dev, i, PAM_WE);
 252         /* Verify the area is not our mask */
 253         g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x42));
 254 #endif
 255
 256         /* Verify the area is our new mask */
 257         g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x42));
 258
 259         /* Write out a new mask */
 260         write_area(pam_area[i].start, pam_area[i].end, 0x82);
 261
 262 #ifndef BROKEN
 263         /* QEMU only supports a limited form of PAM */
 264
 265         /* Verify the area is not our mask */
 266         g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 267
 268         /* Switch to RE for the area */
 269         pam_set(dev, i, PAM_RE | PAM_WE);
 270 #endif
 271         /* Verify the area is our new mask */
 272         g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 273
 274         /* Reset area */
 275         pam_set(dev, i, 0);
 276
 277         /* Verify the area is not our new mask */
 278         g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 279     }
 280     qtest_end();
 281 }
 282
 283 #define BLOB_SIZE ((size_t)65536)
 284 #define ISA_BIOS_MAXSZ ((size_t)(128 * 1024))
 285
 286 /* Create a blob file, and return its absolute pathname as a dynamically
 287  * allocated string.
 288  * The file is closed before the function returns.
 289  * In case of error, NULL is returned. The function prints the error message.
 290  */
 291 static char *create_blob_file(void)
 292 {
 293     int ret, fd;
 294     char *pathname;
 295     GError *error = NULL;
 296
 297     ret = -1;
 298     fd = g_file_open_tmp("blob_XXXXXX", &pathname, &error);
 299     if (fd == -1) {
 300         fprintf(stderr, "unable to create blob file: %s\n", error->message);
 301         g_error_free(error);
 302     } else {
 303         if (ftruncate(fd, BLOB_SIZE) == -1) {
 304             fprintf(stderr, "ftruncate(\"%s\", %zu): %s\n", pathname,
 305                     BLOB_SIZE, strerror(errno));
 306         } else {
 307             void *buf;
 308
 309             buf = mmap(NULL, BLOB_SIZE, PROT_WRITE, MAP_SHARED, fd, 0);
 310             if (buf == MAP_FAILED) {
 311                 fprintf(stderr, "mmap(\"%s\", %zu): %s\n", pathname, BLOB_SIZE,
 312                         strerror(errno));
 313             } else {
 314                 size_t i;
 315
 316                 for (i = 0; i < BLOB_SIZE; ++i) {
 317                     ((uint8_t *)buf)[i] = i;
 318                 }
 319                 munmap(buf, BLOB_SIZE);
 320                 ret = 0;
 321             }
 322         }
 323         close(fd);
 324         if (ret == -1) {
 325             unlink(pathname);
 326             g_free(pathname);
 327         }
 328     }
 329
 330     return ret == -1 ? NULL : pathname;
 331 }
 332
 333 static void test_i440fx_firmware(FirmwareTestFixture *fixture,
 334                                  gconstpointer user_data)
 335 {
 336     char *fw_pathname, *cmdline;
 337     uint8_t *buf;
 338     size_t i, isa_bios_size;
 339
 340     fw_pathname = create_blob_file();
 341     g_assert(fw_pathname != NULL);
 342
 343     /* Better hope the user didn't put metacharacters in TMPDIR and co. */
 344     cmdline = g_strdup_printf("-S %s%s", fixture->is_bios
 345                                          ? "-bios "
 346                                          : "-drive if=pflash,format=raw,file=",
 347                               fw_pathname);
 348     g_test_message("qemu cmdline: %s", cmdline);
 349     qtest_start(cmdline);
 350     g_free(cmdline);
 351
 352     /* QEMU has loaded the firmware (because qtest_start() only returns after
 353      * the QMP handshake completes). We must unlink the firmware blob right
 354      * here, because any assertion firing below would leak it in the
 355      * filesystem. This is also the reason why we recreate the blob every time
 356      * this function is invoked.
 357      */
 358     unlink(fw_pathname);
 359     g_free(fw_pathname);
 360
 361     /* check below 4G */
 362     buf = g_malloc0(BLOB_SIZE);
 363     memread(0x100000000ULL - BLOB_SIZE, buf, BLOB_SIZE);
 364     for (i = 0; i < BLOB_SIZE; ++i) {
 365         g_assert_cmphex(buf[i], ==, (uint8_t)i);
 366     }
 367
 368     /* check in ISA space too */
 369     memset(buf, 0, BLOB_SIZE);
 370     isa_bios_size = ISA_BIOS_MAXSZ < BLOB_SIZE ? ISA_BIOS_MAXSZ : BLOB_SIZE;
 371     memread(0x100000 - isa_bios_size, buf, isa_bios_size);
 372     for (i = 0; i < isa_bios_size; ++i) {
 373         g_assert_cmphex(buf[i], ==,
 374                         (uint8_t)((BLOB_SIZE - isa_bios_size) + i));
 375     }
 376
 377     g_free(buf);
 378     qtest_end();
 379 }
 380
 381 static void add_firmware_test(const char *testpath,
 382                               void (*setup_fixture)(FirmwareTestFixture *f,
 383                                                     gconstpointer test_data))
 384 {
 385     qtest_add(testpath, FirmwareTestFixture, NULL, setup_fixture,
 386               test_i440fx_firmware, NULL);
 387 }
 388
 389 static void request_bios(FirmwareTestFixture *fixture,
 390                          gconstpointer user_data)
 391 {
 392     fixture->is_bios = true;
 393 }
 394
 395 static void request_pflash(FirmwareTestFixture *fixture,
 396                            gconstpointer user_data)
 397 {
 398     fixture->is_bios = false;
 399 }
 400
 401 int main(int argc, char **argv)
 402 {
 403     TestData data;
 404     int ret;
 405
 406     g_test_init(&argc, &argv, NULL);
 407
 408     data.num_cpus = 1;
 409
 410     qtest_add_data_func("i440fx/defaults", &data, test_i440fx_defaults);
 411     qtest_add_data_func("i440fx/pam", &data, test_i440fx_pam);
 412     add_firmware_test("i440fx/firmware/bios", request_bios);
 413     add_firmware_test("i440fx/firmware/pflash", request_pflash);
 414
 415     ret = g_test_run();
 416     return ret;
 417 }