tests/i440fx-test.c

   1 /*
   2  * qtest I440FX test case
   3  *
   4  * Copyright IBM, Corp. 2012-2013
   5  * Copyright Red Hat, Inc. 2013
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *  Laszlo Ersek      <lersek@redhat.com>
  10  *
  11  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  12  * See the COPYING file in the top-level directory.
  13  */
  14
  15 #include "libqos/pci.h"
  16 #include "libqos/pci-pc.h"
  17 #include "libqtest.h"
  18
  19 #include "hw/pci/pci_regs.h"
  20
  21 #include <glib.h>
  22 #include <string.h>
  23
  24 #define BROKEN 1
  25
  26 #define ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0]))
  27
  28 typedef struct TestData
  29 {
  30     int num_cpus;
  31 } TestData;
  32
  33 static QPCIBus *test_start_get_bus(const TestData *s)
  34 {
  35     char *cmdline;
  36
  37     cmdline = g_strdup_printf("-smp %d", s->num_cpus);
  38     qtest_start(cmdline);
  39     g_free(cmdline);
  40     return qpci_init_pc();
  41 }
  42
  43 static void test_i440fx_defaults(gconstpointer opaque)
  44 {
  45     const TestData *s = opaque;
  46     QPCIBus *bus;
  47     QPCIDevice *dev;
  48     uint32_t value;
  49
  50     bus = test_start_get_bus(s);
  51     dev = qpci_device_find(bus, QPCI_DEVFN(0, 0));
  52     g_assert(dev != NULL);
  53
  54     /* 3.2.2 */
  55     g_assert_cmpint(qpci_config_readw(dev, PCI_VENDOR_ID), ==, 0x8086);
  56     /* 3.2.3 */
  57     g_assert_cmpint(qpci_config_readw(dev, PCI_DEVICE_ID), ==, 0x1237);
  58 #ifndef BROKEN
  59     /* 3.2.4 */
  60     g_assert_cmpint(qpci_config_readw(dev, PCI_COMMAND), ==, 0x0006);
  61     /* 3.2.5 */
  62     g_assert_cmpint(qpci_config_readw(dev, PCI_STATUS), ==, 0x0280);
  63 #endif
  64     /* 3.2.7 */
  65     g_assert_cmpint(qpci_config_readb(dev, PCI_CLASS_PROG), ==, 0x00);
  66     g_assert_cmpint(qpci_config_readw(dev, PCI_CLASS_DEVICE), ==, 0x0600);
  67     /* 3.2.8 */
  68     g_assert_cmpint(qpci_config_readb(dev, PCI_LATENCY_TIMER), ==, 0x00);
  69     /* 3.2.9 */
  70     g_assert_cmpint(qpci_config_readb(dev, PCI_HEADER_TYPE), ==, 0x00);
  71     /* 3.2.10 */
  72     g_assert_cmpint(qpci_config_readb(dev, PCI_BIST), ==, 0x00);
  73
  74     /* 3.2.11 */
  75     value = qpci_config_readw(dev, 0x50); /* PMCCFG */
  76     if (s->num_cpus == 1) { /* WPE */
  77         g_assert(!(value & (1 << 15)));
  78     } else {
  79         g_assert((value & (1 << 15)));
  80     }
  81
  82     g_assert(!(value & (1 << 6))); /* EPTE */
  83
  84     /* 3.2.12 */
  85     g_assert_cmpint(qpci_config_readb(dev, 0x52), ==, 0x00); /* DETURBO */
  86     /* 3.2.13 */
  87 #ifndef BROKEN
  88     g_assert_cmpint(qpci_config_readb(dev, 0x53), ==, 0x80); /* DBC */
  89 #endif
  90     /* 3.2.14 */
  91     g_assert_cmpint(qpci_config_readb(dev, 0x54), ==, 0x00); /* AXC */
  92     /* 3.2.15 */
  93     g_assert_cmpint(qpci_config_readw(dev, 0x55), ==, 0x0000); /* DRT */
  94 #ifndef BROKEN
  95     /* 3.2.16 */
  96     g_assert_cmpint(qpci_config_readb(dev, 0x57), ==, 0x01); /* DRAMC */
  97     /* 3.2.17 */
  98     g_assert_cmpint(qpci_config_readb(dev, 0x58), ==, 0x10); /* DRAMT */
  99 #endif
 100     /* 3.2.18 */
 101     g_assert_cmpint(qpci_config_readb(dev, 0x59), ==, 0x00); /* PAM0 */
 102     g_assert_cmpint(qpci_config_readb(dev, 0x5A), ==, 0x00); /* PAM1 */
 103     g_assert_cmpint(qpci_config_readb(dev, 0x5B), ==, 0x00); /* PAM2 */
 104     g_assert_cmpint(qpci_config_readb(dev, 0x5C), ==, 0x00); /* PAM3 */
 105     g_assert_cmpint(qpci_config_readb(dev, 0x5D), ==, 0x00); /* PAM4 */
 106     g_assert_cmpint(qpci_config_readb(dev, 0x5E), ==, 0x00); /* PAM5 */
 107     g_assert_cmpint(qpci_config_readb(dev, 0x5F), ==, 0x00); /* PAM6 */
 108 #ifndef BROKEN
 109     /* 3.2.19 */
 110     g_assert_cmpint(qpci_config_readb(dev, 0x60), ==, 0x01); /* DRB0 */
 111     g_assert_cmpint(qpci_config_readb(dev, 0x61), ==, 0x01); /* DRB1 */
 112     g_assert_cmpint(qpci_config_readb(dev, 0x62), ==, 0x01); /* DRB2 */
 113     g_assert_cmpint(qpci_config_readb(dev, 0x63), ==, 0x01); /* DRB3 */
 114     g_assert_cmpint(qpci_config_readb(dev, 0x64), ==, 0x01); /* DRB4 */
 115     g_assert_cmpint(qpci_config_readb(dev, 0x65), ==, 0x01); /* DRB5 */
 116     g_assert_cmpint(qpci_config_readb(dev, 0x66), ==, 0x01); /* DRB6 */
 117     g_assert_cmpint(qpci_config_readb(dev, 0x67), ==, 0x01); /* DRB7 */
 118 #endif
 119     /* 3.2.20 */
 120     g_assert_cmpint(qpci_config_readb(dev, 0x68), ==, 0x00); /* FDHC */
 121     /* 3.2.21 */
 122     g_assert_cmpint(qpci_config_readb(dev, 0x70), ==, 0x00); /* MTT */
 123 #ifndef BROKEN
 124     /* 3.2.22 */
 125     g_assert_cmpint(qpci_config_readb(dev, 0x71), ==, 0x10); /* CLT */
 126 #endif
 127     /* 3.2.23 */
 128     g_assert_cmpint(qpci_config_readb(dev, 0x72), ==, 0x02); /* SMRAM */
 129     /* 3.2.24 */
 130     g_assert_cmpint(qpci_config_readb(dev, 0x90), ==, 0x00); /* ERRCMD */
 131     /* 3.2.25 */
 132     g_assert_cmpint(qpci_config_readb(dev, 0x91), ==, 0x00); /* ERRSTS */
 133     /* 3.2.26 */
 134     g_assert_cmpint(qpci_config_readb(dev, 0x93), ==, 0x00); /* TRC */
 135
 136     qtest_end();
 137 }
 138
 139 #define PAM_RE 1
 140 #define PAM_WE 2
 141
 142 static void pam_set(QPCIDevice *dev, int index, int flags)
 143 {
 144     int regno = 0x59 + (index / 2);
 145     uint8_t reg;
 146
 147     reg = qpci_config_readb(dev, regno);
 148     if (index & 1) {
 149         reg = (reg & 0x0F) | (flags << 4);
 150     } else {
 151         reg = (reg & 0xF0) | flags;
 152     }
 153     qpci_config_writeb(dev, regno, reg);
 154 }
 155
 156 static gboolean verify_area(uint32_t start, uint32_t end, uint8_t value)
 157 {
 158     uint32_t size = end - start + 1;
 159     gboolean ret = TRUE;
 160     uint8_t *data;
 161     int i;
 162
 163     data = g_malloc0(size);
 164     memread(start, data, size);
 165
 166     g_test_message("verify_area: data[0] = 0x%x", data[0]);
 167
 168     for (i = 0; i < size; i++) {
 169         if (data[i] != value) {
 170             ret = FALSE;
 171             break;
 172         }
 173     }
 174
 175     g_free(data);
 176
 177     return ret;
 178 }
 179
 180 static void write_area(uint32_t start, uint32_t end, uint8_t value)
 181 {
 182     uint32_t size = end - start + 1;
 183     uint8_t *data;
 184
 185     data = g_malloc0(size);
 186     memset(data, value, size);
 187     memwrite(start, data, size);
 188
 189     g_free(data);
 190 }
 191
 192 static void test_i440fx_pam(gconstpointer opaque)
 193 {
 194     const TestData *s = opaque;
 195     QPCIBus *bus;
 196     QPCIDevice *dev;
 197     int i;
 198     static struct {
 199         uint32_t start;
 200         uint32_t end;
 201     } pam_area[] = {
 202         { 0, 0 },             /* Reserved */
 203         { 0xF0000, 0xFFFFF }, /* BIOS Area */
 204         { 0xC0000, 0xC3FFF }, /* Option ROM */
 205         { 0xC4000, 0xC7FFF }, /* Option ROM */
 206         { 0xC8000, 0xCBFFF }, /* Option ROM */
 207         { 0xCC000, 0xCFFFF }, /* Option ROM */
 208         { 0xD0000, 0xD3FFF }, /* Option ROM */
 209         { 0xD4000, 0xD7FFF }, /* Option ROM */
 210         { 0xD8000, 0xDBFFF }, /* Option ROM */
 211         { 0xDC000, 0xDFFFF }, /* Option ROM */
 212         { 0xE0000, 0xE3FFF }, /* BIOS Extension */
 213         { 0xE4000, 0xE7FFF }, /* BIOS Extension */
 214         { 0xE8000, 0xEBFFF }, /* BIOS Extension */
 215         { 0xEC000, 0xEFFFF }, /* BIOS Extension */
 216     };
 217
 218     bus = test_start_get_bus(s);
 219     dev = qpci_device_find(bus, QPCI_DEVFN(0, 0));
 220     g_assert(dev != NULL);
 221
 222     for (i = 0; i < ARRAY_SIZE(pam_area); i++) {
 223         if (pam_area[i].start == pam_area[i].end) {
 224             continue;
 225         }
 226
 227         g_test_message("Checking area 0x%05x..0x%05x",
 228                        pam_area[i].start, pam_area[i].end);
 229         /* Switch to RE for the area */
 230         pam_set(dev, i, PAM_RE);
 231         /* Verify the RAM is all zeros */
 232         g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0));
 233
 234         /* Switch to WE for the area */
 235         pam_set(dev, i, PAM_RE | PAM_WE);
 236         /* Write out a non-zero mask to the full area */
 237         write_area(pam_area[i].start, pam_area[i].end, 0x42);
 238
 239 #ifndef BROKEN
 240         /* QEMU only supports a limited form of PAM */
 241
 242         /* Switch to !RE for the area */
 243         pam_set(dev, i, PAM_WE);
 244         /* Verify the area is not our mask */
 245         g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x42));
 246 #endif
 247
 248         /* Verify the area is our new mask */
 249         g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x42));
 250
 251         /* Write out a new mask */
 252         write_area(pam_area[i].start, pam_area[i].end, 0x82);
 253
 254 #ifndef BROKEN
 255         /* QEMU only supports a limited form of PAM */
 256
 257         /* Verify the area is not our mask */
 258         g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 259
 260         /* Switch to RE for the area */
 261         pam_set(dev, i, PAM_RE | PAM_WE);
 262 #endif
 263         /* Verify the area is our new mask */
 264         g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 265
 266         /* Reset area */
 267         pam_set(dev, i, 0);
 268
 269         /* Verify the area is not our new mask */
 270         g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 271     }
 272     qtest_end();
 273 }
 274
 275 int main(int argc, char **argv)
 276 {
 277     TestData data;
 278     int ret;
 279
 280     g_test_init(&argc, &argv, NULL);
 281
 282     data.num_cpus = 1;
 283
 284     g_test_add_data_func("/i440fx/defaults", &data, test_i440fx_defaults);
 285     g_test_add_data_func("/i440fx/pam", &data, test_i440fx_pam);
 286
 287     ret = g_test_run();
 288     return ret;
 289 }