tests/mir-opt/inline/inline_instruction_set.t32.Inline.diff

   1 - // MIR for `t32` before Inline
   2 + // MIR for `t32` after Inline
   3
   4   fn t32() -> () {
   5       let mut _0: ();                      // return place in scope 0 at $DIR/inline_instruction_set.rs:+0:14: +0:14
   6       let _1: ();                          // in scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
   7       let _2: ();                          // in scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
   8       let _3: ();                          // in scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
   9       let _4: ();                          // in scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
  10 +     scope 1 (inlined instruction_set_t32) { // at $DIR/inline_instruction_set.rs:50:5: 50:26
  11 +     }
  12 +     scope 2 (inlined instruction_set_default) { // at $DIR/inline_instruction_set.rs:51:5: 51:30
  13 +     }
  14
  15       bb0: {
  16           StorageLive(_1);                 // scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
  17           _1 = instruction_set_a32() -> [return: bb1, unwind unreachable]; // scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
  18                                            // mir::Constant
  19                                            // + span: $DIR/inline_instruction_set.rs:49:5: 49:24
  20                                            // + literal: Const { ty: fn() {instruction_set_a32}, val: Value(<ZST>) }
  21       }
  22
  23       bb1: {
  24           StorageDead(_1);                 // scope 0 at $DIR/inline_instruction_set.rs:+1:26: +1:27
  25           StorageLive(_2);                 // scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
  26 -         _2 = instruction_set_t32() -> [return: bb2, unwind unreachable]; // scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
  27 -                                          // mir::Constant
  28 -                                          // + span: $DIR/inline_instruction_set.rs:50:5: 50:24
  29 -                                          // + literal: Const { ty: fn() {instruction_set_t32}, val: Value(<ZST>) }
  30 -     }
  31 -
  32 -     bb2: {
  33           StorageDead(_2);                 // scope 0 at $DIR/inline_instruction_set.rs:+2:26: +2:27
  34           StorageLive(_3);                 // scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
  35 -         _3 = instruction_set_default() -> [return: bb3, unwind unreachable]; // scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
  36 -                                          // mir::Constant
  37 -                                          // + span: $DIR/inline_instruction_set.rs:51:5: 51:28
  38 -                                          // + literal: Const { ty: fn() {instruction_set_default}, val: Value(<ZST>) }
  39 -     }
  40 -
  41 -     bb3: {
  42           StorageDead(_3);                 // scope 0 at $DIR/inline_instruction_set.rs:+3:30: +3:31
  43           StorageLive(_4);                 // scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
  44 -         _4 = inline_always_and_using_inline_asm() -> [return: bb4, unwind unreachable]; // scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
  45 +         _4 = inline_always_and_using_inline_asm() -> [return: bb2, unwind unreachable]; // scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
  46                                            // mir::Constant
  47                                            // + span: $DIR/inline_instruction_set.rs:52:5: 52:39
  48                                            // + literal: Const { ty: fn() {inline_always_and_using_inline_asm}, val: Value(<ZST>) }
  49       }
  50
  51 -     bb4: {
  52 +     bb2: {
  53           StorageDead(_4);                 // scope 0 at $DIR/inline_instruction_set.rs:+4:41: +4:42
  54           _0 = const ();                   // scope 0 at $DIR/inline_instruction_set.rs:+0:14: +5:2
  55           return;                          // scope 0 at $DIR/inline_instruction_set.rs:+5:2: +5:2
  56       }
  57   }
  58