tests/tcg/xtensa/test_sr.S

   1 .include "macros.inc"
   2
   3 test_suite sr
   4
   5 .macro  sr_op sym, op_sym, op_byte, sr
   6     .if \sym
   7     \op_sym a4, \sr
   8     .else
   9     .byte 0x40, \sr, \op_byte
  10     .endif
  11 .endm
  12
  13 .macro  test_sr_op sym, mask, op, op_byte, sr
  14     movi    a4, 0
  15     .if (\mask)
  16     set_vector kernel, 0
  17     sr_op   \sym, \op, \op_byte, \sr
  18     .else
  19     set_vector kernel, 2f
  20 1:
  21     sr_op   \sym, \op, \op_byte, \sr
  22     test_fail
  23 2:
  24     reset_ps
  25     rsr     a2, exccause
  26     assert  eqi, a2, 0
  27     rsr     a2, epc1
  28     movi    a3, 1b
  29     assert  eq, a2, a3
  30     .endif
  31 .endm
  32
  33 .macro  test_sr_mask sr, sym, mask
  34 test \sr
  35     test_sr_op \sym, \mask & 1, rsr, 0x03, \sr
  36     test_sr_op \sym, \mask & 2, wsr, 0x13, \sr
  37     test_sr_op \sym, \mask & 4, xsr, 0x61, \sr
  38 test_end
  39 .endm
  40
  41 .macro  test_sr sr, conf
  42     test_sr_mask    \sr, \conf, 7
  43 .endm
  44
  45 test_sr acchi, 1
  46 test_sr acclo, 1
  47 test_sr_mask /*atomctl*/99, 0, 0
  48 test_sr_mask /*br*/4, 0, 0
  49 test_sr_mask /*cacheattr*/98, 0, 0
  50 test_sr ccompare0, 1
  51 test_sr ccount, 1
  52 test_sr cpenable, 1
  53 test_sr dbreaka0, 1
  54 test_sr dbreakc0, 1
  55 test_sr_mask debugcause, 1, 1
  56 test_sr depc, 1
  57 test_sr dtlbcfg, 1
  58 test_sr epc1, 1
  59 test_sr epc2, 1
  60 test_sr eps2, 1
  61 test_sr exccause, 1
  62 test_sr excsave1, 1
  63 test_sr excsave2, 1
  64 test_sr excvaddr, 1
  65 test_sr ibreaka0, 1
  66 test_sr ibreakenable, 1
  67 test_sr icount, 1
  68 test_sr icountlevel, 1
  69 test_sr_mask /*intclear*/227, 0, 2
  70 test_sr_mask /*interrupt*/226, 0, 3
  71 test_sr intenable, 1
  72 test_sr itlbcfg, 1
  73 test_sr lbeg, 1
  74 test_sr lcount, 1
  75 test_sr lend, 1
  76 test_sr litbase, 1
  77 test_sr m0, 1
  78 test_sr misc0, 1
  79 test_sr_mask /*prefctl*/40, 0, 0
  80 test_sr_mask /*prid*/235, 0, 1
  81 test_sr ps, 1
  82 test_sr ptevaddr, 1
  83 test_sr rasid, 1
  84 test_sr sar, 1
  85 test_sr scompare1, 1
  86 test_sr vecbase, 1
  87 test_sr windowbase, 1
  88 test_sr windowstart, 1
  89
  90 test_suite_end