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1 /*
2 * Performance events:
3 *
4 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra
7 *
8 * Data type definitions, declarations, prototypes.
9 *
10 * Started by: Thomas Gleixner and Ingo Molnar
11 *
12 * For licencing details see kernel-base/COPYING
13 */
14 #ifndef _UAPI_LINUX_PERF_EVENT_H
15 #define _UAPI_LINUX_PERF_EVENT_H
16
17 #include <linux/types.h>
18 #include <linux/ioctl.h>
19 #include <asm/byteorder.h>
20
21 /*
22 * User-space ABI bits:
23 */
24
25 /*
26 * attr.type
27 */
28 enum perf_type_id {
29 PERF_TYPE_HARDWARE = 0,
30 PERF_TYPE_SOFTWARE = 1,
31 PERF_TYPE_TRACEPOINT = 2,
32 PERF_TYPE_HW_CACHE = 3,
33 PERF_TYPE_RAW = 4,
34 PERF_TYPE_BREAKPOINT = 5,
35
36 PERF_TYPE_MAX, /* non-ABI */
37 };
38
39 /*
40 * Generalized performance event event_id types, used by the
41 * attr.event_id parameter of the sys_perf_event_open()
42 * syscall:
43 */
44 enum perf_hw_id {
45 /*
46 * Common hardware events, generalized by the kernel:
47 */
48 PERF_COUNT_HW_CPU_CYCLES = 0,
49 PERF_COUNT_HW_INSTRUCTIONS = 1,
50 PERF_COUNT_HW_CACHE_REFERENCES = 2,
51 PERF_COUNT_HW_CACHE_MISSES = 3,
52 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4,
53 PERF_COUNT_HW_BRANCH_MISSES = 5,
54 PERF_COUNT_HW_BUS_CYCLES = 6,
55 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7,
56 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8,
57 PERF_COUNT_HW_REF_CPU_CYCLES = 9,
58
59 PERF_COUNT_HW_MAX, /* non-ABI */
60 };
61
62 /*
63 * Generalized hardware cache events:
64 *
65 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x
66 * { read, write, prefetch } x
67 * { accesses, misses }
68 */
69 enum perf_hw_cache_id {
70 PERF_COUNT_HW_CACHE_L1D = 0,
71 PERF_COUNT_HW_CACHE_L1I = 1,
72 PERF_COUNT_HW_CACHE_LL = 2,
73 PERF_COUNT_HW_CACHE_DTLB = 3,
74 PERF_COUNT_HW_CACHE_ITLB = 4,
75 PERF_COUNT_HW_CACHE_BPU = 5,
76 PERF_COUNT_HW_CACHE_NODE = 6,
77
78 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */
79 };
80
81 enum perf_hw_cache_op_id {
82 PERF_COUNT_HW_CACHE_OP_READ = 0,
83 PERF_COUNT_HW_CACHE_OP_WRITE = 1,
84 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2,
85
86 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */
87 };
88
89 enum perf_hw_cache_op_result_id {
90 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0,
91 PERF_COUNT_HW_CACHE_RESULT_MISS = 1,
92
93 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */
94 };
95
96 /*
97 * Special "software" events provided by the kernel, even if the hardware
98 * does not support performance events. These events measure various
99 * physical and sw events of the kernel (and allow the profiling of them as
100 * well):
101 */
102 enum perf_sw_ids {
103 PERF_COUNT_SW_CPU_CLOCK = 0,
104 PERF_COUNT_SW_TASK_CLOCK = 1,
105 PERF_COUNT_SW_PAGE_FAULTS = 2,
106 PERF_COUNT_SW_CONTEXT_SWITCHES = 3,
107 PERF_COUNT_SW_CPU_MIGRATIONS = 4,
108 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5,
109 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6,
110 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7,
111 PERF_COUNT_SW_EMULATION_FAULTS = 8,
112 PERF_COUNT_SW_DUMMY = 9,
113 PERF_COUNT_SW_BPF_OUTPUT = 10,
114
115 PERF_COUNT_SW_MAX, /* non-ABI */
116 };
117
118 /*
119 * Bits that can be set in attr.sample_type to request information
120 * in the overflow packets.
121 */
122 enum perf_event_sample_format {
123 PERF_SAMPLE_IP = 1U << 0,
124 PERF_SAMPLE_TID = 1U << 1,
125 PERF_SAMPLE_TIME = 1U << 2,
126 PERF_SAMPLE_ADDR = 1U << 3,
127 PERF_SAMPLE_READ = 1U << 4,
128 PERF_SAMPLE_CALLCHAIN = 1U << 5,
129 PERF_SAMPLE_ID = 1U << 6,
130 PERF_SAMPLE_CPU = 1U << 7,
131 PERF_SAMPLE_PERIOD = 1U << 8,
132 PERF_SAMPLE_STREAM_ID = 1U << 9,
133 PERF_SAMPLE_RAW = 1U << 10,
134 PERF_SAMPLE_BRANCH_STACK = 1U << 11,
135 PERF_SAMPLE_REGS_USER = 1U << 12,
136 PERF_SAMPLE_STACK_USER = 1U << 13,
137 PERF_SAMPLE_WEIGHT = 1U << 14,
138 PERF_SAMPLE_DATA_SRC = 1U << 15,
139 PERF_SAMPLE_IDENTIFIER = 1U << 16,
140 PERF_SAMPLE_TRANSACTION = 1U << 17,
141 PERF_SAMPLE_REGS_INTR = 1U << 18,
142
143 PERF_SAMPLE_MAX = 1U << 19, /* non-ABI */
144 };
145
146 /*
147 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set
148 *
149 * If the user does not pass priv level information via branch_sample_type,
150 * the kernel uses the event's priv level. Branch and event priv levels do
151 * not have to match. Branch priv level is checked for permissions.
152 *
153 * The branch types can be combined, however BRANCH_ANY covers all types
154 * of branches and therefore it supersedes all the other types.
155 */
156 enum perf_branch_sample_type_shift {
157 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */
158 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */
159 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */
160
161 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */
162 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */
163 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */
164 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */
165 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */
166 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */
167 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */
168 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */
169
170 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */
171 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */
172 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */
173
174 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */
175 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */
176
177 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */
178
179 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */
180 };
181
182 enum perf_branch_sample_type {
183 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT,
184 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT,
185 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT,
186
187 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT,
188 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT,
189 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT,
190 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT,
191 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT,
192 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT,
193 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT,
194 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT,
195
196 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT,
197 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT,
198 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT,
199
200 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT,
201 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT,
202
203 PERF_SAMPLE_BRANCH_TYPE_SAVE =
204 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT,
205
206 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,
207 };
208
209 /*
210 * Common flow change classification
211 */
212 enum {
213 PERF_BR_UNKNOWN = 0, /* unknown */
214 PERF_BR_COND = 1, /* conditional */
215 PERF_BR_UNCOND = 2, /* unconditional */
216 PERF_BR_IND = 3, /* indirect */
217 PERF_BR_CALL = 4, /* function call */
218 PERF_BR_IND_CALL = 5, /* indirect function call */
219 PERF_BR_RET = 6, /* function return */
220 PERF_BR_SYSCALL = 7, /* syscall */
221 PERF_BR_SYSRET = 8, /* syscall return */
222 PERF_BR_COND_CALL = 9, /* conditional function call */
223 PERF_BR_COND_RET = 10, /* conditional function return */
224 PERF_BR_MAX,
225 };
226
227 #define PERF_SAMPLE_BRANCH_PLM_ALL \
228 (PERF_SAMPLE_BRANCH_USER|\
229 PERF_SAMPLE_BRANCH_KERNEL|\
230 PERF_SAMPLE_BRANCH_HV)
231
232 /*
233 * Values to determine ABI of the registers dump.
234 */
235 enum perf_sample_regs_abi {
236 PERF_SAMPLE_REGS_ABI_NONE = 0,
237 PERF_SAMPLE_REGS_ABI_32 = 1,
238 PERF_SAMPLE_REGS_ABI_64 = 2,
239 };
240
241 /*
242 * Values for the memory transaction event qualifier, mostly for
243 * abort events. Multiple bits can be set.
244 */
245 enum {
246 PERF_TXN_ELISION = (1 << 0), /* From elision */
247 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */
248 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */
249 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */
250 PERF_TXN_RETRY = (1 << 4), /* Retry possible */
251 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */
252 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */
253 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */
254
255 PERF_TXN_MAX = (1 << 8), /* non-ABI */
256
257 /* bits 32..63 are reserved for the abort code */
258
259 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32),
260 PERF_TXN_ABORT_SHIFT = 32,
261 };
262
263 /*
264 * The format of the data returned by read() on a perf event fd,
265 * as specified by attr.read_format:
266 *
267 * struct read_format {
268 * { u64 value;
269 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
270 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
271 * { u64 id; } && PERF_FORMAT_ID
272 * } && !PERF_FORMAT_GROUP
273 *
274 * { u64 nr;
275 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED
276 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING
277 * { u64 value;
278 * { u64 id; } && PERF_FORMAT_ID
279 * } cntr[nr];
280 * } && PERF_FORMAT_GROUP
281 * };
282 */
283 enum perf_event_read_format {
284 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0,
285 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1,
286 PERF_FORMAT_ID = 1U << 2,
287 PERF_FORMAT_GROUP = 1U << 3,
288
289 PERF_FORMAT_MAX = 1U << 4, /* non-ABI */
290 };
291
292 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */
293 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */
294 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */
295 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */
296 /* add: sample_stack_user */
297 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */
298 #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */
299
300 /*
301 * Hardware event_id to monitor via a performance monitoring event:
302 *
303 * @sample_max_stack: Max number of frame pointers in a callchain,
304 * should be < /proc/sys/kernel/perf_event_max_stack
305 */
306 struct perf_event_attr {
307
308 /*
309 * Major type: hardware/software/tracepoint/etc.
310 */
311 __u32 type;
312
313 /*
314 * Size of the attr structure, for fwd/bwd compat.
315 */
316 __u32 size;
317
318 /*
319 * Type specific configuration information.
320 */
321 __u64 config;
322
323 union {
324 __u64 sample_period;
325 __u64 sample_freq;
326 };
327
328 __u64 sample_type;
329 __u64 read_format;
330
331 __u64 disabled : 1, /* off by default */
332 inherit : 1, /* children inherit it */
333 pinned : 1, /* must always be on PMU */
334 exclusive : 1, /* only group on PMU */
335 exclude_user : 1, /* don't count user */
336 exclude_kernel : 1, /* ditto kernel */
337 exclude_hv : 1, /* ditto hypervisor */
338 exclude_idle : 1, /* don't count when idle */
339 mmap : 1, /* include mmap data */
340 comm : 1, /* include comm data */
341 freq : 1, /* use freq, not period */
342 inherit_stat : 1, /* per task counts */
343 enable_on_exec : 1, /* next exec enables */
344 task : 1, /* trace fork/exit */
345 watermark : 1, /* wakeup_watermark */
346 /*
347 * precise_ip:
348 *
349 * 0 - SAMPLE_IP can have arbitrary skid
350 * 1 - SAMPLE_IP must have constant skid
351 * 2 - SAMPLE_IP requested to have 0 skid
352 * 3 - SAMPLE_IP must have 0 skid
353 *
354 * See also PERF_RECORD_MISC_EXACT_IP
355 */
356 precise_ip : 2, /* skid constraint */
357 mmap_data : 1, /* non-exec mmap data */
358 sample_id_all : 1, /* sample_type all events */
359
360 exclude_host : 1, /* don't count in host */
361 exclude_guest : 1, /* don't count in guest */
362
363 exclude_callchain_kernel : 1, /* exclude kernel callchains */
364 exclude_callchain_user : 1, /* exclude user callchains */
365 mmap2 : 1, /* include mmap with inode data */
366 comm_exec : 1, /* flag comm events that are due to an exec */
367 use_clockid : 1, /* use @clockid for time fields */
368 context_switch : 1, /* context switch data */
369 write_backward : 1, /* Write ring buffer from end to beginning */
370 namespaces : 1, /* include namespaces data */
371 __reserved_1 : 35;
372
373 union {
374 __u32 wakeup_events; /* wakeup every n events */
375 __u32 wakeup_watermark; /* bytes before wakeup */
376 };
377
378 __u32 bp_type;
379 union {
380 __u64 bp_addr;
381 __u64 config1; /* extension of config */
382 };
383 union {
384 __u64 bp_len;
385 __u64 config2; /* extension of config1 */
386 };
387 __u64 branch_sample_type; /* enum perf_branch_sample_type */
388
389 /*
390 * Defines set of user regs to dump on samples.
391 * See asm/perf_regs.h for details.
392 */
393 __u64 sample_regs_user;
394
395 /*
396 * Defines size of the user stack to dump on samples.
397 */
398 __u32 sample_stack_user;
399
400 __s32 clockid;
401 /*
402 * Defines set of regs to dump for each sample
403 * state captured on:
404 * - precise = 0: PMU interrupt
405 * - precise > 0: sampled instruction
406 *
407 * See asm/perf_regs.h for details.
408 */
409 __u64 sample_regs_intr;
410
411 /*
412 * Wakeup watermark for AUX area
413 */
414 __u32 aux_watermark;
415 __u16 sample_max_stack;
416 __u16 __reserved_2; /* align to __u64 */
417 };
418
419 #define perf_flags(attr) (*(&(attr)->read_format + 1))
420
421 /*
422 * Ioctls that can be done on a perf event fd:
423 */
424 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0)
425 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1)
426 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2)
427 #define PERF_EVENT_IOC_RESET _IO ('$', 3)
428 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64)
429 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5)
430 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *)
431 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *)
432 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32)
433 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32)
434
435 enum perf_event_ioc_flags {
436 PERF_IOC_FLAG_GROUP = 1U << 0,
437 };
438
439 /*
440 * Structure of the page that can be mapped via mmap
441 */
442 struct perf_event_mmap_page {
443 __u32 version; /* version number of this structure */
444 __u32 compat_version; /* lowest version this is compat with */
445
446 /*
447 * Bits needed to read the hw events in user-space.
448 *
449 * u32 seq, time_mult, time_shift, index, width;
450 * u64 count, enabled, running;
451 * u64 cyc, time_offset;
452 * s64 pmc = 0;
453 *
454 * do {
455 * seq = pc->lock;
456 * barrier()
457 *
458 * enabled = pc->time_enabled;
459 * running = pc->time_running;
460 *
461 * if (pc->cap_usr_time && enabled != running) {
462 * cyc = rdtsc();
463 * time_offset = pc->time_offset;
464 * time_mult = pc->time_mult;
465 * time_shift = pc->time_shift;
466 * }
467 *
468 * index = pc->index;
469 * count = pc->offset;
470 * if (pc->cap_user_rdpmc && index) {
471 * width = pc->pmc_width;
472 * pmc = rdpmc(index - 1);
473 * }
474 *
475 * barrier();
476 * } while (pc->lock != seq);
477 *
478 * NOTE: for obvious reason this only works on self-monitoring
479 * processes.
480 */
481 __u32 lock; /* seqlock for synchronization */
482 __u32 index; /* hardware event identifier */
483 __s64 offset; /* add to hardware event value */
484 __u64 time_enabled; /* time event active */
485 __u64 time_running; /* time event on cpu */
486 union {
487 __u64 capabilities;
488 struct {
489 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */
490 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */
491
492 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */
493 cap_user_time : 1, /* The time_* fields are used */
494 cap_user_time_zero : 1, /* The time_zero field is used */
495 cap_____res : 59;
496 };
497 };
498
499 /*
500 * If cap_user_rdpmc this field provides the bit-width of the value
501 * read using the rdpmc() or equivalent instruction. This can be used
502 * to sign extend the result like:
503 *
504 * pmc <<= 64 - width;
505 * pmc >>= 64 - width; // signed shift right
506 * count += pmc;
507 */
508 __u16 pmc_width;
509
510 /*
511 * If cap_usr_time the below fields can be used to compute the time
512 * delta since time_enabled (in ns) using rdtsc or similar.
513 *
514 * u64 quot, rem;
515 * u64 delta;
516 *
517 * quot = (cyc >> time_shift);
518 * rem = cyc & (((u64)1 << time_shift) - 1);
519 * delta = time_offset + quot * time_mult +
520 * ((rem * time_mult) >> time_shift);
521 *
522 * Where time_offset,time_mult,time_shift and cyc are read in the
523 * seqcount loop described above. This delta can then be added to
524 * enabled and possible running (if index), improving the scaling:
525 *
526 * enabled += delta;
527 * if (index)
528 * running += delta;
529 *
530 * quot = count / running;
531 * rem = count % running;
532 * count = quot * enabled + (rem * enabled) / running;
533 */
534 __u16 time_shift;
535 __u32 time_mult;
536 __u64 time_offset;
537 /*
538 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated
539 * from sample timestamps.
540 *
541 * time = timestamp - time_zero;
542 * quot = time / time_mult;
543 * rem = time % time_mult;
544 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult;
545 *
546 * And vice versa:
547 *
548 * quot = cyc >> time_shift;
549 * rem = cyc & (((u64)1 << time_shift) - 1);
550 * timestamp = time_zero + quot * time_mult +
551 * ((rem * time_mult) >> time_shift);
552 */
553 __u64 time_zero;
554 __u32 size; /* Header size up to __reserved[] fields. */
555
556 /*
557 * Hole for extension of the self monitor capabilities
558 */
559
560 __u8 __reserved[118*8+4]; /* align to 1k. */
561
562 /*
563 * Control data for the mmap() data buffer.
564 *
565 * User-space reading the @data_head value should issue an smp_rmb(),
566 * after reading this value.
567 *
568 * When the mapping is PROT_WRITE the @data_tail value should be
569 * written by userspace to reflect the last read data, after issueing
570 * an smp_mb() to separate the data read from the ->data_tail store.
571 * In this case the kernel will not over-write unread data.
572 *
573 * See perf_output_put_handle() for the data ordering.
574 *
575 * data_{offset,size} indicate the location and size of the perf record
576 * buffer within the mmapped area.
577 */
578 __u64 data_head; /* head in the data section */
579 __u64 data_tail; /* user-space written tail */
580 __u64 data_offset; /* where the buffer starts */
581 __u64 data_size; /* data buffer size */
582
583 /*
584 * AUX area is defined by aux_{offset,size} fields that should be set
585 * by the userspace, so that
586 *
587 * aux_offset >= data_offset + data_size
588 *
589 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size.
590 *
591 * Ring buffer pointers aux_{head,tail} have the same semantics as
592 * data_{head,tail} and same ordering rules apply.
593 */
594 __u64 aux_head;
595 __u64 aux_tail;
596 __u64 aux_offset;
597 __u64 aux_size;
598 };
599
600 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0)
601 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0)
602 #define PERF_RECORD_MISC_KERNEL (1 << 0)
603 #define PERF_RECORD_MISC_USER (2 << 0)
604 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0)
605 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0)
606 #define PERF_RECORD_MISC_GUEST_USER (5 << 0)
607
608 /*
609 * Indicates that /proc/PID/maps parsing are truncated by time out.
610 */
611 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12)
612 /*
613 * PERF_RECORD_MISC_MMAP_DATA and PERF_RECORD_MISC_COMM_EXEC are used on
614 * different events so can reuse the same bit position.
615 * Ditto PERF_RECORD_MISC_SWITCH_OUT.
616 */
617 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13)
618 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13)
619 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13)
620 /*
621 * Indicates that the content of PERF_SAMPLE_IP points to
622 * the actual instruction that triggered the event. See also
623 * perf_event_attr::precise_ip.
624 */
625 #define PERF_RECORD_MISC_EXACT_IP (1 << 14)
626 /*
627 * Reserve the last bit to indicate some extended misc field
628 */
629 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15)
630
631 struct perf_event_header {
632 __u32 type;
633 __u16 misc;
634 __u16 size;
635 };
636
637 struct perf_ns_link_info {
638 __u64 dev;
639 __u64 ino;
640 };
641
642 enum {
643 NET_NS_INDEX = 0,
644 UTS_NS_INDEX = 1,
645 IPC_NS_INDEX = 2,
646 PID_NS_INDEX = 3,
647 USER_NS_INDEX = 4,
648 MNT_NS_INDEX = 5,
649 CGROUP_NS_INDEX = 6,
650
651 NR_NAMESPACES, /* number of available namespaces */
652 };
653
654 enum perf_event_type {
655
656 /*
657 * If perf_event_attr.sample_id_all is set then all event types will
658 * have the sample_type selected fields related to where/when
659 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU,
660 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed
661 * just after the perf_event_header and the fields already present for
662 * the existing fields, i.e. at the end of the payload. That way a newer
663 * perf.data file will be supported by older perf tools, with these new
664 * optional fields being ignored.
665 *
666 * struct sample_id {
667 * { u32 pid, tid; } && PERF_SAMPLE_TID
668 * { u64 time; } && PERF_SAMPLE_TIME
669 * { u64 id; } && PERF_SAMPLE_ID
670 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
671 * { u32 cpu, res; } && PERF_SAMPLE_CPU
672 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
673 * } && perf_event_attr::sample_id_all
674 *
675 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The
676 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed
677 * relative to header.size.
678 */
679
680 /*
681 * The MMAP events record the PROT_EXEC mappings so that we can
682 * correlate userspace IPs to code. They have the following structure:
683 *
684 * struct {
685 * struct perf_event_header header;
686 *
687 * u32 pid, tid;
688 * u64 addr;
689 * u64 len;
690 * u64 pgoff;
691 * char filename[];
692 * struct sample_id sample_id;
693 * };
694 */
695 PERF_RECORD_MMAP = 1,
696
697 /*
698 * struct {
699 * struct perf_event_header header;
700 * u64 id;
701 * u64 lost;
702 * struct sample_id sample_id;
703 * };
704 */
705 PERF_RECORD_LOST = 2,
706
707 /*
708 * struct {
709 * struct perf_event_header header;
710 *
711 * u32 pid, tid;
712 * char comm[];
713 * struct sample_id sample_id;
714 * };
715 */
716 PERF_RECORD_COMM = 3,
717
718 /*
719 * struct {
720 * struct perf_event_header header;
721 * u32 pid, ppid;
722 * u32 tid, ptid;
723 * u64 time;
724 * struct sample_id sample_id;
725 * };
726 */
727 PERF_RECORD_EXIT = 4,
728
729 /*
730 * struct {
731 * struct perf_event_header header;
732 * u64 time;
733 * u64 id;
734 * u64 stream_id;
735 * struct sample_id sample_id;
736 * };
737 */
738 PERF_RECORD_THROTTLE = 5,
739 PERF_RECORD_UNTHROTTLE = 6,
740
741 /*
742 * struct {
743 * struct perf_event_header header;
744 * u32 pid, ppid;
745 * u32 tid, ptid;
746 * u64 time;
747 * struct sample_id sample_id;
748 * };
749 */
750 PERF_RECORD_FORK = 7,
751
752 /*
753 * struct {
754 * struct perf_event_header header;
755 * u32 pid, tid;
756 *
757 * struct read_format values;
758 * struct sample_id sample_id;
759 * };
760 */
761 PERF_RECORD_READ = 8,
762
763 /*
764 * struct {
765 * struct perf_event_header header;
766 *
767 * #
768 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID.
769 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position
770 * # is fixed relative to header.
771 * #
772 *
773 * { u64 id; } && PERF_SAMPLE_IDENTIFIER
774 * { u64 ip; } && PERF_SAMPLE_IP
775 * { u32 pid, tid; } && PERF_SAMPLE_TID
776 * { u64 time; } && PERF_SAMPLE_TIME
777 * { u64 addr; } && PERF_SAMPLE_ADDR
778 * { u64 id; } && PERF_SAMPLE_ID
779 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID
780 * { u32 cpu, res; } && PERF_SAMPLE_CPU
781 * { u64 period; } && PERF_SAMPLE_PERIOD
782 *
783 * { struct read_format values; } && PERF_SAMPLE_READ
784 *
785 * { u64 nr,
786 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN
787 *
788 * #
789 * # The RAW record below is opaque data wrt the ABI
790 * #
791 * # That is, the ABI doesn't make any promises wrt to
792 * # the stability of its content, it may vary depending
793 * # on event, hardware, kernel version and phase of
794 * # the moon.
795 * #
796 * # In other words, PERF_SAMPLE_RAW contents are not an ABI.
797 * #
798 *
799 * { u32 size;
800 * char data[size];}&& PERF_SAMPLE_RAW
801 *
802 * { u64 nr;
803 * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK
804 *
805 * { u64 abi; # enum perf_sample_regs_abi
806 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
807 *
808 * { u64 size;
809 * char data[size];
810 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER
811 *
812 * { u64 weight; } && PERF_SAMPLE_WEIGHT
813 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC
814 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION
815 * { u64 abi; # enum perf_sample_regs_abi
816 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR
817 * };
818 */
819 PERF_RECORD_SAMPLE = 9,
820
821 /*
822 * The MMAP2 records are an augmented version of MMAP, they add
823 * maj, min, ino numbers to be used to uniquely identify each mapping
824 *
825 * struct {
826 * struct perf_event_header header;
827 *
828 * u32 pid, tid;
829 * u64 addr;
830 * u64 len;
831 * u64 pgoff;
832 * u32 maj;
833 * u32 min;
834 * u64 ino;
835 * u64 ino_generation;
836 * u32 prot, flags;
837 * char filename[];
838 * struct sample_id sample_id;
839 * };
840 */
841 PERF_RECORD_MMAP2 = 10,
842
843 /*
844 * Records that new data landed in the AUX buffer part.
845 *
846 * struct {
847 * struct perf_event_header header;
848 *
849 * u64 aux_offset;
850 * u64 aux_size;
851 * u64 flags;
852 * struct sample_id sample_id;
853 * };
854 */
855 PERF_RECORD_AUX = 11,
856
857 /*
858 * Indicates that instruction trace has started
859 *
860 * struct {
861 * struct perf_event_header header;
862 * u32 pid;
863 * u32 tid;
864 * };
865 */
866 PERF_RECORD_ITRACE_START = 12,
867
868 /*
869 * Records the dropped/lost sample number.
870 *
871 * struct {
872 * struct perf_event_header header;
873 *
874 * u64 lost;
875 * struct sample_id sample_id;
876 * };
877 */
878 PERF_RECORD_LOST_SAMPLES = 13,
879
880 /*
881 * Records a context switch in or out (flagged by
882 * PERF_RECORD_MISC_SWITCH_OUT). See also
883 * PERF_RECORD_SWITCH_CPU_WIDE.
884 *
885 * struct {
886 * struct perf_event_header header;
887 * struct sample_id sample_id;
888 * };
889 */
890 PERF_RECORD_SWITCH = 14,
891
892 /*
893 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and
894 * next_prev_tid that are the next (switching out) or previous
895 * (switching in) pid/tid.
896 *
897 * struct {
898 * struct perf_event_header header;
899 * u32 next_prev_pid;
900 * u32 next_prev_tid;
901 * struct sample_id sample_id;
902 * };
903 */
904 PERF_RECORD_SWITCH_CPU_WIDE = 15,
905
906 /*
907 * struct {
908 * struct perf_event_header header;
909 * u32 pid;
910 * u32 tid;
911 * u64 nr_namespaces;
912 * { u64 dev, inode; } [nr_namespaces];
913 * struct sample_id sample_id;
914 * };
915 */
916 PERF_RECORD_NAMESPACES = 16,
917
918 PERF_RECORD_MAX, /* non-ABI */
919 };
920
921 #define PERF_MAX_STACK_DEPTH 127
922 #define PERF_MAX_CONTEXTS_PER_STACK 8
923
924 enum perf_callchain_context {
925 PERF_CONTEXT_HV = (__u64)-32,
926 PERF_CONTEXT_KERNEL = (__u64)-128,
927 PERF_CONTEXT_USER = (__u64)-512,
928
929 PERF_CONTEXT_GUEST = (__u64)-2048,
930 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176,
931 PERF_CONTEXT_GUEST_USER = (__u64)-2560,
932
933 PERF_CONTEXT_MAX = (__u64)-4095,
934 };
935
936 /**
937 * PERF_RECORD_AUX::flags bits
938 */
939 #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */
940 #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */
941 #define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */
942
943 #define PERF_FLAG_FD_NO_GROUP (1UL << 0)
944 #define PERF_FLAG_FD_OUTPUT (1UL << 1)
945 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */
946 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */
947
948 #if defined(__LITTLE_ENDIAN_BITFIELD)
949 union perf_mem_data_src {
950 __u64 val;
951 struct {
952 __u64 mem_op:5, /* type of opcode */
953 mem_lvl:14, /* memory hierarchy level */
954 mem_snoop:5, /* snoop mode */
955 mem_lock:2, /* lock instr */
956 mem_dtlb:7, /* tlb access */
957 mem_lvl_num:4, /* memory hierarchy level number */
958 mem_remote:1, /* remote */
959 mem_snoopx:2, /* snoop mode, ext */
960 mem_rsvd:24;
961 };
962 };
963 #elif defined(__BIG_ENDIAN_BITFIELD)
964 union perf_mem_data_src {
965 __u64 val;
966 struct {
967 __u64 mem_rsvd:24,
968 mem_snoopx:2, /* snoop mode, ext */
969 mem_remote:1, /* remote */
970 mem_lvl_num:4, /* memory hierarchy level number */
971 mem_dtlb:7, /* tlb access */
972 mem_lock:2, /* lock instr */
973 mem_snoop:5, /* snoop mode */
974 mem_lvl:14, /* memory hierarchy level */
975 mem_op:5; /* type of opcode */
976 };
977 };
978 #else
979 #error "Unknown endianness"
980 #endif
981
982 /* type of opcode (load/store/prefetch,code) */
983 #define PERF_MEM_OP_NA 0x01 /* not available */
984 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */
985 #define PERF_MEM_OP_STORE 0x04 /* store instruction */
986 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */
987 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */
988 #define PERF_MEM_OP_SHIFT 0
989
990 /* memory hierarchy (memory level, hit or miss) */
991 #define PERF_MEM_LVL_NA 0x01 /* not available */
992 #define PERF_MEM_LVL_HIT 0x02 /* hit level */
993 #define PERF_MEM_LVL_MISS 0x04 /* miss level */
994 #define PERF_MEM_LVL_L1 0x08 /* L1 */
995 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */
996 #define PERF_MEM_LVL_L2 0x20 /* L2 */
997 #define PERF_MEM_LVL_L3 0x40 /* L3 */
998 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */
999 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */
1000 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */
1001 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */
1002 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */
1003 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */
1004 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */
1005 #define PERF_MEM_LVL_SHIFT 5
1006
1007 #define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */
1008 #define PERF_MEM_REMOTE_SHIFT 37
1009
1010 #define PERF_MEM_LVLNUM_L1 0x01 /* L1 */
1011 #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */
1012 #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */
1013 #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */
1014 /* 5-0xa available */
1015 #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */
1016 #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */
1017 #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */
1018 #define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */
1019 #define PERF_MEM_LVLNUM_NA 0x0f /* N/A */
1020
1021 #define PERF_MEM_LVLNUM_SHIFT 33
1022
1023 /* snoop mode */
1024 #define PERF_MEM_SNOOP_NA 0x01 /* not available */
1025 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */
1026 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */
1027 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */
1028 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */
1029 #define PERF_MEM_SNOOP_SHIFT 19
1030
1031 #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */
1032 /* 1 free */
1033 #define PERF_MEM_SNOOPX_SHIFT 37
1034
1035 /* locked instruction */
1036 #define PERF_MEM_LOCK_NA 0x01 /* not available */
1037 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */
1038 #define PERF_MEM_LOCK_SHIFT 24
1039
1040 /* TLB access */
1041 #define PERF_MEM_TLB_NA 0x01 /* not available */
1042 #define PERF_MEM_TLB_HIT 0x02 /* hit level */
1043 #define PERF_MEM_TLB_MISS 0x04 /* miss level */
1044 #define PERF_MEM_TLB_L1 0x08 /* L1 */
1045 #define PERF_MEM_TLB_L2 0x10 /* L2 */
1046 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/
1047 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */
1048 #define PERF_MEM_TLB_SHIFT 26
1049
1050 #define PERF_MEM_S(a, s) \
1051 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)
1052
1053 /*
1054 * single taken branch record layout:
1055 *
1056 * from: source instruction (may not always be a branch insn)
1057 * to: branch target
1058 * mispred: branch target was mispredicted
1059 * predicted: branch target was predicted
1060 *
1061 * support for mispred, predicted is optional. In case it
1062 * is not supported mispred = predicted = 0.
1063 *
1064 * in_tx: running in a hardware transaction
1065 * abort: aborting a hardware transaction
1066 * cycles: cycles from last branch (or 0 if not supported)
1067 * type: branch type
1068 */
1069 struct perf_branch_entry {
1070 __u64 from;
1071 __u64 to;
1072 __u64 mispred:1, /* target mispredicted */
1073 predicted:1,/* target predicted */
1074 in_tx:1, /* in transaction */
1075 abort:1, /* transaction abort */
1076 cycles:16, /* cycle count to last branch */
1077 type:4, /* branch type */
1078 reserved:40;
1079 };
1080
1081 #endif /* _UAPI_LINUX_PERF_EVENT_H */
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