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git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blob - tools/objtool/arch/x86/lib/insn.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * x86 instruction analysis
5 * Copyright (C) IBM Corporation, 2002, 2004, 2009
9 #include <linux/string.h>
16 /* Verify next sizeof(t) bytes can be on the same instruction */
17 #define validate_next(t, insn, n) \
18 ((insn)->next_byte + sizeof(t) + n <= (insn)->end_kaddr)
20 #define __get_next(t, insn) \
21 ({ t r = *(t*)insn->next_byte; insn->next_byte += sizeof(t); r; })
23 #define __peek_nbyte_next(t, insn, n) \
24 ({ t r = *(t*)((insn)->next_byte + n); r; })
26 #define get_next(t, insn) \
27 ({ if (unlikely(!validate_next(t, insn, 0))) goto err_out; __get_next(t, insn); })
29 #define peek_nbyte_next(t, insn, n) \
30 ({ if (unlikely(!validate_next(t, insn, n))) goto err_out; __peek_nbyte_next(t, insn, n); })
32 #define peek_next(t, insn) peek_nbyte_next(t, insn, 0)
35 * insn_init() - initialize struct insn
36 * @insn: &struct insn to be initialized
37 * @kaddr: address (in kernel memory) of instruction (or copy thereof)
38 * @x86_64: !0 for 64-bit kernel or 64-bit app
40 void insn_init(struct insn
*insn
, const void *kaddr
, int buf_len
, int x86_64
)
43 * Instructions longer than MAX_INSN_SIZE (15 bytes) are invalid
44 * even if the input buffer is long enough to hold them.
46 if (buf_len
> MAX_INSN_SIZE
)
47 buf_len
= MAX_INSN_SIZE
;
49 memset(insn
, 0, sizeof(*insn
));
51 insn
->end_kaddr
= kaddr
+ buf_len
;
52 insn
->next_byte
= kaddr
;
53 insn
->x86_64
= x86_64
? 1 : 0;
62 * insn_get_prefixes - scan x86 instruction prefix bytes
63 * @insn: &struct insn containing instruction
65 * Populates the @insn->prefixes bitmap, and updates @insn->next_byte
66 * to point to the (first) opcode. No effect if @insn->prefixes.got
69 void insn_get_prefixes(struct insn
*insn
)
71 struct insn_field
*prefixes
= &insn
->prefixes
;
81 b
= peek_next(insn_byte_t
, insn
);
82 attr
= inat_get_opcode_attribute(b
);
83 while (inat_is_legacy_prefix(attr
)) {
84 /* Skip if same prefix */
85 for (i
= 0; i
< nb
; i
++)
86 if (prefixes
->bytes
[i
] == b
)
89 /* Invalid instruction */
91 prefixes
->bytes
[nb
++] = b
;
92 if (inat_is_address_size_prefix(attr
)) {
93 /* address size switches 2/4 or 4/8 */
95 insn
->addr_bytes
^= 12;
97 insn
->addr_bytes
^= 6;
98 } else if (inat_is_operand_size_prefix(attr
)) {
99 /* oprand size switches 2/4 */
100 insn
->opnd_bytes
^= 6;
106 b
= peek_next(insn_byte_t
, insn
);
107 attr
= inat_get_opcode_attribute(b
);
109 /* Set the last prefix */
110 if (lb
&& lb
!= insn
->prefixes
.bytes
[3]) {
111 if (unlikely(insn
->prefixes
.bytes
[3])) {
112 /* Swap the last prefix */
113 b
= insn
->prefixes
.bytes
[3];
114 for (i
= 0; i
< nb
; i
++)
115 if (prefixes
->bytes
[i
] == lb
)
116 prefixes
->bytes
[i
] = b
;
118 insn
->prefixes
.bytes
[3] = lb
;
121 /* Decode REX prefix */
123 b
= peek_next(insn_byte_t
, insn
);
124 attr
= inat_get_opcode_attribute(b
);
125 if (inat_is_rex_prefix(attr
)) {
126 insn
->rex_prefix
.value
= b
;
127 insn
->rex_prefix
.nbytes
= 1;
130 /* REX.W overrides opnd_size */
131 insn
->opnd_bytes
= 8;
134 insn
->rex_prefix
.got
= 1;
136 /* Decode VEX prefix */
137 b
= peek_next(insn_byte_t
, insn
);
138 attr
= inat_get_opcode_attribute(b
);
139 if (inat_is_vex_prefix(attr
)) {
140 insn_byte_t b2
= peek_nbyte_next(insn_byte_t
, insn
, 1);
143 * In 32-bits mode, if the [7:6] bits (mod bits of
144 * ModRM) on the second byte are not 11b, it is
145 * LDS or LES or BOUND.
147 if (X86_MODRM_MOD(b2
) != 3)
150 insn
->vex_prefix
.bytes
[0] = b
;
151 insn
->vex_prefix
.bytes
[1] = b2
;
152 if (inat_is_evex_prefix(attr
)) {
153 b2
= peek_nbyte_next(insn_byte_t
, insn
, 2);
154 insn
->vex_prefix
.bytes
[2] = b2
;
155 b2
= peek_nbyte_next(insn_byte_t
, insn
, 3);
156 insn
->vex_prefix
.bytes
[3] = b2
;
157 insn
->vex_prefix
.nbytes
= 4;
158 insn
->next_byte
+= 4;
159 if (insn
->x86_64
&& X86_VEX_W(b2
))
160 /* VEX.W overrides opnd_size */
161 insn
->opnd_bytes
= 8;
162 } else if (inat_is_vex3_prefix(attr
)) {
163 b2
= peek_nbyte_next(insn_byte_t
, insn
, 2);
164 insn
->vex_prefix
.bytes
[2] = b2
;
165 insn
->vex_prefix
.nbytes
= 3;
166 insn
->next_byte
+= 3;
167 if (insn
->x86_64
&& X86_VEX_W(b2
))
168 /* VEX.W overrides opnd_size */
169 insn
->opnd_bytes
= 8;
172 * For VEX2, fake VEX3-like byte#2.
173 * Makes it easier to decode vex.W, vex.vvvv,
174 * vex.L and vex.pp. Masking with 0x7f sets vex.W == 0.
176 insn
->vex_prefix
.bytes
[2] = b2
& 0x7f;
177 insn
->vex_prefix
.nbytes
= 2;
178 insn
->next_byte
+= 2;
182 insn
->vex_prefix
.got
= 1;
191 * insn_get_opcode - collect opcode(s)
192 * @insn: &struct insn containing instruction
194 * Populates @insn->opcode, updates @insn->next_byte to point past the
195 * opcode byte(s), and set @insn->attr (except for groups).
196 * If necessary, first collects any preceding (prefix) bytes.
197 * Sets @insn->opcode.value = opcode1. No effect if @insn->opcode.got
200 void insn_get_opcode(struct insn
*insn
)
202 struct insn_field
*opcode
= &insn
->opcode
;
207 if (!insn
->prefixes
.got
)
208 insn_get_prefixes(insn
);
210 /* Get first opcode */
211 op
= get_next(insn_byte_t
, insn
);
212 opcode
->bytes
[0] = op
;
215 /* Check if there is VEX prefix or not */
216 if (insn_is_avx(insn
)) {
218 m
= insn_vex_m_bits(insn
);
219 p
= insn_vex_p_bits(insn
);
220 insn
->attr
= inat_get_avx_attribute(op
, m
, p
);
221 if ((inat_must_evex(insn
->attr
) && !insn_is_evex(insn
)) ||
222 (!inat_accept_vex(insn
->attr
) &&
223 !inat_is_group(insn
->attr
)))
224 insn
->attr
= 0; /* This instruction is bad */
225 goto end
; /* VEX has only 1 byte for opcode */
228 insn
->attr
= inat_get_opcode_attribute(op
);
229 while (inat_is_escape(insn
->attr
)) {
230 /* Get escaped opcode */
231 op
= get_next(insn_byte_t
, insn
);
232 opcode
->bytes
[opcode
->nbytes
++] = op
;
233 pfx_id
= insn_last_prefix_id(insn
);
234 insn
->attr
= inat_get_escape_attribute(op
, pfx_id
, insn
->attr
);
236 if (inat_must_vex(insn
->attr
))
237 insn
->attr
= 0; /* This instruction is bad */
246 * insn_get_modrm - collect ModRM byte, if any
247 * @insn: &struct insn containing instruction
249 * Populates @insn->modrm and updates @insn->next_byte to point past the
250 * ModRM byte, if any. If necessary, first collects the preceding bytes
251 * (prefixes and opcode(s)). No effect if @insn->modrm.got is already 1.
253 void insn_get_modrm(struct insn
*insn
)
255 struct insn_field
*modrm
= &insn
->modrm
;
256 insn_byte_t pfx_id
, mod
;
259 if (!insn
->opcode
.got
)
260 insn_get_opcode(insn
);
262 if (inat_has_modrm(insn
->attr
)) {
263 mod
= get_next(insn_byte_t
, insn
);
266 if (inat_is_group(insn
->attr
)) {
267 pfx_id
= insn_last_prefix_id(insn
);
268 insn
->attr
= inat_get_group_attribute(mod
, pfx_id
,
270 if (insn_is_avx(insn
) && !inat_accept_vex(insn
->attr
))
271 insn
->attr
= 0; /* This is bad */
275 if (insn
->x86_64
&& inat_is_force64(insn
->attr
))
276 insn
->opnd_bytes
= 8;
285 * insn_rip_relative() - Does instruction use RIP-relative addressing mode?
286 * @insn: &struct insn containing instruction
288 * If necessary, first collects the instruction up to and including the
289 * ModRM byte. No effect if @insn->x86_64 is 0.
291 int insn_rip_relative(struct insn
*insn
)
293 struct insn_field
*modrm
= &insn
->modrm
;
298 insn_get_modrm(insn
);
300 * For rip-relative instructions, the mod field (top 2 bits)
301 * is zero and the r/m field (bottom 3 bits) is 0x5.
303 return (modrm
->nbytes
&& (modrm
->value
& 0xc7) == 0x5);
307 * insn_get_sib() - Get the SIB byte of instruction
308 * @insn: &struct insn containing instruction
310 * If necessary, first collects the instruction up to and including the
313 void insn_get_sib(struct insn
*insn
)
319 if (!insn
->modrm
.got
)
320 insn_get_modrm(insn
);
321 if (insn
->modrm
.nbytes
) {
322 modrm
= (insn_byte_t
)insn
->modrm
.value
;
323 if (insn
->addr_bytes
!= 2 &&
324 X86_MODRM_MOD(modrm
) != 3 && X86_MODRM_RM(modrm
) == 4) {
325 insn
->sib
.value
= get_next(insn_byte_t
, insn
);
326 insn
->sib
.nbytes
= 1;
337 * insn_get_displacement() - Get the displacement of instruction
338 * @insn: &struct insn containing instruction
340 * If necessary, first collects the instruction up to and including the
342 * Displacement value is sign-expanded.
344 void insn_get_displacement(struct insn
*insn
)
346 insn_byte_t mod
, rm
, base
;
348 if (insn
->displacement
.got
)
352 if (insn
->modrm
.nbytes
) {
354 * Interpreting the modrm byte:
355 * mod = 00 - no displacement fields (exceptions below)
356 * mod = 01 - 1-byte displacement field
357 * mod = 10 - displacement field is 4 bytes, or 2 bytes if
358 * address size = 2 (0x67 prefix in 32-bit mode)
359 * mod = 11 - no memory operand
361 * If address size = 2...
362 * mod = 00, r/m = 110 - displacement field is 2 bytes
364 * If address size != 2...
365 * mod != 11, r/m = 100 - SIB byte exists
366 * mod = 00, SIB base = 101 - displacement field is 4 bytes
367 * mod = 00, r/m = 101 - rip-relative addressing, displacement
370 mod
= X86_MODRM_MOD(insn
->modrm
.value
);
371 rm
= X86_MODRM_RM(insn
->modrm
.value
);
372 base
= X86_SIB_BASE(insn
->sib
.value
);
376 insn
->displacement
.value
= get_next(signed char, insn
);
377 insn
->displacement
.nbytes
= 1;
378 } else if (insn
->addr_bytes
== 2) {
379 if ((mod
== 0 && rm
== 6) || mod
== 2) {
380 insn
->displacement
.value
=
381 get_next(short, insn
);
382 insn
->displacement
.nbytes
= 2;
385 if ((mod
== 0 && rm
== 5) || mod
== 2 ||
386 (mod
== 0 && base
== 5)) {
387 insn
->displacement
.value
= get_next(int, insn
);
388 insn
->displacement
.nbytes
= 4;
393 insn
->displacement
.got
= 1;
399 /* Decode moffset16/32/64. Return 0 if failed */
400 static int __get_moffset(struct insn
*insn
)
402 switch (insn
->addr_bytes
) {
404 insn
->moffset1
.value
= get_next(short, insn
);
405 insn
->moffset1
.nbytes
= 2;
408 insn
->moffset1
.value
= get_next(int, insn
);
409 insn
->moffset1
.nbytes
= 4;
412 insn
->moffset1
.value
= get_next(int, insn
);
413 insn
->moffset1
.nbytes
= 4;
414 insn
->moffset2
.value
= get_next(int, insn
);
415 insn
->moffset2
.nbytes
= 4;
417 default: /* opnd_bytes must be modified manually */
420 insn
->moffset1
.got
= insn
->moffset2
.got
= 1;
428 /* Decode imm v32(Iz). Return 0 if failed */
429 static int __get_immv32(struct insn
*insn
)
431 switch (insn
->opnd_bytes
) {
433 insn
->immediate
.value
= get_next(short, insn
);
434 insn
->immediate
.nbytes
= 2;
438 insn
->immediate
.value
= get_next(int, insn
);
439 insn
->immediate
.nbytes
= 4;
441 default: /* opnd_bytes must be modified manually */
451 /* Decode imm v64(Iv/Ov), Return 0 if failed */
452 static int __get_immv(struct insn
*insn
)
454 switch (insn
->opnd_bytes
) {
456 insn
->immediate1
.value
= get_next(short, insn
);
457 insn
->immediate1
.nbytes
= 2;
460 insn
->immediate1
.value
= get_next(int, insn
);
461 insn
->immediate1
.nbytes
= 4;
464 insn
->immediate1
.value
= get_next(int, insn
);
465 insn
->immediate1
.nbytes
= 4;
466 insn
->immediate2
.value
= get_next(int, insn
);
467 insn
->immediate2
.nbytes
= 4;
469 default: /* opnd_bytes must be modified manually */
472 insn
->immediate1
.got
= insn
->immediate2
.got
= 1;
479 /* Decode ptr16:16/32(Ap) */
480 static int __get_immptr(struct insn
*insn
)
482 switch (insn
->opnd_bytes
) {
484 insn
->immediate1
.value
= get_next(short, insn
);
485 insn
->immediate1
.nbytes
= 2;
488 insn
->immediate1
.value
= get_next(int, insn
);
489 insn
->immediate1
.nbytes
= 4;
492 /* ptr16:64 is not exist (no segment) */
494 default: /* opnd_bytes must be modified manually */
497 insn
->immediate2
.value
= get_next(unsigned short, insn
);
498 insn
->immediate2
.nbytes
= 2;
499 insn
->immediate1
.got
= insn
->immediate2
.got
= 1;
507 * insn_get_immediate() - Get the immediates of instruction
508 * @insn: &struct insn containing instruction
510 * If necessary, first collects the instruction up to and including the
511 * displacement bytes.
512 * Basically, most of immediates are sign-expanded. Unsigned-value can be
513 * get by bit masking with ((1 << (nbytes * 8)) - 1)
515 void insn_get_immediate(struct insn
*insn
)
517 if (insn
->immediate
.got
)
519 if (!insn
->displacement
.got
)
520 insn_get_displacement(insn
);
522 if (inat_has_moffset(insn
->attr
)) {
523 if (!__get_moffset(insn
))
528 if (!inat_has_immediate(insn
->attr
))
532 switch (inat_immediate_size(insn
->attr
)) {
534 insn
->immediate
.value
= get_next(signed char, insn
);
535 insn
->immediate
.nbytes
= 1;
538 insn
->immediate
.value
= get_next(short, insn
);
539 insn
->immediate
.nbytes
= 2;
542 insn
->immediate
.value
= get_next(int, insn
);
543 insn
->immediate
.nbytes
= 4;
546 insn
->immediate1
.value
= get_next(int, insn
);
547 insn
->immediate1
.nbytes
= 4;
548 insn
->immediate2
.value
= get_next(int, insn
);
549 insn
->immediate2
.nbytes
= 4;
552 if (!__get_immptr(insn
))
555 case INAT_IMM_VWORD32
:
556 if (!__get_immv32(insn
))
560 if (!__get_immv(insn
))
564 /* Here, insn must have an immediate, but failed */
567 if (inat_has_second_immediate(insn
->attr
)) {
568 insn
->immediate2
.value
= get_next(signed char, insn
);
569 insn
->immediate2
.nbytes
= 1;
572 insn
->immediate
.got
= 1;
579 * insn_get_length() - Get the length of instruction
580 * @insn: &struct insn containing instruction
582 * If necessary, first collects the instruction up to and including the
585 void insn_get_length(struct insn
*insn
)
589 if (!insn
->immediate
.got
)
590 insn_get_immediate(insn
);
591 insn
->length
= (unsigned char)((unsigned long)insn
->next_byte
592 - (unsigned long)insn
->kaddr
);