tools/perf/Documentation/perf-list.txt

   1 perf-list(1)
   2 ============
   3
   4 NAME
   5 ----
   6 perf-list - List all symbolic event types
   7
   8 SYNOPSIS
   9 --------
  10 [verse]
  11 'perf list' [hw|sw|cache|tracepoint|pmu|event_glob]
  12
  13 DESCRIPTION
  14 -----------
  15 This command displays the symbolic event types which can be selected in the
  16 various perf commands with the -e option.
  17
  18 [[EVENT_MODIFIERS]]
  19 EVENT MODIFIERS
  20 ---------------
  21
  22 Events can optionally have a modifier by appending a colon and one or
  23 more modifiers. Modifiers allow the user to restrict the events to be
  24 counted. The following modifiers exist:
  25
  26  u - user-space counting
  27  k - kernel counting
  28  h - hypervisor counting
  29  I - non idle counting
  30  G - guest counting (in KVM guests)
  31  H - host counting (not in KVM guests)
  32  p - precise level
  33  P - use maximum detected precise level
  34  S - read sample value (PERF_SAMPLE_READ)
  35  D - pin the event to the PMU
  36
  37 The 'p' modifier can be used for specifying how precise the instruction
  38 address should be. The 'p' modifier can be specified multiple times:
  39
  40  0 - SAMPLE_IP can have arbitrary skid
  41  1 - SAMPLE_IP must have constant skid
  42  2 - SAMPLE_IP requested to have 0 skid
  43  3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
  44      sample shadowing effects.
  45
  46 For Intel systems precise event sampling is implemented with PEBS
  47 which supports up to precise-level 2, and precise level 3 for
  48 some special cases
  49
  50 On AMD systems it is implemented using IBS (up to precise-level 2).
  51 The precise modifier works with event types 0x76 (cpu-cycles, CPU
  52 clocks not halted) and 0xC1 (micro-ops retired). Both events map to
  53 IBS execution sampling (IBS op) with the IBS Op Counter Control bit
  54 (IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
  55 Manual Volume 2: System Programming, 13.3 Instruction-Based
  56 Sampling). Examples to use IBS:
  57
  58  perf record -a -e cpu-cycles:p ...    # use ibs op counting cycles
  59  perf record -a -e r076:p ...          # same as -e cpu-cycles:p
  60  perf record -a -e r0C1:p ...          # use ibs op counting micro-ops
  61
  62 RAW HARDWARE EVENT DESCRIPTOR
  63 -----------------------------
  64 Even when an event is not available in a symbolic form within perf right now,
  65 it can be encoded in a per processor specific way.
  66
  67 For instance For x86 CPUs NNN represents the raw register encoding with the
  68 layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
  69 of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
  70 Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
  71
  72 Note: Only the following bit fields can be set in x86 counter
  73 registers: event, umask, edge, inv, cmask. Esp. guest/host only and
  74 OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
  75 MODIFIERS>>.
  76
  77 Example:
  78
  79 If the Intel docs for a QM720 Core i7 describe an event as:
  80
  81   Event  Umask  Event Mask
  82   Num.   Value  Mnemonic    Description                        Comment
  83
  84   A8H      01H  LSD.UOPS    Counts the number of micro-ops     Use cmask=1 and
  85                             delivered by loop stream detector  invert to count
  86                                                                cycles
  87
  88 raw encoding of 0x1A8 can be used:
  89
  90  perf stat -e r1a8 -a sleep 1
  91  perf record -e r1a8 ...
  92
  93 You should refer to the processor specific documentation for getting these
  94 details. Some of them are referenced in the SEE ALSO section below.
  95
  96 ARBITRARY PMUS
  97 --------------
  98
  99 perf also supports an extended syntax for specifying raw parameters
 100 to PMUs. Using this typically requires looking up the specific event
 101 in the CPU vendor specific documentation.
 102
 103 The available PMUs and their raw parameters can be listed with
 104
 105   ls /sys/devices/*/format
 106
 107 For example the raw event "LSD.UOPS" core pmu event above could
 108 be specified as
 109
 110   perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=1/ ...
 111
 112 PER SOCKET PMUS
 113 ---------------
 114
 115 Some PMUs are not associated with a core, but with a whole CPU socket.
 116 Events on these PMUs generally cannot be sampled, but only counted globally
 117 with perf stat -a. They can be bound to one logical CPU, but will measure
 118 all the CPUs in the same socket.
 119
 120 This example measures memory bandwidth every second
 121 on the first memory controller on socket 0 of a Intel Xeon system
 122
 123   perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
 124
 125 Each memory controller has its own PMU.  Measuring the complete system
 126 bandwidth would require specifying all imc PMUs (see perf list output),
 127 and adding the values together.
 128
 129 This example measures the combined core power every second
 130
 131   perf stat -I 1000 -e power/energy-cores/  -a
 132
 133 ACCESS RESTRICTIONS
 134 -------------------
 135
 136 For non root users generally only context switched PMU events are available.
 137 This is normally only the events in the cpu PMU, the predefined events
 138 like cycles and instructions and some software events.
 139
 140 Other PMUs and global measurements are normally root only.
 141 Some event qualifiers, such as "any", are also root only.
 142
 143 This can be overriden by setting the kernel.perf_event_paranoid
 144 sysctl to -1, which allows non root to use these events.
 145
 146 For accessing trace point events perf needs to have read access to
 147 /sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed
 148 setting.
 149
 150 TRACING
 151 -------
 152
 153 Some PMUs control advanced hardware tracing capabilities, such as Intel PT,
 154 that allows low overhead execution tracing.  These are described in a separate
 155 intel-pt.txt document.
 156
 157 PARAMETERIZED EVENTS
 158 --------------------
 159
 160 Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
 161 example:
 162
 163   hv_gpci/dtbp_ptitc,phys_processor_idx=?/
 164
 165 This means that when provided as an event, a value for '?' must
 166 also be supplied. For example:
 167
 168   perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
 169
 170 EVENT GROUPS
 171 ------------
 172
 173 Perf supports time based multiplexing of events, when the number of events
 174 active exceeds the number of hardware performance counters. Multiplexing
 175 can cause measurement errors when the workload changes its execution
 176 profile.
 177
 178 When metrics are computed using formulas from event counts, it is useful to
 179 ensure some events are always measured together as a group to minimize multiplexing
 180 errors. Event groups can be specified using { }.
 181
 182   perf stat -e '{instructions,cycles}' ...
 183
 184 The number of available performance counters depend on the CPU. A group
 185 cannot contain more events than available counters.
 186 For example Intel Core CPUs typically have four generic performance counters
 187 for the core, plus three fixed counters for instructions, cycles and
 188 ref-cycles. Some special events have restrictions on which counter they
 189 can schedule, and may not support multiple instances in a single group.
 190 When too many events are specified in the group none of them will not
 191 be measured.
 192
 193 Globally pinned events can limit the number of counters available for
 194 other groups. On x86 systems, the NMI watchdog pins a counter by default.
 195 The nmi watchdog can be disabled as root with
 196
 197         echo 0 > /proc/sys/kernel/nmi_watchdog
 198
 199 Events from multiple different PMUs cannot be mixed in a group, with
 200 some exceptions for software events.
 201
 202 LEADER SAMPLING
 203 ---------------
 204
 205 perf also supports group leader sampling using the :S specifier.
 206
 207   perf record -e '{cycles,instructions}:S' ...
 208   perf report --group
 209
 210 Normally all events in a event group sample, but with :S only
 211 the first event (the leader) samples, and it only reads the values of the
 212 other events in the group.
 213
 214 OPTIONS
 215 -------
 216
 217 Without options all known events will be listed.
 218
 219 To limit the list use:
 220
 221 . 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
 222
 223 . 'sw' or 'software' to list software events such as context switches, etc.
 224
 225 . 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
 226
 227 . 'tracepoint' to list all tracepoint events, alternatively use
 228   'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
 229   block, etc.
 230
 231 . 'pmu' to print the kernel supplied PMU events.
 232
 233 . If none of the above is matched, it will apply the supplied glob to all
 234   events, printing the ones that match.
 235
 236 . As a last resort, it will do a substring search in all event names.
 237
 238 One or more types can be used at the same time, listing the events for the
 239 types specified.
 240
 241 Support raw format:
 242
 243 . '--raw-dump', shows the raw-dump of all the events.
 244 . '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
 245   a certain kind of events.
 246
 247 SEE ALSO
 248 --------
 249 linkperf:perf-stat[1], linkperf:perf-top[1],
 250 linkperf:perf-record[1],
 251 http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
 252 http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]