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1 #ifndef _PERF_SYS_H
2 #define _PERF_SYS_H
3
4 #include <unistd.h>
5 #include <sys/types.h>
6 #include <sys/syscall.h>
7 #include <linux/types.h>
8 #include <linux/perf_event.h>
9 #include <asm/barrier.h>
10
11 #if defined(__i386__)
12 #define cpu_relax() asm volatile("rep; nop" ::: "memory");
13 #define CPUINFO_PROC {"model name"}
14 #ifndef __NR_perf_event_open
15 # define __NR_perf_event_open 336
16 #endif
17 #ifndef __NR_futex
18 # define __NR_futex 240
19 #endif
20 #ifndef __NR_gettid
21 # define __NR_gettid 224
22 #endif
23 #endif
24
25 #if defined(__x86_64__)
26 #define cpu_relax() asm volatile("rep; nop" ::: "memory");
27 #define CPUINFO_PROC {"model name"}
28 #ifndef __NR_perf_event_open
29 # define __NR_perf_event_open 298
30 #endif
31 #ifndef __NR_futex
32 # define __NR_futex 202
33 #endif
34 #ifndef __NR_gettid
35 # define __NR_gettid 186
36 #endif
37 #endif
38
39 #ifdef __powerpc__
40 #include "../../arch/powerpc/include/uapi/asm/unistd.h"
41 #define CPUINFO_PROC {"cpu"}
42 #endif
43
44 #ifdef __s390__
45 #define CPUINFO_PROC {"vendor_id"}
46 #endif
47
48 #ifdef __sh__
49 #if defined(__SH4A__) || defined(__SH5__)
50 # define mb() asm volatile("synco" ::: "memory")
51 # define wmb() asm volatile("synco" ::: "memory")
52 # define rmb() asm volatile("synco" ::: "memory")
53 #else
54 # define mb() asm volatile("" ::: "memory")
55 # define wmb() asm volatile("" ::: "memory")
56 # define rmb() asm volatile("" ::: "memory")
57 #endif
58 #define CPUINFO_PROC {"cpu type"}
59 #endif
60
61 #ifdef __hppa__
62 #define mb() asm volatile("" ::: "memory")
63 #define wmb() asm volatile("" ::: "memory")
64 #define rmb() asm volatile("" ::: "memory")
65 #define CPUINFO_PROC {"cpu"}
66 #endif
67
68 #ifdef __sparc__
69 #ifdef __LP64__
70 #define mb() asm volatile("ba,pt %%xcc, 1f\n" \
71 "membar #StoreLoad\n" \
72 "1:\n":::"memory")
73 #else
74 #define mb() asm volatile("":::"memory")
75 #endif
76 #define wmb() asm volatile("":::"memory")
77 #define rmb() asm volatile("":::"memory")
78 #define CPUINFO_PROC {"cpu"}
79 #endif
80
81 #ifdef __alpha__
82 #define mb() asm volatile("mb" ::: "memory")
83 #define wmb() asm volatile("wmb" ::: "memory")
84 #define rmb() asm volatile("mb" ::: "memory")
85 #define CPUINFO_PROC {"cpu model"}
86 #endif
87
88 #ifdef __ia64__
89 #define mb() asm volatile ("mf" ::: "memory")
90 #define wmb() asm volatile ("mf" ::: "memory")
91 #define rmb() asm volatile ("mf" ::: "memory")
92 #define cpu_relax() asm volatile ("hint @pause" ::: "memory")
93 #define CPUINFO_PROC {"model name"}
94 #endif
95
96 #ifdef __arm__
97 /*
98 * Use the __kuser_memory_barrier helper in the CPU helper page. See
99 * arch/arm/kernel/entry-armv.S in the kernel source for details.
100 */
101 #define mb() ((void(*)(void))0xffff0fa0)()
102 #define wmb() ((void(*)(void))0xffff0fa0)()
103 #define rmb() ((void(*)(void))0xffff0fa0)()
104 #define CPUINFO_PROC {"model name", "Processor"}
105 #endif
106
107 #ifdef __aarch64__
108 #define mb() asm volatile("dmb ish" ::: "memory")
109 #define wmb() asm volatile("dmb ishst" ::: "memory")
110 #define rmb() asm volatile("dmb ishld" ::: "memory")
111 #define cpu_relax() asm volatile("yield" ::: "memory")
112 #endif
113
114 #ifdef __mips__
115 #define mb() asm volatile( \
116 ".set mips2\n\t" \
117 "sync\n\t" \
118 ".set mips0" \
119 : /* no output */ \
120 : /* no input */ \
121 : "memory")
122 #define wmb() mb()
123 #define rmb() mb()
124 #define CPUINFO_PROC {"cpu model"}
125 #endif
126
127 #ifdef __arc__
128 #define mb() asm volatile("" ::: "memory")
129 #define wmb() asm volatile("" ::: "memory")
130 #define rmb() asm volatile("" ::: "memory")
131 #define CPUINFO_PROC {"Processor"}
132 #endif
133
134 #ifdef __metag__
135 #define mb() asm volatile("" ::: "memory")
136 #define wmb() asm volatile("" ::: "memory")
137 #define rmb() asm volatile("" ::: "memory")
138 #define CPUINFO_PROC {"CPU"}
139 #endif
140
141 #ifdef __xtensa__
142 #define mb() asm volatile("memw" ::: "memory")
143 #define wmb() asm volatile("memw" ::: "memory")
144 #define rmb() asm volatile("" ::: "memory")
145 #define CPUINFO_PROC {"core ID"}
146 #endif
147
148 #ifdef __tile__
149 #define mb() asm volatile ("mf" ::: "memory")
150 #define wmb() asm volatile ("mf" ::: "memory")
151 #define rmb() asm volatile ("mf" ::: "memory")
152 #define cpu_relax() asm volatile ("mfspr zero, PASS" ::: "memory")
153 #define CPUINFO_PROC {"model name"}
154 #endif
155
156 #define barrier() asm volatile ("" ::: "memory")
157
158 #ifndef cpu_relax
159 #define cpu_relax() barrier()
160 #endif
161
162 static inline int
163 sys_perf_event_open(struct perf_event_attr *attr,
164 pid_t pid, int cpu, int group_fd,
165 unsigned long flags)
166 {
167 int fd;
168
169 fd = syscall(__NR_perf_event_open, attr, pid, cpu,
170 group_fd, flags);
171
172 #ifdef HAVE_ATTR_TEST
173 if (unlikely(test_attr__enabled))
174 test_attr__open(attr, pid, cpu, fd, group_fd, flags);
175 #endif
176 return fd;
177 }
178
179 #endif /* _PERF_SYS_H */