tools/perf/pmu-events/arch/powerpc/power9/pmc.json

   1 [
   2   {,
   3     "EventCode": "0x0",
   4     "EventName": "PM_SUSPENDED",
   5     "BriefDescription": "Counter OFF",
   6     "PublicDescription": ""
   7   },
   8   {,
   9     "EventCode": "0x10026",
  10     "EventName": "PM_TABLEWALK_CYC",
  11     "BriefDescription": "Cycles when an instruction tablewalk is active",
  12     "PublicDescription": ""
  13   },
  14   {,
  15     "EventCode": "0x1E04C",
  16     "EventName": "PM_DPTEG_FROM_LL4",
  17     "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
  18     "PublicDescription": ""
  19   },
  20   {,
  21     "EventCode": "0x1F14E",
  22     "EventName": "PM_MRK_DPTEG_FROM_L2MISS",
  23     "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
  24     "PublicDescription": ""
  25   },
  26   {,
  27     "EventCode": "0x10060",
  28     "EventName": "PM_TM_TRANS_RUN_CYC",
  29     "BriefDescription": "run cycles in transactional state",
  30     "PublicDescription": ""
  31   },
  32   {,
  33     "EventCode": "0x2C012",
  34     "EventName": "PM_CMPLU_STALL_DCACHE_MISS",
  35     "BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest",
  36     "PublicDescription": ""
  37   },
  38   {,
  39     "EventCode": "0x2E04C",
  40     "EventName": "PM_DPTEG_FROM_MEMORY",
  41     "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
  42     "PublicDescription": ""
  43   },
  44   {,
  45     "EventCode": "0x2C056",
  46     "EventName": "PM_DTLB_MISS_4K",
  47     "BriefDescription": "Data TLB Miss page size 4k",
  48     "PublicDescription": ""
  49   },
  50   {,
  51     "EventCode": "0x3000C",
  52     "EventName": "PM_FREQ_DOWN",
  53     "BriefDescription": "Power Management: Below Threshold B",
  54     "PublicDescription": ""
  55   },
  56   {,
  57     "EventCode": "0x3D142",
  58     "EventName": "PM_MRK_DATA_FROM_LMEM",
  59     "BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load",
  60     "PublicDescription": ""
  61   },
  62   {,
  63     "EventCode": "0x3F142",
  64     "EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
  65     "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
  66     "PublicDescription": ""
  67   },
  68   {,
  69     "EventCode": "0x301E8",
  70     "EventName": "PM_THRESH_EXC_64",
  71     "BriefDescription": "Threshold counter exceeded a value of 64",
  72     "PublicDescription": ""
  73   },
  74   {,
  75     "EventCode": "0x40118",
  76     "EventName": "PM_MRK_DCACHE_RELOAD_INTV",
  77     "BriefDescription": "Combined Intervention event",
  78     "PublicDescription": ""
  79   },
  80   {,
  81     "EventCode": "0x4C01E",
  82     "EventName": "PM_CMPLU_STALL_CRYPTO",
  83     "BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish",
  84     "PublicDescription": ""
  85   },
  86   {,
  87     "EventCode": "0x4D018",
  88     "EventName": "PM_CMPLU_STALL_BRU",
  89     "BriefDescription": "Completion stall due to a Branch Unit",
  90     "PublicDescription": ""
  91   },
  92   {,
  93     "EventCode": "0x4D128",
  94     "EventName": "PM_MRK_DATA_FROM_LMEM_CYC",
  95     "BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load",
  96     "PublicDescription": ""
  97   },
  98   {,
  99     "EventCode": "0x4E04E",
 100     "EventName": "PM_DPTEG_FROM_L3MISS",
 101     "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
 102     "PublicDescription": ""
 103   },
 104   {,
 105     "EventCode": "0x4F142",
 106     "EventName": "PM_MRK_DPTEG_FROM_L3",
 107     "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
 108     "PublicDescription": ""
 109   },
 110   {,
 111     "EventCode": "0x4F148",
 112     "EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
 113     "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
 114     "PublicDescription": ""
 115   },
 116   {,
 117     "EventCode": "0x40050",
 118     "EventName": "PM_SYS_PUMP_MPRED_RTY",
 119     "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
 120     "PublicDescription": ""
 121   },
 122   {,
 123     "EventCode": "0x40056",
 124     "EventName": "PM_MEM_LOC_THRESH_LSU_HIGH",
 125     "BriefDescription": "Local memory above threshold for LSU medium",
 126     "PublicDescription": ""
 127   },
 128   {,
 129     "EventCode": "0x4D054",
 130     "EventName": "PM_8FLOP_CMPL",
 131     "BriefDescription": "8 FLOP instruction completed",
 132     "PublicDescription": ""
 133   },
 134   {,
 135     "EventCode": "0x45050",
 136     "EventName": "PM_1FLOP_CMPL",
 137     "BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed",
 138     "PublicDescription": ""
 139   },
 140   {,
 141     "EventCode": "0x45052",
 142     "EventName": "PM_4FLOP_CMPL",
 143     "BriefDescription": "4 FLOP instruction completed",
 144     "PublicDescription": ""
 145   }
 146 ]