tools/perf/pmu-events/arch/powerpc/power9/pmc.json

   1 [
   2   {,
   3     "EventCode": "0x20036",
   4     "EventName": "PM_BR_2PATH",
   5     "BriefDescription": "Branches that are not strongly biased"
   6   },
   7   {,
   8     "EventCode": "0x40036",
   9     "EventName": "PM_BR_2PATH",
  10     "BriefDescription": "Branches that are not strongly biased"
  11   },
  12   {,
  13     "EventCode": "0x40056",
  14     "EventName": "PM_MEM_LOC_THRESH_LSU_HIGH",
  15     "BriefDescription": "Local memory above threshold for LSU medium"
  16   },
  17   {,
  18     "EventCode": "0x2C056",
  19     "EventName": "PM_DTLB_MISS_4K",
  20     "BriefDescription": "Data TLB Miss page size 4k"
  21   },
  22   {,
  23     "EventCode": "0x40118",
  24     "EventName": "PM_MRK_DCACHE_RELOAD_INTV",
  25     "BriefDescription": "Combined Intervention event"
  26   },
  27   {,
  28     "EventCode": "0x4F148",
  29     "EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
  30     "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
  31   },
  32   {,
  33     "EventCode": "0x301E8",
  34     "EventName": "PM_THRESH_EXC_64",
  35     "BriefDescription": "Threshold counter exceeded a value of 64"
  36   },
  37   {,
  38     "EventCode": "0x4E04E",
  39     "EventName": "PM_DPTEG_FROM_L3MISS",
  40     "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
  41   },
  42   {,
  43     "EventCode": "0x40050",
  44     "EventName": "PM_SYS_PUMP_MPRED_RTY",
  45     "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
  46   },
  47   {,
  48     "EventCode": "0x1F14E",
  49     "EventName": "PM_MRK_DPTEG_FROM_L2MISS",
  50     "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
  51   },
  52   {,
  53     "EventCode": "0x4D018",
  54     "EventName": "PM_CMPLU_STALL_BRU",
  55     "BriefDescription": "Completion stall due to a Branch Unit"
  56   },
  57   {,
  58     "EventCode": "0x45052",
  59     "EventName": "PM_4FLOP_CMPL",
  60     "BriefDescription": "4 FLOP instruction completed"
  61   },
  62   {,
  63     "EventCode": "0x3D142",
  64     "EventName": "PM_MRK_DATA_FROM_LMEM",
  65     "BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load"
  66   },
  67   {,
  68     "EventCode": "0x4C01E",
  69     "EventName": "PM_CMPLU_STALL_CRYPTO",
  70     "BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish"
  71   },
  72   {,
  73     "EventCode": "0x3000C",
  74     "EventName": "PM_FREQ_DOWN",
  75     "BriefDescription": "Power Management: Below Threshold B"
  76   },
  77   {,
  78     "EventCode": "0x4D128",
  79     "EventName": "PM_MRK_DATA_FROM_LMEM_CYC",
  80     "BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load"
  81   },
  82   {,
  83     "EventCode": "0x4D054",
  84     "EventName": "PM_8FLOP_CMPL",
  85     "BriefDescription": "8 FLOP instruction completed"
  86   },
  87   {,
  88     "EventCode": "0x10026",
  89     "EventName": "PM_TABLEWALK_CYC",
  90     "BriefDescription": "Cycles when an instruction tablewalk is active"
  91   },
  92   {,
  93     "EventCode": "0x2C012",
  94     "EventName": "PM_CMPLU_STALL_DCACHE_MISS",
  95     "BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest"
  96   },
  97   {,
  98     "EventCode": "0x2E04C",
  99     "EventName": "PM_DPTEG_FROM_MEMORY",
 100     "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
 101   },
 102   {,
 103     "EventCode": "0x3F142",
 104     "EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
 105     "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
 106   },
 107   {,
 108     "EventCode": "0x4F142",
 109     "EventName": "PM_MRK_DPTEG_FROM_L3",
 110     "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
 111   },
 112   {,
 113     "EventCode": "0x10060",
 114     "EventName": "PM_TM_TRANS_RUN_CYC",
 115     "BriefDescription": "run cycles in transactional state"
 116   },
 117   {,
 118     "EventCode": "0x1E04C",
 119     "EventName": "PM_DPTEG_FROM_LL4",
 120     "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
 121   },
 122   {,
 123     "EventCode": "0x45050",
 124     "EventName": "PM_1FLOP_CMPL",
 125     "BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed"
 126   }
 127 ]