2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
5 * Copyright (c) 2013 Intel Corporation.
6 * Len Brown <len.brown@intel.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
24 #include INTEL_FAMILY_HEADER
29 #include <sys/types.h>
32 #include <sys/resource.h>
44 #include <linux/capability.h>
47 char *proc_stat
= "/proc/stat";
50 struct timespec interval_ts
= {5, 0};
53 unsigned int sums_need_wide_columns
;
54 unsigned int rapl_joules
;
55 unsigned int summary_only
;
56 unsigned int list_header_only
;
57 unsigned int dump_only
;
58 unsigned int do_snb_cstates
;
59 unsigned int do_knl_cstates
;
60 unsigned int do_skl_residency
;
61 unsigned int do_slm_cstates
;
62 unsigned int use_c1_residency_msr
;
63 unsigned int has_aperf
;
65 unsigned int do_irtl_snb
;
66 unsigned int do_irtl_hsw
;
67 unsigned int units
= 1000000; /* MHz etc */
68 unsigned int genuine_intel
;
69 unsigned int has_invariant_tsc
;
70 unsigned int do_nhm_platform_info
;
71 unsigned int no_MSR_MISC_PWR_MGMT
;
72 unsigned int aperf_mperf_multiplier
= 1;
75 unsigned int has_base_hz
;
76 double tsc_tweak
= 1.0;
77 unsigned int show_pkg_only
;
78 unsigned int show_core_only
;
79 char *output_buffer
, *outp
;
83 unsigned long long gfx_cur_rc6_ms
;
84 unsigned int gfx_cur_mhz
;
85 unsigned int tcc_activation_temp
;
86 unsigned int tcc_activation_temp_override
;
87 double rapl_power_units
, rapl_time_units
;
88 double rapl_dram_energy_units
, rapl_energy_units
;
89 double rapl_joule_counter_range
;
90 unsigned int do_core_perf_limit_reasons
;
91 unsigned int do_gfx_perf_limit_reasons
;
92 unsigned int do_ring_perf_limit_reasons
;
93 unsigned int crystal_hz
;
94 unsigned long long tsc_hz
;
96 double discover_bclk(unsigned int family
, unsigned int model
);
97 unsigned int has_hwp
; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
98 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */
99 unsigned int has_hwp_notify
; /* IA32_HWP_INTERRUPT */
100 unsigned int has_hwp_activity_window
; /* IA32_HWP_REQUEST[bits 41:32] */
101 unsigned int has_hwp_epp
; /* IA32_HWP_REQUEST[bits 31:24] */
102 unsigned int has_hwp_pkg
; /* IA32_HWP_REQUEST_PKG */
103 unsigned int has_misc_feature_control
;
105 #define RAPL_PKG (1 << 0)
106 /* 0x610 MSR_PKG_POWER_LIMIT */
107 /* 0x611 MSR_PKG_ENERGY_STATUS */
108 #define RAPL_PKG_PERF_STATUS (1 << 1)
109 /* 0x613 MSR_PKG_PERF_STATUS */
110 #define RAPL_PKG_POWER_INFO (1 << 2)
111 /* 0x614 MSR_PKG_POWER_INFO */
113 #define RAPL_DRAM (1 << 3)
114 /* 0x618 MSR_DRAM_POWER_LIMIT */
115 /* 0x619 MSR_DRAM_ENERGY_STATUS */
116 #define RAPL_DRAM_PERF_STATUS (1 << 4)
117 /* 0x61b MSR_DRAM_PERF_STATUS */
118 #define RAPL_DRAM_POWER_INFO (1 << 5)
119 /* 0x61c MSR_DRAM_POWER_INFO */
121 #define RAPL_CORES_POWER_LIMIT (1 << 6)
122 /* 0x638 MSR_PP0_POWER_LIMIT */
123 #define RAPL_CORE_POLICY (1 << 7)
124 /* 0x63a MSR_PP0_POLICY */
126 #define RAPL_GFX (1 << 8)
127 /* 0x640 MSR_PP1_POWER_LIMIT */
128 /* 0x641 MSR_PP1_ENERGY_STATUS */
129 /* 0x642 MSR_PP1_POLICY */
131 #define RAPL_CORES_ENERGY_STATUS (1 << 9)
132 /* 0x639 MSR_PP0_ENERGY_STATUS */
133 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT)
134 #define TJMAX_DEFAULT 100
136 #define MAX(a, b) ((a) > (b) ? (a) : (b))
139 * buffer size used by sscanf() for added column names
140 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters
142 #define NAME_BYTES 20
143 #define PATH_BYTES 128
148 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */
149 cpu_set_t
*cpu_present_set
, *cpu_affinity_set
, *cpu_subset
;
150 size_t cpu_present_setsize
, cpu_affinity_setsize
, cpu_subset_size
;
151 #define MAX_ADDED_COUNTERS 16
154 unsigned long long tsc
;
155 unsigned long long aperf
;
156 unsigned long long mperf
;
157 unsigned long long c1
;
158 unsigned long long irq_count
;
159 unsigned int smi_count
;
162 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2
163 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4
164 unsigned long long counter
[MAX_ADDED_COUNTERS
];
165 } *thread_even
, *thread_odd
;
168 unsigned long long c3
;
169 unsigned long long c6
;
170 unsigned long long c7
;
171 unsigned long long mc6_us
; /* duplicate as per-core for now, even though per module */
172 unsigned int core_temp_c
;
173 unsigned int core_id
;
174 unsigned long long counter
[MAX_ADDED_COUNTERS
];
175 } *core_even
, *core_odd
;
178 unsigned long long pc2
;
179 unsigned long long pc3
;
180 unsigned long long pc6
;
181 unsigned long long pc7
;
182 unsigned long long pc8
;
183 unsigned long long pc9
;
184 unsigned long long pc10
;
185 unsigned long long pkg_wtd_core_c0
;
186 unsigned long long pkg_any_core_c0
;
187 unsigned long long pkg_any_gfxe_c0
;
188 unsigned long long pkg_both_core_gfxe_c0
;
189 long long gfx_rc6_ms
;
190 unsigned int gfx_mhz
;
191 unsigned int package_id
;
192 unsigned int energy_pkg
; /* MSR_PKG_ENERGY_STATUS */
193 unsigned int energy_dram
; /* MSR_DRAM_ENERGY_STATUS */
194 unsigned int energy_cores
; /* MSR_PP0_ENERGY_STATUS */
195 unsigned int energy_gfx
; /* MSR_PP1_ENERGY_STATUS */
196 unsigned int rapl_pkg_perf_status
; /* MSR_PKG_PERF_STATUS */
197 unsigned int rapl_dram_perf_status
; /* MSR_DRAM_PERF_STATUS */
198 unsigned int pkg_temp_c
;
199 unsigned long long counter
[MAX_ADDED_COUNTERS
];
200 } *package_even
, *package_odd
;
202 #define ODD_COUNTERS thread_odd, core_odd, package_odd
203 #define EVEN_COUNTERS thread_even, core_even, package_even
205 #define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \
206 (thread_base + (pkg_no) * topo.num_cores_per_pkg * \
207 topo.num_threads_per_core + \
208 (core_no) * topo.num_threads_per_core + (thread_no))
209 #define GET_CORE(core_base, core_no, pkg_no) \
210 (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no))
211 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no)
213 enum counter_scope
{SCOPE_CPU
, SCOPE_CORE
, SCOPE_PACKAGE
};
214 enum counter_type
{COUNTER_ITEMS
, COUNTER_CYCLES
, COUNTER_SECONDS
, COUNTER_USEC
};
215 enum counter_format
{FORMAT_RAW
, FORMAT_DELTA
, FORMAT_PERCENT
};
218 unsigned int msr_num
;
219 char name
[NAME_BYTES
];
220 char path
[PATH_BYTES
];
222 enum counter_type type
;
223 enum counter_format format
;
224 struct msr_counter
*next
;
226 #define FLAGS_HIDE (1 << 0)
227 #define FLAGS_SHOW (1 << 1)
228 #define SYSFS_PERCPU (1 << 1)
231 struct sys_counters
{
232 unsigned int added_thread_counters
;
233 unsigned int added_core_counters
;
234 unsigned int added_package_counters
;
235 struct msr_counter
*tp
;
236 struct msr_counter
*cp
;
237 struct msr_counter
*pp
;
240 struct system_summary
{
241 struct thread_data threads
;
242 struct core_data cores
;
243 struct pkg_data packages
;
252 int num_cores_per_pkg
;
253 int num_threads_per_core
;
256 struct timeval tv_even
, tv_odd
, tv_delta
;
258 int *irq_column_2_cpu
; /* /proc/interrupts column numbers */
259 int *irqs_per_cpu
; /* indexed by cpu_num */
261 void setup_all_buffers(void);
263 int cpu_is_not_present(int cpu
)
265 return !CPU_ISSET_S(cpu
, cpu_present_setsize
, cpu_present_set
);
268 * run func(thread, core, package) in topology order
269 * skip non-present cpus
272 int for_all_cpus(int (func
)(struct thread_data
*, struct core_data
*, struct pkg_data
*),
273 struct thread_data
*thread_base
, struct core_data
*core_base
, struct pkg_data
*pkg_base
)
275 int retval
, pkg_no
, core_no
, thread_no
;
277 for (pkg_no
= 0; pkg_no
< topo
.num_packages
; ++pkg_no
) {
278 for (core_no
= 0; core_no
< topo
.num_cores_per_pkg
; ++core_no
) {
279 for (thread_no
= 0; thread_no
<
280 topo
.num_threads_per_core
; ++thread_no
) {
281 struct thread_data
*t
;
285 t
= GET_THREAD(thread_base
, thread_no
, core_no
, pkg_no
);
287 if (cpu_is_not_present(t
->cpu_id
))
290 c
= GET_CORE(core_base
, core_no
, pkg_no
);
291 p
= GET_PKG(pkg_base
, pkg_no
);
293 retval
= func(t
, c
, p
);
302 int cpu_migrate(int cpu
)
304 CPU_ZERO_S(cpu_affinity_setsize
, cpu_affinity_set
);
305 CPU_SET_S(cpu
, cpu_affinity_setsize
, cpu_affinity_set
);
306 if (sched_setaffinity(0, cpu_affinity_setsize
, cpu_affinity_set
) == -1)
311 int get_msr_fd(int cpu
)
321 sprintf(pathname
, "/dev/cpu/%d/msr", cpu
);
322 fd
= open(pathname
, O_RDONLY
);
324 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname
);
331 int get_msr(int cpu
, off_t offset
, unsigned long long *msr
)
335 retval
= pread(get_msr_fd(cpu
), msr
, sizeof(*msr
), offset
);
337 if (retval
!= sizeof *msr
)
338 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu
, (unsigned long long)offset
);
344 * Each string in this array is compared in --show and --hide cmdline.
345 * Thus, strings that are proper sub-sets must follow their more specific peers.
347 struct msr_counter bic
[] = {
353 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA
, NULL
},
389 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
390 #define BIC_Package (1ULL << 0)
391 #define BIC_Avg_MHz (1ULL << 1)
392 #define BIC_Bzy_MHz (1ULL << 2)
393 #define BIC_TSC_MHz (1ULL << 3)
394 #define BIC_IRQ (1ULL << 4)
395 #define BIC_SMI (1ULL << 5)
396 #define BIC_Busy (1ULL << 6)
397 #define BIC_CPU_c1 (1ULL << 7)
398 #define BIC_CPU_c3 (1ULL << 8)
399 #define BIC_CPU_c6 (1ULL << 9)
400 #define BIC_CPU_c7 (1ULL << 10)
401 #define BIC_ThreadC (1ULL << 11)
402 #define BIC_CoreTmp (1ULL << 12)
403 #define BIC_CoreCnt (1ULL << 13)
404 #define BIC_PkgTmp (1ULL << 14)
405 #define BIC_GFX_rc6 (1ULL << 15)
406 #define BIC_GFXMHz (1ULL << 16)
407 #define BIC_Pkgpc2 (1ULL << 17)
408 #define BIC_Pkgpc3 (1ULL << 18)
409 #define BIC_Pkgpc6 (1ULL << 19)
410 #define BIC_Pkgpc7 (1ULL << 20)
411 #define BIC_Pkgpc8 (1ULL << 21)
412 #define BIC_Pkgpc9 (1ULL << 22)
413 #define BIC_Pkgpc10 (1ULL << 23)
414 #define BIC_PkgWatt (1ULL << 24)
415 #define BIC_CorWatt (1ULL << 25)
416 #define BIC_GFXWatt (1ULL << 26)
417 #define BIC_PkgCnt (1ULL << 27)
418 #define BIC_RAMWatt (1ULL << 28)
419 #define BIC_PKG__ (1ULL << 29)
420 #define BIC_RAM__ (1ULL << 30)
421 #define BIC_Pkg_J (1ULL << 31)
422 #define BIC_Cor_J (1ULL << 32)
423 #define BIC_GFX_J (1ULL << 33)
424 #define BIC_RAM_J (1ULL << 34)
425 #define BIC_Core (1ULL << 35)
426 #define BIC_CPU (1ULL << 36)
427 #define BIC_Mod_c6 (1ULL << 37)
428 #define BIC_sysfs (1ULL << 38)
430 unsigned long long bic_enabled
= 0xFFFFFFFFFFFFFFFFULL
;
431 unsigned long long bic_present
= BIC_sysfs
;
433 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME)
434 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT)
435 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT)
437 #define MAX_DEFERRED 16
438 char *deferred_skip_names
[MAX_DEFERRED
];
439 int deferred_skip_index
;
442 * HIDE_LIST - hide this list of counters, show the rest [default]
443 * SHOW_LIST - show this list of counters, hide the rest
445 enum show_hide_mode
{ SHOW_LIST
, HIDE_LIST
} global_show_hide_mode
= HIDE_LIST
;
450 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n"
452 "Turbostat forks the specified COMMAND and prints statistics\n"
453 "when COMMAND completes.\n"
454 "If no COMMAND is specified, turbostat wakes every 5-seconds\n"
455 "to print statistics, until interrupted.\n"
456 "--add add a counter\n"
457 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n"
458 "--cpu cpu-set limit output to summary plus cpu-set:\n"
459 " {core | package | j,k,l..m,n-p }\n"
460 "--quiet skip decoding system configuration header\n"
461 "--interval sec Override default 5-second measurement interval\n"
462 "--help print this help message\n"
463 "--list list column headers only\n"
464 "--out file create or truncate \"file\" for all output\n"
465 "--version print version information\n"
467 "For more help, run \"man turbostat\"\n");
472 * for all the strings in comma separate name_list,
473 * set the approprate bit in return value.
475 unsigned long long bic_lookup(char *name_list
, enum show_hide_mode mode
)
478 unsigned long long retval
= 0;
483 comma
= strchr(name_list
, ',');
488 for (i
= 0; i
< MAX_BIC
; ++i
) {
489 if (!strcmp(name_list
, bic
[i
].name
)) {
490 retval
|= (1ULL << i
);
495 if (mode
== SHOW_LIST
) {
496 fprintf(stderr
, "Invalid counter name: %s\n", name_list
);
499 deferred_skip_names
[deferred_skip_index
++] = name_list
;
501 fprintf(stderr
, "deferred \"%s\"\n", name_list
);
502 if (deferred_skip_index
>= MAX_DEFERRED
) {
503 fprintf(stderr
, "More than max %d un-recognized --skip options '%s'\n",
504 MAX_DEFERRED
, name_list
);
519 void print_header(char *delim
)
521 struct msr_counter
*mp
;
524 if (DO_BIC(BIC_Package
))
525 outp
+= sprintf(outp
, "%sPackage", (printed
++ ? delim
: ""));
526 if (DO_BIC(BIC_Core
))
527 outp
+= sprintf(outp
, "%sCore", (printed
++ ? delim
: ""));
529 outp
+= sprintf(outp
, "%sCPU", (printed
++ ? delim
: ""));
530 if (DO_BIC(BIC_Avg_MHz
))
531 outp
+= sprintf(outp
, "%sAvg_MHz", (printed
++ ? delim
: ""));
532 if (DO_BIC(BIC_Busy
))
533 outp
+= sprintf(outp
, "%sBusy%%", (printed
++ ? delim
: ""));
534 if (DO_BIC(BIC_Bzy_MHz
))
535 outp
+= sprintf(outp
, "%sBzy_MHz", (printed
++ ? delim
: ""));
536 if (DO_BIC(BIC_TSC_MHz
))
537 outp
+= sprintf(outp
, "%sTSC_MHz", (printed
++ ? delim
: ""));
539 if (DO_BIC(BIC_IRQ
)) {
540 if (sums_need_wide_columns
)
541 outp
+= sprintf(outp
, "%s IRQ", (printed
++ ? delim
: ""));
543 outp
+= sprintf(outp
, "%sIRQ", (printed
++ ? delim
: ""));
547 outp
+= sprintf(outp
, "%sSMI", (printed
++ ? delim
: ""));
549 for (mp
= sys
.tp
; mp
; mp
= mp
->next
) {
551 if (mp
->format
== FORMAT_RAW
) {
553 outp
+= sprintf(outp
, "%s%18.18s", (printed
++ ? delim
: ""), mp
->name
);
555 outp
+= sprintf(outp
, "%s%10.10s", (printed
++ ? delim
: ""), mp
->name
);
557 if ((mp
->type
== COUNTER_ITEMS
) && sums_need_wide_columns
)
558 outp
+= sprintf(outp
, "%s%8s", (printed
++ ? delim
: ""), mp
->name
);
560 outp
+= sprintf(outp
, "%s%s", (printed
++ ? delim
: ""), mp
->name
);
564 if (DO_BIC(BIC_CPU_c1
))
565 outp
+= sprintf(outp
, "%sCPU%%c1", (printed
++ ? delim
: ""));
566 if (DO_BIC(BIC_CPU_c3
) && !do_slm_cstates
&& !do_knl_cstates
)
567 outp
+= sprintf(outp
, "%sCPU%%c3", (printed
++ ? delim
: ""));
568 if (DO_BIC(BIC_CPU_c6
))
569 outp
+= sprintf(outp
, "%sCPU%%c6", (printed
++ ? delim
: ""));
570 if (DO_BIC(BIC_CPU_c7
))
571 outp
+= sprintf(outp
, "%sCPU%%c7", (printed
++ ? delim
: ""));
573 if (DO_BIC(BIC_Mod_c6
))
574 outp
+= sprintf(outp
, "%sMod%%c6", (printed
++ ? delim
: ""));
576 if (DO_BIC(BIC_CoreTmp
))
577 outp
+= sprintf(outp
, "%sCoreTmp", (printed
++ ? delim
: ""));
579 for (mp
= sys
.cp
; mp
; mp
= mp
->next
) {
580 if (mp
->format
== FORMAT_RAW
) {
582 outp
+= sprintf(outp
, "%s%18.18s", delim
, mp
->name
);
584 outp
+= sprintf(outp
, "%s%10.10s", delim
, mp
->name
);
586 if ((mp
->type
== COUNTER_ITEMS
) && sums_need_wide_columns
)
587 outp
+= sprintf(outp
, "%s%8s", delim
, mp
->name
);
589 outp
+= sprintf(outp
, "%s%s", delim
, mp
->name
);
593 if (DO_BIC(BIC_PkgTmp
))
594 outp
+= sprintf(outp
, "%sPkgTmp", (printed
++ ? delim
: ""));
596 if (DO_BIC(BIC_GFX_rc6
))
597 outp
+= sprintf(outp
, "%sGFX%%rc6", (printed
++ ? delim
: ""));
599 if (DO_BIC(BIC_GFXMHz
))
600 outp
+= sprintf(outp
, "%sGFXMHz", (printed
++ ? delim
: ""));
602 if (do_skl_residency
) {
603 outp
+= sprintf(outp
, "%sTotl%%C0", (printed
++ ? delim
: ""));
604 outp
+= sprintf(outp
, "%sAny%%C0", (printed
++ ? delim
: ""));
605 outp
+= sprintf(outp
, "%sGFX%%C0", (printed
++ ? delim
: ""));
606 outp
+= sprintf(outp
, "%sCPUGFX%%", (printed
++ ? delim
: ""));
609 if (DO_BIC(BIC_Pkgpc2
))
610 outp
+= sprintf(outp
, "%sPkg%%pc2", (printed
++ ? delim
: ""));
611 if (DO_BIC(BIC_Pkgpc3
))
612 outp
+= sprintf(outp
, "%sPkg%%pc3", (printed
++ ? delim
: ""));
613 if (DO_BIC(BIC_Pkgpc6
))
614 outp
+= sprintf(outp
, "%sPkg%%pc6", (printed
++ ? delim
: ""));
615 if (DO_BIC(BIC_Pkgpc7
))
616 outp
+= sprintf(outp
, "%sPkg%%pc7", (printed
++ ? delim
: ""));
617 if (DO_BIC(BIC_Pkgpc8
))
618 outp
+= sprintf(outp
, "%sPkg%%pc8", (printed
++ ? delim
: ""));
619 if (DO_BIC(BIC_Pkgpc9
))
620 outp
+= sprintf(outp
, "%sPkg%%pc9", (printed
++ ? delim
: ""));
621 if (DO_BIC(BIC_Pkgpc10
))
622 outp
+= sprintf(outp
, "%sPk%%pc10", (printed
++ ? delim
: ""));
624 if (do_rapl
&& !rapl_joules
) {
625 if (DO_BIC(BIC_PkgWatt
))
626 outp
+= sprintf(outp
, "%sPkgWatt", (printed
++ ? delim
: ""));
627 if (DO_BIC(BIC_CorWatt
))
628 outp
+= sprintf(outp
, "%sCorWatt", (printed
++ ? delim
: ""));
629 if (DO_BIC(BIC_GFXWatt
))
630 outp
+= sprintf(outp
, "%sGFXWatt", (printed
++ ? delim
: ""));
631 if (DO_BIC(BIC_RAMWatt
))
632 outp
+= sprintf(outp
, "%sRAMWatt", (printed
++ ? delim
: ""));
633 if (DO_BIC(BIC_PKG__
))
634 outp
+= sprintf(outp
, "%sPKG_%%", (printed
++ ? delim
: ""));
635 if (DO_BIC(BIC_RAM__
))
636 outp
+= sprintf(outp
, "%sRAM_%%", (printed
++ ? delim
: ""));
637 } else if (do_rapl
&& rapl_joules
) {
638 if (DO_BIC(BIC_Pkg_J
))
639 outp
+= sprintf(outp
, "%sPkg_J", (printed
++ ? delim
: ""));
640 if (DO_BIC(BIC_Cor_J
))
641 outp
+= sprintf(outp
, "%sCor_J", (printed
++ ? delim
: ""));
642 if (DO_BIC(BIC_GFX_J
))
643 outp
+= sprintf(outp
, "%sGFX_J", (printed
++ ? delim
: ""));
644 if (DO_BIC(BIC_RAM_J
))
645 outp
+= sprintf(outp
, "%sRAM_J", (printed
++ ? delim
: ""));
646 if (DO_BIC(BIC_PKG__
))
647 outp
+= sprintf(outp
, "%sPKG_%%", (printed
++ ? delim
: ""));
648 if (DO_BIC(BIC_RAM__
))
649 outp
+= sprintf(outp
, "%sRAM_%%", (printed
++ ? delim
: ""));
651 for (mp
= sys
.pp
; mp
; mp
= mp
->next
) {
652 if (mp
->format
== FORMAT_RAW
) {
654 outp
+= sprintf(outp
, "%s%18.18s", delim
, mp
->name
);
656 outp
+= sprintf(outp
, "%s%10.10s", delim
, mp
->name
);
658 if ((mp
->type
== COUNTER_ITEMS
) && sums_need_wide_columns
)
659 outp
+= sprintf(outp
, "%s%8s", delim
, mp
->name
);
661 outp
+= sprintf(outp
, "%s%s", delim
, mp
->name
);
665 outp
+= sprintf(outp
, "\n");
668 int dump_counters(struct thread_data
*t
, struct core_data
*c
,
672 struct msr_counter
*mp
;
674 outp
+= sprintf(outp
, "t %p, c %p, p %p\n", t
, c
, p
);
677 outp
+= sprintf(outp
, "CPU: %d flags 0x%x\n",
678 t
->cpu_id
, t
->flags
);
679 outp
+= sprintf(outp
, "TSC: %016llX\n", t
->tsc
);
680 outp
+= sprintf(outp
, "aperf: %016llX\n", t
->aperf
);
681 outp
+= sprintf(outp
, "mperf: %016llX\n", t
->mperf
);
682 outp
+= sprintf(outp
, "c1: %016llX\n", t
->c1
);
685 outp
+= sprintf(outp
, "IRQ: %lld\n", t
->irq_count
);
687 outp
+= sprintf(outp
, "SMI: %d\n", t
->smi_count
);
689 for (i
= 0, mp
= sys
.tp
; mp
; i
++, mp
= mp
->next
) {
690 outp
+= sprintf(outp
, "tADDED [%d] msr0x%x: %08llX\n",
691 i
, mp
->msr_num
, t
->counter
[i
]);
696 outp
+= sprintf(outp
, "core: %d\n", c
->core_id
);
697 outp
+= sprintf(outp
, "c3: %016llX\n", c
->c3
);
698 outp
+= sprintf(outp
, "c6: %016llX\n", c
->c6
);
699 outp
+= sprintf(outp
, "c7: %016llX\n", c
->c7
);
700 outp
+= sprintf(outp
, "DTS: %dC\n", c
->core_temp_c
);
702 for (i
= 0, mp
= sys
.cp
; mp
; i
++, mp
= mp
->next
) {
703 outp
+= sprintf(outp
, "cADDED [%d] msr0x%x: %08llX\n",
704 i
, mp
->msr_num
, c
->counter
[i
]);
706 outp
+= sprintf(outp
, "mc6_us: %016llX\n", c
->mc6_us
);
710 outp
+= sprintf(outp
, "package: %d\n", p
->package_id
);
712 outp
+= sprintf(outp
, "Weighted cores: %016llX\n", p
->pkg_wtd_core_c0
);
713 outp
+= sprintf(outp
, "Any cores: %016llX\n", p
->pkg_any_core_c0
);
714 outp
+= sprintf(outp
, "Any GFX: %016llX\n", p
->pkg_any_gfxe_c0
);
715 outp
+= sprintf(outp
, "CPU + GFX: %016llX\n", p
->pkg_both_core_gfxe_c0
);
717 outp
+= sprintf(outp
, "pc2: %016llX\n", p
->pc2
);
718 if (DO_BIC(BIC_Pkgpc3
))
719 outp
+= sprintf(outp
, "pc3: %016llX\n", p
->pc3
);
720 if (DO_BIC(BIC_Pkgpc6
))
721 outp
+= sprintf(outp
, "pc6: %016llX\n", p
->pc6
);
722 if (DO_BIC(BIC_Pkgpc7
))
723 outp
+= sprintf(outp
, "pc7: %016llX\n", p
->pc7
);
724 outp
+= sprintf(outp
, "pc8: %016llX\n", p
->pc8
);
725 outp
+= sprintf(outp
, "pc9: %016llX\n", p
->pc9
);
726 outp
+= sprintf(outp
, "pc10: %016llX\n", p
->pc10
);
727 outp
+= sprintf(outp
, "Joules PKG: %0X\n", p
->energy_pkg
);
728 outp
+= sprintf(outp
, "Joules COR: %0X\n", p
->energy_cores
);
729 outp
+= sprintf(outp
, "Joules GFX: %0X\n", p
->energy_gfx
);
730 outp
+= sprintf(outp
, "Joules RAM: %0X\n", p
->energy_dram
);
731 outp
+= sprintf(outp
, "Throttle PKG: %0X\n",
732 p
->rapl_pkg_perf_status
);
733 outp
+= sprintf(outp
, "Throttle RAM: %0X\n",
734 p
->rapl_dram_perf_status
);
735 outp
+= sprintf(outp
, "PTM: %dC\n", p
->pkg_temp_c
);
737 for (i
= 0, mp
= sys
.pp
; mp
; i
++, mp
= mp
->next
) {
738 outp
+= sprintf(outp
, "pADDED [%d] msr0x%x: %08llX\n",
739 i
, mp
->msr_num
, p
->counter
[i
]);
743 outp
+= sprintf(outp
, "\n");
749 * column formatting convention & formats
751 int format_counters(struct thread_data
*t
, struct core_data
*c
,
754 double interval_float
, tsc
;
757 struct msr_counter
*mp
;
761 /* if showing only 1st thread in core and this isn't one, bail out */
762 if (show_core_only
&& !(t
->flags
& CPU_IS_FIRST_THREAD_IN_CORE
))
765 /* if showing only 1st thread in pkg and this isn't one, bail out */
766 if (show_pkg_only
&& !(t
->flags
& CPU_IS_FIRST_CORE_IN_PACKAGE
))
769 /*if not summary line and --cpu is used */
770 if ((t
!= &average
.threads
) &&
771 (cpu_subset
&& !CPU_ISSET_S(t
->cpu_id
, cpu_subset_size
, cpu_subset
)))
774 interval_float
= tv_delta
.tv_sec
+ tv_delta
.tv_usec
/1000000.0;
776 tsc
= t
->tsc
* tsc_tweak
;
778 /* topo columns, print blanks on 1st (average) line */
779 if (t
== &average
.threads
) {
780 if (DO_BIC(BIC_Package
))
781 outp
+= sprintf(outp
, "%s-", (printed
++ ? delim
: ""));
782 if (DO_BIC(BIC_Core
))
783 outp
+= sprintf(outp
, "%s-", (printed
++ ? delim
: ""));
785 outp
+= sprintf(outp
, "%s-", (printed
++ ? delim
: ""));
787 if (DO_BIC(BIC_Package
)) {
789 outp
+= sprintf(outp
, "%s%d", (printed
++ ? delim
: ""), p
->package_id
);
791 outp
+= sprintf(outp
, "%s-", (printed
++ ? delim
: ""));
793 if (DO_BIC(BIC_Core
)) {
795 outp
+= sprintf(outp
, "%s%d", (printed
++ ? delim
: ""), c
->core_id
);
797 outp
+= sprintf(outp
, "%s-", (printed
++ ? delim
: ""));
800 outp
+= sprintf(outp
, "%s%d", (printed
++ ? delim
: ""), t
->cpu_id
);
803 if (DO_BIC(BIC_Avg_MHz
))
804 outp
+= sprintf(outp
, "%s%.0f", (printed
++ ? delim
: ""),
805 1.0 / units
* t
->aperf
/ interval_float
);
807 if (DO_BIC(BIC_Busy
))
808 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * t
->mperf
/tsc
);
810 if (DO_BIC(BIC_Bzy_MHz
)) {
812 outp
+= sprintf(outp
, "%s%.0f", (printed
++ ? delim
: ""), base_hz
/ units
* t
->aperf
/ t
->mperf
);
814 outp
+= sprintf(outp
, "%s%.0f", (printed
++ ? delim
: ""),
815 tsc
/ units
* t
->aperf
/ t
->mperf
/ interval_float
);
818 if (DO_BIC(BIC_TSC_MHz
))
819 outp
+= sprintf(outp
, "%s%.0f", (printed
++ ? delim
: ""), 1.0 * t
->tsc
/units
/interval_float
);
822 if (DO_BIC(BIC_IRQ
)) {
823 if (sums_need_wide_columns
)
824 outp
+= sprintf(outp
, "%s%8lld", (printed
++ ? delim
: ""), t
->irq_count
);
826 outp
+= sprintf(outp
, "%s%lld", (printed
++ ? delim
: ""), t
->irq_count
);
831 outp
+= sprintf(outp
, "%s%d", (printed
++ ? delim
: ""), t
->smi_count
);
834 for (i
= 0, mp
= sys
.tp
; mp
; i
++, mp
= mp
->next
) {
835 if (mp
->format
== FORMAT_RAW
) {
837 outp
+= sprintf(outp
, "%s0x%08x", (printed
++ ? delim
: ""), (unsigned int) t
->counter
[i
]);
839 outp
+= sprintf(outp
, "%s0x%016llx", (printed
++ ? delim
: ""), t
->counter
[i
]);
840 } else if (mp
->format
== FORMAT_DELTA
) {
841 if ((mp
->type
== COUNTER_ITEMS
) && sums_need_wide_columns
)
842 outp
+= sprintf(outp
, "%s%8lld", (printed
++ ? delim
: ""), t
->counter
[i
]);
844 outp
+= sprintf(outp
, "%s%lld", (printed
++ ? delim
: ""), t
->counter
[i
]);
845 } else if (mp
->format
== FORMAT_PERCENT
) {
846 if (mp
->type
== COUNTER_USEC
)
847 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), t
->counter
[i
]/interval_float
/10000);
849 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * t
->counter
[i
]/tsc
);
854 if (DO_BIC(BIC_CPU_c1
))
855 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * t
->c1
/tsc
);
858 /* print per-core data only for 1st thread in core */
859 if (!(t
->flags
& CPU_IS_FIRST_THREAD_IN_CORE
))
862 if (DO_BIC(BIC_CPU_c3
) && !do_slm_cstates
&& !do_knl_cstates
)
863 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * c
->c3
/tsc
);
864 if (DO_BIC(BIC_CPU_c6
))
865 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * c
->c6
/tsc
);
866 if (DO_BIC(BIC_CPU_c7
))
867 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * c
->c7
/tsc
);
870 if (DO_BIC(BIC_Mod_c6
))
871 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * c
->mc6_us
/ tsc
);
873 if (DO_BIC(BIC_CoreTmp
))
874 outp
+= sprintf(outp
, "%s%d", (printed
++ ? delim
: ""), c
->core_temp_c
);
876 for (i
= 0, mp
= sys
.cp
; mp
; i
++, mp
= mp
->next
) {
877 if (mp
->format
== FORMAT_RAW
) {
879 outp
+= sprintf(outp
, "%s0x%08x", (printed
++ ? delim
: ""), (unsigned int) c
->counter
[i
]);
881 outp
+= sprintf(outp
, "%s0x%016llx", (printed
++ ? delim
: ""), c
->counter
[i
]);
882 } else if (mp
->format
== FORMAT_DELTA
) {
883 if ((mp
->type
== COUNTER_ITEMS
) && sums_need_wide_columns
)
884 outp
+= sprintf(outp
, "%s%8lld", (printed
++ ? delim
: ""), c
->counter
[i
]);
886 outp
+= sprintf(outp
, "%s%lld", (printed
++ ? delim
: ""), c
->counter
[i
]);
887 } else if (mp
->format
== FORMAT_PERCENT
) {
888 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * c
->counter
[i
]/tsc
);
892 /* print per-package data only for 1st core in package */
893 if (!(t
->flags
& CPU_IS_FIRST_CORE_IN_PACKAGE
))
897 if (DO_BIC(BIC_PkgTmp
))
898 outp
+= sprintf(outp
, "%s%d", (printed
++ ? delim
: ""), p
->pkg_temp_c
);
901 if (DO_BIC(BIC_GFX_rc6
)) {
902 if (p
->gfx_rc6_ms
== -1) { /* detect GFX counter reset */
903 outp
+= sprintf(outp
, "%s**.**", (printed
++ ? delim
: ""));
905 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""),
906 p
->gfx_rc6_ms
/ 10.0 / interval_float
);
911 if (DO_BIC(BIC_GFXMHz
))
912 outp
+= sprintf(outp
, "%s%d", (printed
++ ? delim
: ""), p
->gfx_mhz
);
914 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
915 if (do_skl_residency
) {
916 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * p
->pkg_wtd_core_c0
/tsc
);
917 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * p
->pkg_any_core_c0
/tsc
);
918 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * p
->pkg_any_gfxe_c0
/tsc
);
919 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * p
->pkg_both_core_gfxe_c0
/tsc
);
922 if (DO_BIC(BIC_Pkgpc2
))
923 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * p
->pc2
/tsc
);
924 if (DO_BIC(BIC_Pkgpc3
))
925 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * p
->pc3
/tsc
);
926 if (DO_BIC(BIC_Pkgpc6
))
927 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * p
->pc6
/tsc
);
928 if (DO_BIC(BIC_Pkgpc7
))
929 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * p
->pc7
/tsc
);
930 if (DO_BIC(BIC_Pkgpc8
))
931 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * p
->pc8
/tsc
);
932 if (DO_BIC(BIC_Pkgpc9
))
933 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * p
->pc9
/tsc
);
934 if (DO_BIC(BIC_Pkgpc10
))
935 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * p
->pc10
/tsc
);
938 * If measurement interval exceeds minimum RAPL Joule Counter range,
939 * indicate that results are suspect by printing "**" in fraction place.
941 if (interval_float
< rapl_joule_counter_range
)
946 if (DO_BIC(BIC_PkgWatt
))
947 outp
+= sprintf(outp
, fmt8
, (printed
++ ? delim
: ""), p
->energy_pkg
* rapl_energy_units
/ interval_float
);
948 if (DO_BIC(BIC_CorWatt
))
949 outp
+= sprintf(outp
, fmt8
, (printed
++ ? delim
: ""), p
->energy_cores
* rapl_energy_units
/ interval_float
);
950 if (DO_BIC(BIC_GFXWatt
))
951 outp
+= sprintf(outp
, fmt8
, (printed
++ ? delim
: ""), p
->energy_gfx
* rapl_energy_units
/ interval_float
);
952 if (DO_BIC(BIC_RAMWatt
))
953 outp
+= sprintf(outp
, fmt8
, (printed
++ ? delim
: ""), p
->energy_dram
* rapl_dram_energy_units
/ interval_float
);
954 if (DO_BIC(BIC_Pkg_J
))
955 outp
+= sprintf(outp
, fmt8
, (printed
++ ? delim
: ""), p
->energy_pkg
* rapl_energy_units
);
956 if (DO_BIC(BIC_Cor_J
))
957 outp
+= sprintf(outp
, fmt8
, (printed
++ ? delim
: ""), p
->energy_cores
* rapl_energy_units
);
958 if (DO_BIC(BIC_GFX_J
))
959 outp
+= sprintf(outp
, fmt8
, (printed
++ ? delim
: ""), p
->energy_gfx
* rapl_energy_units
);
960 if (DO_BIC(BIC_RAM_J
))
961 outp
+= sprintf(outp
, fmt8
, (printed
++ ? delim
: ""), p
->energy_dram
* rapl_dram_energy_units
);
962 if (DO_BIC(BIC_PKG__
))
963 outp
+= sprintf(outp
, fmt8
, (printed
++ ? delim
: ""), 100.0 * p
->rapl_pkg_perf_status
* rapl_time_units
/ interval_float
);
964 if (DO_BIC(BIC_RAM__
))
965 outp
+= sprintf(outp
, fmt8
, (printed
++ ? delim
: ""), 100.0 * p
->rapl_dram_perf_status
* rapl_time_units
/ interval_float
);
967 for (i
= 0, mp
= sys
.pp
; mp
; i
++, mp
= mp
->next
) {
968 if (mp
->format
== FORMAT_RAW
) {
970 outp
+= sprintf(outp
, "%s0x%08x", (printed
++ ? delim
: ""), (unsigned int) p
->counter
[i
]);
972 outp
+= sprintf(outp
, "%s0x%016llx", (printed
++ ? delim
: ""), p
->counter
[i
]);
973 } else if (mp
->format
== FORMAT_DELTA
) {
974 if ((mp
->type
== COUNTER_ITEMS
) && sums_need_wide_columns
)
975 outp
+= sprintf(outp
, "%s%8lld", (printed
++ ? delim
: ""), p
->counter
[i
]);
977 outp
+= sprintf(outp
, "%s%lld", (printed
++ ? delim
: ""), p
->counter
[i
]);
978 } else if (mp
->format
== FORMAT_PERCENT
) {
979 outp
+= sprintf(outp
, "%s%.2f", (printed
++ ? delim
: ""), 100.0 * p
->counter
[i
]/tsc
);
984 outp
+= sprintf(outp
, "\n");
989 void flush_output_stdout(void)
998 fputs(output_buffer
, filep
);
1001 outp
= output_buffer
;
1003 void flush_output_stderr(void)
1005 fputs(output_buffer
, outf
);
1007 outp
= output_buffer
;
1009 void format_all_counters(struct thread_data
*t
, struct core_data
*c
, struct pkg_data
*p
)
1013 if (!printed
|| !summary_only
)
1016 if (topo
.num_cpus
> 1)
1017 format_counters(&average
.threads
, &average
.cores
,
1025 for_all_cpus(format_counters
, t
, c
, p
);
1028 #define DELTA_WRAP32(new, old) \
1032 old = 0x100000000 + new - old; \
1036 delta_package(struct pkg_data
*new, struct pkg_data
*old
)
1039 struct msr_counter
*mp
;
1041 if (do_skl_residency
) {
1042 old
->pkg_wtd_core_c0
= new->pkg_wtd_core_c0
- old
->pkg_wtd_core_c0
;
1043 old
->pkg_any_core_c0
= new->pkg_any_core_c0
- old
->pkg_any_core_c0
;
1044 old
->pkg_any_gfxe_c0
= new->pkg_any_gfxe_c0
- old
->pkg_any_gfxe_c0
;
1045 old
->pkg_both_core_gfxe_c0
= new->pkg_both_core_gfxe_c0
- old
->pkg_both_core_gfxe_c0
;
1047 old
->pc2
= new->pc2
- old
->pc2
;
1048 if (DO_BIC(BIC_Pkgpc3
))
1049 old
->pc3
= new->pc3
- old
->pc3
;
1050 if (DO_BIC(BIC_Pkgpc6
))
1051 old
->pc6
= new->pc6
- old
->pc6
;
1052 if (DO_BIC(BIC_Pkgpc7
))
1053 old
->pc7
= new->pc7
- old
->pc7
;
1054 old
->pc8
= new->pc8
- old
->pc8
;
1055 old
->pc9
= new->pc9
- old
->pc9
;
1056 old
->pc10
= new->pc10
- old
->pc10
;
1057 old
->pkg_temp_c
= new->pkg_temp_c
;
1059 /* flag an error when rc6 counter resets/wraps */
1060 if (old
->gfx_rc6_ms
> new->gfx_rc6_ms
)
1061 old
->gfx_rc6_ms
= -1;
1063 old
->gfx_rc6_ms
= new->gfx_rc6_ms
- old
->gfx_rc6_ms
;
1065 old
->gfx_mhz
= new->gfx_mhz
;
1067 DELTA_WRAP32(new->energy_pkg
, old
->energy_pkg
);
1068 DELTA_WRAP32(new->energy_cores
, old
->energy_cores
);
1069 DELTA_WRAP32(new->energy_gfx
, old
->energy_gfx
);
1070 DELTA_WRAP32(new->energy_dram
, old
->energy_dram
);
1071 DELTA_WRAP32(new->rapl_pkg_perf_status
, old
->rapl_pkg_perf_status
);
1072 DELTA_WRAP32(new->rapl_dram_perf_status
, old
->rapl_dram_perf_status
);
1074 for (i
= 0, mp
= sys
.pp
; mp
; i
++, mp
= mp
->next
) {
1075 if (mp
->format
== FORMAT_RAW
)
1076 old
->counter
[i
] = new->counter
[i
];
1078 old
->counter
[i
] = new->counter
[i
] - old
->counter
[i
];
1085 delta_core(struct core_data
*new, struct core_data
*old
)
1088 struct msr_counter
*mp
;
1090 old
->c3
= new->c3
- old
->c3
;
1091 old
->c6
= new->c6
- old
->c6
;
1092 old
->c7
= new->c7
- old
->c7
;
1093 old
->core_temp_c
= new->core_temp_c
;
1094 old
->mc6_us
= new->mc6_us
- old
->mc6_us
;
1096 for (i
= 0, mp
= sys
.cp
; mp
; i
++, mp
= mp
->next
) {
1097 if (mp
->format
== FORMAT_RAW
)
1098 old
->counter
[i
] = new->counter
[i
];
1100 old
->counter
[i
] = new->counter
[i
] - old
->counter
[i
];
1108 delta_thread(struct thread_data
*new, struct thread_data
*old
,
1109 struct core_data
*core_delta
)
1112 struct msr_counter
*mp
;
1114 old
->tsc
= new->tsc
- old
->tsc
;
1116 /* check for TSC < 1 Mcycles over interval */
1117 if (old
->tsc
< (1000 * 1000))
1118 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n"
1119 "You can disable all c-states by booting with \"idle=poll\"\n"
1120 "or just the deep ones with \"processor.max_cstate=1\"");
1122 old
->c1
= new->c1
- old
->c1
;
1124 if (DO_BIC(BIC_Avg_MHz
) || DO_BIC(BIC_Busy
) || DO_BIC(BIC_Bzy_MHz
)) {
1125 if ((new->aperf
> old
->aperf
) && (new->mperf
> old
->mperf
)) {
1126 old
->aperf
= new->aperf
- old
->aperf
;
1127 old
->mperf
= new->mperf
- old
->mperf
;
1134 if (use_c1_residency_msr
) {
1136 * Some models have a dedicated C1 residency MSR,
1137 * which should be more accurate than the derivation below.
1141 * As counter collection is not atomic,
1142 * it is possible for mperf's non-halted cycles + idle states
1143 * to exceed TSC's all cycles: show c1 = 0% in that case.
1145 if ((old
->mperf
+ core_delta
->c3
+ core_delta
->c6
+ core_delta
->c7
) > (old
->tsc
* tsc_tweak
))
1148 /* normal case, derive c1 */
1149 old
->c1
= (old
->tsc
* tsc_tweak
) - old
->mperf
- core_delta
->c3
1150 - core_delta
->c6
- core_delta
->c7
;
1154 if (old
->mperf
== 0) {
1156 fprintf(outf
, "cpu%d MPERF 0!\n", old
->cpu_id
);
1157 old
->mperf
= 1; /* divide by 0 protection */
1160 if (DO_BIC(BIC_IRQ
))
1161 old
->irq_count
= new->irq_count
- old
->irq_count
;
1163 if (DO_BIC(BIC_SMI
))
1164 old
->smi_count
= new->smi_count
- old
->smi_count
;
1166 for (i
= 0, mp
= sys
.tp
; mp
; i
++, mp
= mp
->next
) {
1167 if (mp
->format
== FORMAT_RAW
)
1168 old
->counter
[i
] = new->counter
[i
];
1170 old
->counter
[i
] = new->counter
[i
] - old
->counter
[i
];
1175 int delta_cpu(struct thread_data
*t
, struct core_data
*c
,
1176 struct pkg_data
*p
, struct thread_data
*t2
,
1177 struct core_data
*c2
, struct pkg_data
*p2
)
1181 /* calculate core delta only for 1st thread in core */
1182 if (t
->flags
& CPU_IS_FIRST_THREAD_IN_CORE
)
1185 /* always calculate thread delta */
1186 retval
= delta_thread(t
, t2
, c2
); /* c2 is core delta */
1190 /* calculate package delta only for 1st core in package */
1191 if (t
->flags
& CPU_IS_FIRST_CORE_IN_PACKAGE
)
1192 retval
= delta_package(p
, p2
);
1197 void clear_counters(struct thread_data
*t
, struct core_data
*c
, struct pkg_data
*p
)
1200 struct msr_counter
*mp
;
1210 /* tells format_counters to dump all fields from this set */
1211 t
->flags
= CPU_IS_FIRST_THREAD_IN_CORE
| CPU_IS_FIRST_CORE_IN_PACKAGE
;
1219 p
->pkg_wtd_core_c0
= 0;
1220 p
->pkg_any_core_c0
= 0;
1221 p
->pkg_any_gfxe_c0
= 0;
1222 p
->pkg_both_core_gfxe_c0
= 0;
1225 if (DO_BIC(BIC_Pkgpc3
))
1227 if (DO_BIC(BIC_Pkgpc6
))
1229 if (DO_BIC(BIC_Pkgpc7
))
1237 p
->energy_cores
= 0;
1239 p
->rapl_pkg_perf_status
= 0;
1240 p
->rapl_dram_perf_status
= 0;
1245 for (i
= 0, mp
= sys
.tp
; mp
; i
++, mp
= mp
->next
)
1248 for (i
= 0, mp
= sys
.cp
; mp
; i
++, mp
= mp
->next
)
1251 for (i
= 0, mp
= sys
.pp
; mp
; i
++, mp
= mp
->next
)
1254 int sum_counters(struct thread_data
*t
, struct core_data
*c
,
1258 struct msr_counter
*mp
;
1260 average
.threads
.tsc
+= t
->tsc
;
1261 average
.threads
.aperf
+= t
->aperf
;
1262 average
.threads
.mperf
+= t
->mperf
;
1263 average
.threads
.c1
+= t
->c1
;
1265 average
.threads
.irq_count
+= t
->irq_count
;
1266 average
.threads
.smi_count
+= t
->smi_count
;
1268 for (i
= 0, mp
= sys
.tp
; mp
; i
++, mp
= mp
->next
) {
1269 if (mp
->format
== FORMAT_RAW
)
1271 average
.threads
.counter
[i
] += t
->counter
[i
];
1274 /* sum per-core values only for 1st thread in core */
1275 if (!(t
->flags
& CPU_IS_FIRST_THREAD_IN_CORE
))
1278 average
.cores
.c3
+= c
->c3
;
1279 average
.cores
.c6
+= c
->c6
;
1280 average
.cores
.c7
+= c
->c7
;
1281 average
.cores
.mc6_us
+= c
->mc6_us
;
1283 average
.cores
.core_temp_c
= MAX(average
.cores
.core_temp_c
, c
->core_temp_c
);
1285 for (i
= 0, mp
= sys
.cp
; mp
; i
++, mp
= mp
->next
) {
1286 if (mp
->format
== FORMAT_RAW
)
1288 average
.cores
.counter
[i
] += c
->counter
[i
];
1291 /* sum per-pkg values only for 1st core in pkg */
1292 if (!(t
->flags
& CPU_IS_FIRST_CORE_IN_PACKAGE
))
1295 if (do_skl_residency
) {
1296 average
.packages
.pkg_wtd_core_c0
+= p
->pkg_wtd_core_c0
;
1297 average
.packages
.pkg_any_core_c0
+= p
->pkg_any_core_c0
;
1298 average
.packages
.pkg_any_gfxe_c0
+= p
->pkg_any_gfxe_c0
;
1299 average
.packages
.pkg_both_core_gfxe_c0
+= p
->pkg_both_core_gfxe_c0
;
1302 average
.packages
.pc2
+= p
->pc2
;
1303 if (DO_BIC(BIC_Pkgpc3
))
1304 average
.packages
.pc3
+= p
->pc3
;
1305 if (DO_BIC(BIC_Pkgpc6
))
1306 average
.packages
.pc6
+= p
->pc6
;
1307 if (DO_BIC(BIC_Pkgpc7
))
1308 average
.packages
.pc7
+= p
->pc7
;
1309 average
.packages
.pc8
+= p
->pc8
;
1310 average
.packages
.pc9
+= p
->pc9
;
1311 average
.packages
.pc10
+= p
->pc10
;
1313 average
.packages
.energy_pkg
+= p
->energy_pkg
;
1314 average
.packages
.energy_dram
+= p
->energy_dram
;
1315 average
.packages
.energy_cores
+= p
->energy_cores
;
1316 average
.packages
.energy_gfx
+= p
->energy_gfx
;
1318 average
.packages
.gfx_rc6_ms
= p
->gfx_rc6_ms
;
1319 average
.packages
.gfx_mhz
= p
->gfx_mhz
;
1321 average
.packages
.pkg_temp_c
= MAX(average
.packages
.pkg_temp_c
, p
->pkg_temp_c
);
1323 average
.packages
.rapl_pkg_perf_status
+= p
->rapl_pkg_perf_status
;
1324 average
.packages
.rapl_dram_perf_status
+= p
->rapl_dram_perf_status
;
1326 for (i
= 0, mp
= sys
.pp
; mp
; i
++, mp
= mp
->next
) {
1327 if (mp
->format
== FORMAT_RAW
)
1329 average
.packages
.counter
[i
] += p
->counter
[i
];
1334 * sum the counters for all cpus in the system
1335 * compute the weighted average
1337 void compute_average(struct thread_data
*t
, struct core_data
*c
,
1341 struct msr_counter
*mp
;
1343 clear_counters(&average
.threads
, &average
.cores
, &average
.packages
);
1345 for_all_cpus(sum_counters
, t
, c
, p
);
1347 average
.threads
.tsc
/= topo
.num_cpus
;
1348 average
.threads
.aperf
/= topo
.num_cpus
;
1349 average
.threads
.mperf
/= topo
.num_cpus
;
1350 average
.threads
.c1
/= topo
.num_cpus
;
1352 if (average
.threads
.irq_count
> 9999999)
1353 sums_need_wide_columns
= 1;
1355 average
.cores
.c3
/= topo
.num_cores
;
1356 average
.cores
.c6
/= topo
.num_cores
;
1357 average
.cores
.c7
/= topo
.num_cores
;
1358 average
.cores
.mc6_us
/= topo
.num_cores
;
1360 if (do_skl_residency
) {
1361 average
.packages
.pkg_wtd_core_c0
/= topo
.num_packages
;
1362 average
.packages
.pkg_any_core_c0
/= topo
.num_packages
;
1363 average
.packages
.pkg_any_gfxe_c0
/= topo
.num_packages
;
1364 average
.packages
.pkg_both_core_gfxe_c0
/= topo
.num_packages
;
1367 average
.packages
.pc2
/= topo
.num_packages
;
1368 if (DO_BIC(BIC_Pkgpc3
))
1369 average
.packages
.pc3
/= topo
.num_packages
;
1370 if (DO_BIC(BIC_Pkgpc6
))
1371 average
.packages
.pc6
/= topo
.num_packages
;
1372 if (DO_BIC(BIC_Pkgpc7
))
1373 average
.packages
.pc7
/= topo
.num_packages
;
1375 average
.packages
.pc8
/= topo
.num_packages
;
1376 average
.packages
.pc9
/= topo
.num_packages
;
1377 average
.packages
.pc10
/= topo
.num_packages
;
1379 for (i
= 0, mp
= sys
.tp
; mp
; i
++, mp
= mp
->next
) {
1380 if (mp
->format
== FORMAT_RAW
)
1382 if (mp
->type
== COUNTER_ITEMS
) {
1383 if (average
.threads
.counter
[i
] > 9999999)
1384 sums_need_wide_columns
= 1;
1387 average
.threads
.counter
[i
] /= topo
.num_cpus
;
1389 for (i
= 0, mp
= sys
.cp
; mp
; i
++, mp
= mp
->next
) {
1390 if (mp
->format
== FORMAT_RAW
)
1392 if (mp
->type
== COUNTER_ITEMS
) {
1393 if (average
.cores
.counter
[i
] > 9999999)
1394 sums_need_wide_columns
= 1;
1396 average
.cores
.counter
[i
] /= topo
.num_cores
;
1398 for (i
= 0, mp
= sys
.pp
; mp
; i
++, mp
= mp
->next
) {
1399 if (mp
->format
== FORMAT_RAW
)
1401 if (mp
->type
== COUNTER_ITEMS
) {
1402 if (average
.packages
.counter
[i
] > 9999999)
1403 sums_need_wide_columns
= 1;
1405 average
.packages
.counter
[i
] /= topo
.num_packages
;
1409 static unsigned long long rdtsc(void)
1411 unsigned int low
, high
;
1413 asm volatile("rdtsc" : "=a" (low
), "=d" (high
));
1415 return low
| ((unsigned long long)high
) << 32;
1419 * Open a file, and exit on failure
1421 FILE *fopen_or_die(const char *path
, const char *mode
)
1423 FILE *filep
= fopen(path
, mode
);
1426 err(1, "%s: open failed", path
);
1430 * snapshot_sysfs_counter()
1432 * return snapshot of given counter
1434 unsigned long long snapshot_sysfs_counter(char *path
)
1438 unsigned long long counter
;
1440 fp
= fopen_or_die(path
, "r");
1442 retval
= fscanf(fp
, "%lld", &counter
);
1444 err(1, "snapshot_sysfs_counter(%s)", path
);
1451 int get_mp(int cpu
, struct msr_counter
*mp
, unsigned long long *counterp
)
1453 if (mp
->msr_num
!= 0) {
1454 if (get_msr(cpu
, mp
->msr_num
, counterp
))
1459 if (mp
->flags
& SYSFS_PERCPU
) {
1460 sprintf(path
, "/sys/devices/system/cpu/cpu%d/%s",
1463 *counterp
= snapshot_sysfs_counter(path
);
1465 *counterp
= snapshot_sysfs_counter(mp
->path
);
1475 * acquire and record local counters for that cpu
1477 int get_counters(struct thread_data
*t
, struct core_data
*c
, struct pkg_data
*p
)
1479 int cpu
= t
->cpu_id
;
1480 unsigned long long msr
;
1481 int aperf_mperf_retry_count
= 0;
1482 struct msr_counter
*mp
;
1485 if (cpu_migrate(cpu
)) {
1486 fprintf(outf
, "Could not migrate to CPU %d\n", cpu
);
1491 t
->tsc
= rdtsc(); /* we are running on local CPU of interest */
1493 if (DO_BIC(BIC_Avg_MHz
) || DO_BIC(BIC_Busy
) || DO_BIC(BIC_Bzy_MHz
)) {
1494 unsigned long long tsc_before
, tsc_between
, tsc_after
, aperf_time
, mperf_time
;
1497 * The TSC, APERF and MPERF must be read together for
1498 * APERF/MPERF and MPERF/TSC to give accurate results.
1500 * Unfortunately, APERF and MPERF are read by
1501 * individual system call, so delays may occur
1502 * between them. If the time to read them
1503 * varies by a large amount, we re-read them.
1507 * This initial dummy APERF read has been seen to
1508 * reduce jitter in the subsequent reads.
1511 if (get_msr(cpu
, MSR_IA32_APERF
, &t
->aperf
))
1514 t
->tsc
= rdtsc(); /* re-read close to APERF */
1516 tsc_before
= t
->tsc
;
1518 if (get_msr(cpu
, MSR_IA32_APERF
, &t
->aperf
))
1521 tsc_between
= rdtsc();
1523 if (get_msr(cpu
, MSR_IA32_MPERF
, &t
->mperf
))
1526 tsc_after
= rdtsc();
1528 aperf_time
= tsc_between
- tsc_before
;
1529 mperf_time
= tsc_after
- tsc_between
;
1532 * If the system call latency to read APERF and MPERF
1533 * differ by more than 2x, then try again.
1535 if ((aperf_time
> (2 * mperf_time
)) || (mperf_time
> (2 * aperf_time
))) {
1536 aperf_mperf_retry_count
++;
1537 if (aperf_mperf_retry_count
< 5)
1540 warnx("cpu%d jitter %lld %lld",
1541 cpu
, aperf_time
, mperf_time
);
1543 aperf_mperf_retry_count
= 0;
1545 t
->aperf
= t
->aperf
* aperf_mperf_multiplier
;
1546 t
->mperf
= t
->mperf
* aperf_mperf_multiplier
;
1549 if (DO_BIC(BIC_IRQ
))
1550 t
->irq_count
= irqs_per_cpu
[cpu
];
1551 if (DO_BIC(BIC_SMI
)) {
1552 if (get_msr(cpu
, MSR_SMI_COUNT
, &msr
))
1554 t
->smi_count
= msr
& 0xFFFFFFFF;
1556 if (DO_BIC(BIC_CPU_c1
) && use_c1_residency_msr
) {
1557 if (get_msr(cpu
, MSR_CORE_C1_RES
, &t
->c1
))
1561 for (i
= 0, mp
= sys
.tp
; mp
; i
++, mp
= mp
->next
) {
1562 if (get_mp(cpu
, mp
, &t
->counter
[i
]))
1566 /* collect core counters only for 1st thread in core */
1567 if (!(t
->flags
& CPU_IS_FIRST_THREAD_IN_CORE
))
1570 if (DO_BIC(BIC_CPU_c3
) && !do_slm_cstates
&& !do_knl_cstates
) {
1571 if (get_msr(cpu
, MSR_CORE_C3_RESIDENCY
, &c
->c3
))
1575 if (DO_BIC(BIC_CPU_c6
) && !do_knl_cstates
) {
1576 if (get_msr(cpu
, MSR_CORE_C6_RESIDENCY
, &c
->c6
))
1578 } else if (do_knl_cstates
) {
1579 if (get_msr(cpu
, MSR_KNL_CORE_C6_RESIDENCY
, &c
->c6
))
1583 if (DO_BIC(BIC_CPU_c7
))
1584 if (get_msr(cpu
, MSR_CORE_C7_RESIDENCY
, &c
->c7
))
1587 if (DO_BIC(BIC_Mod_c6
))
1588 if (get_msr(cpu
, MSR_MODULE_C6_RES_MS
, &c
->mc6_us
))
1591 if (DO_BIC(BIC_CoreTmp
)) {
1592 if (get_msr(cpu
, MSR_IA32_THERM_STATUS
, &msr
))
1594 c
->core_temp_c
= tcc_activation_temp
- ((msr
>> 16) & 0x7F);
1597 for (i
= 0, mp
= sys
.cp
; mp
; i
++, mp
= mp
->next
) {
1598 if (get_mp(cpu
, mp
, &c
->counter
[i
]))
1602 /* collect package counters only for 1st core in package */
1603 if (!(t
->flags
& CPU_IS_FIRST_CORE_IN_PACKAGE
))
1606 if (do_skl_residency
) {
1607 if (get_msr(cpu
, MSR_PKG_WEIGHTED_CORE_C0_RES
, &p
->pkg_wtd_core_c0
))
1609 if (get_msr(cpu
, MSR_PKG_ANY_CORE_C0_RES
, &p
->pkg_any_core_c0
))
1611 if (get_msr(cpu
, MSR_PKG_ANY_GFXE_C0_RES
, &p
->pkg_any_gfxe_c0
))
1613 if (get_msr(cpu
, MSR_PKG_BOTH_CORE_GFXE_C0_RES
, &p
->pkg_both_core_gfxe_c0
))
1616 if (DO_BIC(BIC_Pkgpc3
))
1617 if (get_msr(cpu
, MSR_PKG_C3_RESIDENCY
, &p
->pc3
))
1619 if (DO_BIC(BIC_Pkgpc6
)) {
1620 if (do_slm_cstates
) {
1621 if (get_msr(cpu
, MSR_ATOM_PKG_C6_RESIDENCY
, &p
->pc6
))
1624 if (get_msr(cpu
, MSR_PKG_C6_RESIDENCY
, &p
->pc6
))
1629 if (DO_BIC(BIC_Pkgpc2
))
1630 if (get_msr(cpu
, MSR_PKG_C2_RESIDENCY
, &p
->pc2
))
1632 if (DO_BIC(BIC_Pkgpc7
))
1633 if (get_msr(cpu
, MSR_PKG_C7_RESIDENCY
, &p
->pc7
))
1635 if (DO_BIC(BIC_Pkgpc8
))
1636 if (get_msr(cpu
, MSR_PKG_C8_RESIDENCY
, &p
->pc8
))
1638 if (DO_BIC(BIC_Pkgpc9
))
1639 if (get_msr(cpu
, MSR_PKG_C9_RESIDENCY
, &p
->pc9
))
1641 if (DO_BIC(BIC_Pkgpc10
))
1642 if (get_msr(cpu
, MSR_PKG_C10_RESIDENCY
, &p
->pc10
))
1645 if (do_rapl
& RAPL_PKG
) {
1646 if (get_msr(cpu
, MSR_PKG_ENERGY_STATUS
, &msr
))
1648 p
->energy_pkg
= msr
& 0xFFFFFFFF;
1650 if (do_rapl
& RAPL_CORES_ENERGY_STATUS
) {
1651 if (get_msr(cpu
, MSR_PP0_ENERGY_STATUS
, &msr
))
1653 p
->energy_cores
= msr
& 0xFFFFFFFF;
1655 if (do_rapl
& RAPL_DRAM
) {
1656 if (get_msr(cpu
, MSR_DRAM_ENERGY_STATUS
, &msr
))
1658 p
->energy_dram
= msr
& 0xFFFFFFFF;
1660 if (do_rapl
& RAPL_GFX
) {
1661 if (get_msr(cpu
, MSR_PP1_ENERGY_STATUS
, &msr
))
1663 p
->energy_gfx
= msr
& 0xFFFFFFFF;
1665 if (do_rapl
& RAPL_PKG_PERF_STATUS
) {
1666 if (get_msr(cpu
, MSR_PKG_PERF_STATUS
, &msr
))
1668 p
->rapl_pkg_perf_status
= msr
& 0xFFFFFFFF;
1670 if (do_rapl
& RAPL_DRAM_PERF_STATUS
) {
1671 if (get_msr(cpu
, MSR_DRAM_PERF_STATUS
, &msr
))
1673 p
->rapl_dram_perf_status
= msr
& 0xFFFFFFFF;
1675 if (DO_BIC(BIC_PkgTmp
)) {
1676 if (get_msr(cpu
, MSR_IA32_PACKAGE_THERM_STATUS
, &msr
))
1678 p
->pkg_temp_c
= tcc_activation_temp
- ((msr
>> 16) & 0x7F);
1681 if (DO_BIC(BIC_GFX_rc6
))
1682 p
->gfx_rc6_ms
= gfx_cur_rc6_ms
;
1684 if (DO_BIC(BIC_GFXMHz
))
1685 p
->gfx_mhz
= gfx_cur_mhz
;
1687 for (i
= 0, mp
= sys
.pp
; mp
; i
++, mp
= mp
->next
) {
1688 if (get_mp(cpu
, mp
, &p
->counter
[i
]))
1696 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit:
1697 * If you change the values, note they are used both in comparisons
1698 * (>= PCL__7) and to index pkg_cstate_limit_strings[].
1701 #define PCLUKN 0 /* Unknown */
1702 #define PCLRSV 1 /* Reserved */
1703 #define PCL__0 2 /* PC0 */
1704 #define PCL__1 3 /* PC1 */
1705 #define PCL__2 4 /* PC2 */
1706 #define PCL__3 5 /* PC3 */
1707 #define PCL__4 6 /* PC4 */
1708 #define PCL__6 7 /* PC6 */
1709 #define PCL_6N 8 /* PC6 No Retention */
1710 #define PCL_6R 9 /* PC6 Retention */
1711 #define PCL__7 10 /* PC7 */
1712 #define PCL_7S 11 /* PC7 Shrink */
1713 #define PCL__8 12 /* PC8 */
1714 #define PCL__9 13 /* PC9 */
1715 #define PCLUNL 14 /* Unlimited */
1717 int pkg_cstate_limit
= PCLUKN
;
1718 char *pkg_cstate_limit_strings
[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
1719 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"};
1721 int nhm_pkg_cstate_limits
[16] = {PCL__0
, PCL__1
, PCL__3
, PCL__6
, PCL__7
, PCLRSV
, PCLRSV
, PCLUNL
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
};
1722 int snb_pkg_cstate_limits
[16] = {PCL__0
, PCL__2
, PCL_6N
, PCL_6R
, PCL__7
, PCL_7S
, PCLRSV
, PCLUNL
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
};
1723 int hsw_pkg_cstate_limits
[16] = {PCL__0
, PCL__2
, PCL__3
, PCL__6
, PCL__7
, PCL_7S
, PCL__8
, PCL__9
, PCLUNL
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
};
1724 int slv_pkg_cstate_limits
[16] = {PCL__0
, PCL__1
, PCLRSV
, PCLRSV
, PCL__4
, PCLRSV
, PCL__6
, PCL__7
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCL__6
, PCL__7
};
1725 int amt_pkg_cstate_limits
[16] = {PCLUNL
, PCL__1
, PCL__2
, PCLRSV
, PCLRSV
, PCLRSV
, PCL__6
, PCL__7
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
};
1726 int phi_pkg_cstate_limits
[16] = {PCL__0
, PCL__2
, PCL_6N
, PCL_6R
, PCLRSV
, PCLRSV
, PCLRSV
, PCLUNL
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
};
1727 int bxt_pkg_cstate_limits
[16] = {PCL__0
, PCL__2
, PCLUNL
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
};
1728 int skx_pkg_cstate_limits
[16] = {PCL__0
, PCL__2
, PCL_6N
, PCL_6R
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLUNL
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
, PCLRSV
};
1732 calculate_tsc_tweak()
1734 tsc_tweak
= base_hz
/ tsc_hz
;
1738 dump_nhm_platform_info(void)
1740 unsigned long long msr
;
1743 get_msr(base_cpu
, MSR_PLATFORM_INFO
, &msr
);
1745 fprintf(outf
, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu
, msr
);
1747 ratio
= (msr
>> 40) & 0xFF;
1748 fprintf(outf
, "%d * %.1f = %.1f MHz max efficiency frequency\n",
1749 ratio
, bclk
, ratio
* bclk
);
1751 ratio
= (msr
>> 8) & 0xFF;
1752 fprintf(outf
, "%d * %.1f = %.1f MHz base frequency\n",
1753 ratio
, bclk
, ratio
* bclk
);
1755 get_msr(base_cpu
, MSR_IA32_POWER_CTL
, &msr
);
1756 fprintf(outf
, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
1757 base_cpu
, msr
, msr
& 0x2 ? "EN" : "DIS");
1763 dump_hsw_turbo_ratio_limits(void)
1765 unsigned long long msr
;
1768 get_msr(base_cpu
, MSR_TURBO_RATIO_LIMIT2
, &msr
);
1770 fprintf(outf
, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu
, msr
);
1772 ratio
= (msr
>> 8) & 0xFF;
1774 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo 18 active cores\n",
1775 ratio
, bclk
, ratio
* bclk
);
1777 ratio
= (msr
>> 0) & 0xFF;
1779 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo 17 active cores\n",
1780 ratio
, bclk
, ratio
* bclk
);
1785 dump_ivt_turbo_ratio_limits(void)
1787 unsigned long long msr
;
1790 get_msr(base_cpu
, MSR_TURBO_RATIO_LIMIT1
, &msr
);
1792 fprintf(outf
, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu
, msr
);
1794 ratio
= (msr
>> 56) & 0xFF;
1796 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo 16 active cores\n",
1797 ratio
, bclk
, ratio
* bclk
);
1799 ratio
= (msr
>> 48) & 0xFF;
1801 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo 15 active cores\n",
1802 ratio
, bclk
, ratio
* bclk
);
1804 ratio
= (msr
>> 40) & 0xFF;
1806 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo 14 active cores\n",
1807 ratio
, bclk
, ratio
* bclk
);
1809 ratio
= (msr
>> 32) & 0xFF;
1811 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo 13 active cores\n",
1812 ratio
, bclk
, ratio
* bclk
);
1814 ratio
= (msr
>> 24) & 0xFF;
1816 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo 12 active cores\n",
1817 ratio
, bclk
, ratio
* bclk
);
1819 ratio
= (msr
>> 16) & 0xFF;
1821 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo 11 active cores\n",
1822 ratio
, bclk
, ratio
* bclk
);
1824 ratio
= (msr
>> 8) & 0xFF;
1826 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo 10 active cores\n",
1827 ratio
, bclk
, ratio
* bclk
);
1829 ratio
= (msr
>> 0) & 0xFF;
1831 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo 9 active cores\n",
1832 ratio
, bclk
, ratio
* bclk
);
1835 int has_turbo_ratio_group_limits(int family
, int model
)
1842 case INTEL_FAM6_ATOM_GOLDMONT
:
1843 case INTEL_FAM6_SKYLAKE_X
:
1844 case INTEL_FAM6_ATOM_DENVERTON
:
1851 dump_turbo_ratio_limits(int family
, int model
)
1853 unsigned long long msr
, core_counts
;
1854 unsigned int ratio
, group_size
;
1856 get_msr(base_cpu
, MSR_TURBO_RATIO_LIMIT
, &msr
);
1857 fprintf(outf
, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu
, msr
);
1859 if (has_turbo_ratio_group_limits(family
, model
)) {
1860 get_msr(base_cpu
, MSR_TURBO_RATIO_LIMIT1
, &core_counts
);
1861 fprintf(outf
, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu
, core_counts
);
1863 core_counts
= 0x0807060504030201;
1866 ratio
= (msr
>> 56) & 0xFF;
1867 group_size
= (core_counts
>> 56) & 0xFF;
1869 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1870 ratio
, bclk
, ratio
* bclk
, group_size
);
1872 ratio
= (msr
>> 48) & 0xFF;
1873 group_size
= (core_counts
>> 48) & 0xFF;
1875 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1876 ratio
, bclk
, ratio
* bclk
, group_size
);
1878 ratio
= (msr
>> 40) & 0xFF;
1879 group_size
= (core_counts
>> 40) & 0xFF;
1881 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1882 ratio
, bclk
, ratio
* bclk
, group_size
);
1884 ratio
= (msr
>> 32) & 0xFF;
1885 group_size
= (core_counts
>> 32) & 0xFF;
1887 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1888 ratio
, bclk
, ratio
* bclk
, group_size
);
1890 ratio
= (msr
>> 24) & 0xFF;
1891 group_size
= (core_counts
>> 24) & 0xFF;
1893 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1894 ratio
, bclk
, ratio
* bclk
, group_size
);
1896 ratio
= (msr
>> 16) & 0xFF;
1897 group_size
= (core_counts
>> 16) & 0xFF;
1899 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1900 ratio
, bclk
, ratio
* bclk
, group_size
);
1902 ratio
= (msr
>> 8) & 0xFF;
1903 group_size
= (core_counts
>> 8) & 0xFF;
1905 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1906 ratio
, bclk
, ratio
* bclk
, group_size
);
1908 ratio
= (msr
>> 0) & 0xFF;
1909 group_size
= (core_counts
>> 0) & 0xFF;
1911 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
1912 ratio
, bclk
, ratio
* bclk
, group_size
);
1917 dump_atom_turbo_ratio_limits(void)
1919 unsigned long long msr
;
1922 get_msr(base_cpu
, MSR_ATOM_CORE_RATIOS
, &msr
);
1923 fprintf(outf
, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu
, msr
& 0xFFFFFFFF);
1925 ratio
= (msr
>> 0) & 0x3F;
1927 fprintf(outf
, "%d * %.1f = %.1f MHz minimum operating frequency\n",
1928 ratio
, bclk
, ratio
* bclk
);
1930 ratio
= (msr
>> 8) & 0x3F;
1932 fprintf(outf
, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n",
1933 ratio
, bclk
, ratio
* bclk
);
1935 ratio
= (msr
>> 16) & 0x3F;
1937 fprintf(outf
, "%d * %.1f = %.1f MHz base frequency\n",
1938 ratio
, bclk
, ratio
* bclk
);
1940 get_msr(base_cpu
, MSR_ATOM_CORE_TURBO_RATIOS
, &msr
);
1941 fprintf(outf
, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu
, msr
& 0xFFFFFFFF);
1943 ratio
= (msr
>> 24) & 0x3F;
1945 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo 4 active cores\n",
1946 ratio
, bclk
, ratio
* bclk
);
1948 ratio
= (msr
>> 16) & 0x3F;
1950 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo 3 active cores\n",
1951 ratio
, bclk
, ratio
* bclk
);
1953 ratio
= (msr
>> 8) & 0x3F;
1955 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo 2 active cores\n",
1956 ratio
, bclk
, ratio
* bclk
);
1958 ratio
= (msr
>> 0) & 0x3F;
1960 fprintf(outf
, "%d * %.1f = %.1f MHz max turbo 1 active core\n",
1961 ratio
, bclk
, ratio
* bclk
);
1965 dump_knl_turbo_ratio_limits(void)
1967 const unsigned int buckets_no
= 7;
1969 unsigned long long msr
;
1970 int delta_cores
, delta_ratio
;
1972 unsigned int cores
[buckets_no
];
1973 unsigned int ratio
[buckets_no
];
1975 get_msr(base_cpu
, MSR_TURBO_RATIO_LIMIT
, &msr
);
1977 fprintf(outf
, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n",
1981 * Turbo encoding in KNL is as follows:
1983 * [7:1] -- Base value of number of active cores of bucket 1.
1984 * [15:8] -- Base value of freq ratio of bucket 1.
1985 * [20:16] -- +ve delta of number of active cores of bucket 2.
1986 * i.e. active cores of bucket 2 =
1987 * active cores of bucket 1 + delta
1988 * [23:21] -- Negative delta of freq ratio of bucket 2.
1989 * i.e. freq ratio of bucket 2 =
1990 * freq ratio of bucket 1 - delta
1991 * [28:24]-- +ve delta of number of active cores of bucket 3.
1992 * [31:29]-- -ve delta of freq ratio of bucket 3.
1993 * [36:32]-- +ve delta of number of active cores of bucket 4.
1994 * [39:37]-- -ve delta of freq ratio of bucket 4.
1995 * [44:40]-- +ve delta of number of active cores of bucket 5.
1996 * [47:45]-- -ve delta of freq ratio of bucket 5.
1997 * [52:48]-- +ve delta of number of active cores of bucket 6.
1998 * [55:53]-- -ve delta of freq ratio of bucket 6.
1999 * [60:56]-- +ve delta of number of active cores of bucket 7.
2000 * [63:61]-- -ve delta of freq ratio of bucket 7.
2004 cores
[b_nr
] = (msr
& 0xFF) >> 1;
2005 ratio
[b_nr
] = (msr
>> 8) & 0xFF;
2007 for (i
= 16; i
< 64; i
+= 8) {
2008 delta_cores
= (msr
>> i
) & 0x1F;
2009 delta_ratio
= (msr
>> (i
+ 5)) & 0x7;
2011 cores
[b_nr
+ 1] = cores
[b_nr
] + delta_cores
;
2012 ratio
[b_nr
+ 1] = ratio
[b_nr
] - delta_ratio
;
2016 for (i
= buckets_no
- 1; i
>= 0; i
--)
2017 if (i
> 0 ? ratio
[i
] != ratio
[i
- 1] : 1)
2019 "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2020 ratio
[i
], bclk
, ratio
[i
] * bclk
, cores
[i
]);
2024 dump_nhm_cst_cfg(void)
2026 unsigned long long msr
;
2028 get_msr(base_cpu
, MSR_PKG_CST_CONFIG_CONTROL
, &msr
);
2030 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
2031 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
2033 fprintf(outf
, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu
, msr
);
2035 fprintf(outf
, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n",
2036 (msr
& SNB_C3_AUTO_UNDEMOTE
) ? "UNdemote-C3, " : "",
2037 (msr
& SNB_C1_AUTO_UNDEMOTE
) ? "UNdemote-C1, " : "",
2038 (msr
& NHM_C3_AUTO_DEMOTE
) ? "demote-C3, " : "",
2039 (msr
& NHM_C1_AUTO_DEMOTE
) ? "demote-C1, " : "",
2040 (msr
& (1 << 15)) ? "" : "UN",
2041 (unsigned int)msr
& 0xF,
2042 pkg_cstate_limit_strings
[pkg_cstate_limit
]);
2047 dump_config_tdp(void)
2049 unsigned long long msr
;
2051 get_msr(base_cpu
, MSR_CONFIG_TDP_NOMINAL
, &msr
);
2052 fprintf(outf
, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu
, msr
);
2053 fprintf(outf
, " (base_ratio=%d)\n", (unsigned int)msr
& 0xFF);
2055 get_msr(base_cpu
, MSR_CONFIG_TDP_LEVEL_1
, &msr
);
2056 fprintf(outf
, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu
, msr
);
2058 fprintf(outf
, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr
>> 48) & 0x7FFF);
2059 fprintf(outf
, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr
>> 32) & 0x7FFF);
2060 fprintf(outf
, "LVL1_RATIO=%d ", (unsigned int)(msr
>> 16) & 0xFF);
2061 fprintf(outf
, "PKG_TDP_LVL1=%d", (unsigned int)(msr
) & 0x7FFF);
2063 fprintf(outf
, ")\n");
2065 get_msr(base_cpu
, MSR_CONFIG_TDP_LEVEL_2
, &msr
);
2066 fprintf(outf
, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu
, msr
);
2068 fprintf(outf
, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr
>> 48) & 0x7FFF);
2069 fprintf(outf
, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr
>> 32) & 0x7FFF);
2070 fprintf(outf
, "LVL2_RATIO=%d ", (unsigned int)(msr
>> 16) & 0xFF);
2071 fprintf(outf
, "PKG_TDP_LVL2=%d", (unsigned int)(msr
) & 0x7FFF);
2073 fprintf(outf
, ")\n");
2075 get_msr(base_cpu
, MSR_CONFIG_TDP_CONTROL
, &msr
);
2076 fprintf(outf
, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu
, msr
);
2078 fprintf(outf
, "TDP_LEVEL=%d ", (unsigned int)(msr
) & 0x3);
2079 fprintf(outf
, " lock=%d", (unsigned int)(msr
>> 31) & 1);
2080 fprintf(outf
, ")\n");
2082 get_msr(base_cpu
, MSR_TURBO_ACTIVATION_RATIO
, &msr
);
2083 fprintf(outf
, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu
, msr
);
2084 fprintf(outf
, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr
) & 0xFF);
2085 fprintf(outf
, " lock=%d", (unsigned int)(msr
>> 31) & 1);
2086 fprintf(outf
, ")\n");
2089 unsigned int irtl_time_units
[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
2091 void print_irtl(void)
2093 unsigned long long msr
;
2095 get_msr(base_cpu
, MSR_PKGC3_IRTL
, &msr
);
2096 fprintf(outf
, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu
, msr
);
2097 fprintf(outf
, "%svalid, %lld ns)\n", msr
& (1 << 15) ? "" : "NOT",
2098 (msr
& 0x3FF) * irtl_time_units
[(msr
>> 10) & 0x3]);
2100 get_msr(base_cpu
, MSR_PKGC6_IRTL
, &msr
);
2101 fprintf(outf
, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu
, msr
);
2102 fprintf(outf
, "%svalid, %lld ns)\n", msr
& (1 << 15) ? "" : "NOT",
2103 (msr
& 0x3FF) * irtl_time_units
[(msr
>> 10) & 0x3]);
2105 get_msr(base_cpu
, MSR_PKGC7_IRTL
, &msr
);
2106 fprintf(outf
, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu
, msr
);
2107 fprintf(outf
, "%svalid, %lld ns)\n", msr
& (1 << 15) ? "" : "NOT",
2108 (msr
& 0x3FF) * irtl_time_units
[(msr
>> 10) & 0x3]);
2113 get_msr(base_cpu
, MSR_PKGC8_IRTL
, &msr
);
2114 fprintf(outf
, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu
, msr
);
2115 fprintf(outf
, "%svalid, %lld ns)\n", msr
& (1 << 15) ? "" : "NOT",
2116 (msr
& 0x3FF) * irtl_time_units
[(msr
>> 10) & 0x3]);
2118 get_msr(base_cpu
, MSR_PKGC9_IRTL
, &msr
);
2119 fprintf(outf
, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu
, msr
);
2120 fprintf(outf
, "%svalid, %lld ns)\n", msr
& (1 << 15) ? "" : "NOT",
2121 (msr
& 0x3FF) * irtl_time_units
[(msr
>> 10) & 0x3]);
2123 get_msr(base_cpu
, MSR_PKGC10_IRTL
, &msr
);
2124 fprintf(outf
, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu
, msr
);
2125 fprintf(outf
, "%svalid, %lld ns)\n", msr
& (1 << 15) ? "" : "NOT",
2126 (msr
& 0x3FF) * irtl_time_units
[(msr
>> 10) & 0x3]);
2129 void free_fd_percpu(void)
2133 for (i
= 0; i
< topo
.max_cpu_num
+ 1; ++i
) {
2134 if (fd_percpu
[i
] != 0)
2135 close(fd_percpu
[i
]);
2141 void free_all_buffers(void)
2143 CPU_FREE(cpu_present_set
);
2144 cpu_present_set
= NULL
;
2145 cpu_present_setsize
= 0;
2147 CPU_FREE(cpu_affinity_set
);
2148 cpu_affinity_set
= NULL
;
2149 cpu_affinity_setsize
= 0;
2157 package_even
= NULL
;
2167 free(output_buffer
);
2168 output_buffer
= NULL
;
2173 free(irq_column_2_cpu
);
2179 * Parse a file containing a single int.
2181 int parse_int_file(const char *fmt
, ...)
2184 char path
[PATH_MAX
];
2188 va_start(args
, fmt
);
2189 vsnprintf(path
, sizeof(path
), fmt
, args
);
2191 filep
= fopen_or_die(path
, "r");
2192 if (fscanf(filep
, "%d", &value
) != 1)
2193 err(1, "%s: failed to parse number from file", path
);
2199 * get_cpu_position_in_core(cpu)
2200 * return the position of the CPU among its HT siblings in the core
2201 * return -1 if the sibling is not in list
2203 int get_cpu_position_in_core(int cpu
)
2212 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list",
2214 filep
= fopen(path
, "r");
2215 if (filep
== NULL
) {
2220 for (i
= 0; i
< topo
.num_threads_per_core
; i
++) {
2221 fscanf(filep
, "%d", &this_cpu
);
2222 if (this_cpu
== cpu
) {
2227 /* Account for no separator after last thread*/
2228 if (i
!= (topo
.num_threads_per_core
- 1))
2229 fscanf(filep
, "%c", &character
);
2237 * cpu_is_first_core_in_package(cpu)
2238 * return 1 if given CPU is 1st core in package
2240 int cpu_is_first_core_in_package(int cpu
)
2242 return cpu
== parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu
);
2245 int get_physical_package_id(int cpu
)
2247 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu
);
2250 int get_core_id(int cpu
)
2252 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu
);
2255 int get_num_ht_siblings(int cpu
)
2265 sprintf(path
, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu
);
2266 filep
= fopen_or_die(path
, "r");
2270 * A ',' separated or '-' separated set of numbers
2271 * (eg 1-2 or 1,3,4,5)
2273 fscanf(filep
, "%d%c\n", &sib1
, &character
);
2274 fseek(filep
, 0, SEEK_SET
);
2275 fgets(str
, 100, filep
);
2276 ch
= strchr(str
, character
);
2277 while (ch
!= NULL
) {
2279 ch
= strchr(ch
+1, character
);
2287 * run func(thread, core, package) in topology order
2288 * skip non-present cpus
2291 int for_all_cpus_2(int (func
)(struct thread_data
*, struct core_data
*,
2292 struct pkg_data
*, struct thread_data
*, struct core_data
*,
2293 struct pkg_data
*), struct thread_data
*thread_base
,
2294 struct core_data
*core_base
, struct pkg_data
*pkg_base
,
2295 struct thread_data
*thread_base2
, struct core_data
*core_base2
,
2296 struct pkg_data
*pkg_base2
)
2298 int retval
, pkg_no
, core_no
, thread_no
;
2300 for (pkg_no
= 0; pkg_no
< topo
.num_packages
; ++pkg_no
) {
2301 for (core_no
= 0; core_no
< topo
.num_cores_per_pkg
; ++core_no
) {
2302 for (thread_no
= 0; thread_no
<
2303 topo
.num_threads_per_core
; ++thread_no
) {
2304 struct thread_data
*t
, *t2
;
2305 struct core_data
*c
, *c2
;
2306 struct pkg_data
*p
, *p2
;
2308 t
= GET_THREAD(thread_base
, thread_no
, core_no
, pkg_no
);
2310 if (cpu_is_not_present(t
->cpu_id
))
2313 t2
= GET_THREAD(thread_base2
, thread_no
, core_no
, pkg_no
);
2315 c
= GET_CORE(core_base
, core_no
, pkg_no
);
2316 c2
= GET_CORE(core_base2
, core_no
, pkg_no
);
2318 p
= GET_PKG(pkg_base
, pkg_no
);
2319 p2
= GET_PKG(pkg_base2
, pkg_no
);
2321 retval
= func(t
, c
, p
, t2
, c2
, p2
);
2331 * run func(cpu) on every cpu in /proc/stat
2332 * return max_cpu number
2334 int for_all_proc_cpus(int (func
)(int))
2340 fp
= fopen_or_die(proc_stat
, "r");
2342 retval
= fscanf(fp
, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
2344 err(1, "%s: failed to parse format", proc_stat
);
2347 retval
= fscanf(fp
, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num
);
2351 retval
= func(cpu_num
);
2361 void re_initialize(void)
2364 setup_all_buffers();
2365 printf("turbostat: re-initialized with num_cpus %d\n", topo
.num_cpus
);
2371 * remember the last one seen, it will be the max
2373 int count_cpus(int cpu
)
2375 if (topo
.max_cpu_num
< cpu
)
2376 topo
.max_cpu_num
= cpu
;
2381 int mark_cpu_present(int cpu
)
2383 CPU_SET_S(cpu
, cpu_present_setsize
, cpu_present_set
);
2388 * snapshot_proc_interrupts()
2390 * read and record summary of /proc/interrupts
2392 * return 1 if config change requires a restart, else return 0
2394 int snapshot_proc_interrupts(void)
2400 fp
= fopen_or_die("/proc/interrupts", "r");
2404 /* read 1st line of /proc/interrupts to get cpu* name for each column */
2405 for (column
= 0; column
< topo
.num_cpus
; ++column
) {
2408 retval
= fscanf(fp
, " CPU%d", &cpu_number
);
2412 if (cpu_number
> topo
.max_cpu_num
) {
2413 warn("/proc/interrupts: cpu%d: > %d", cpu_number
, topo
.max_cpu_num
);
2417 irq_column_2_cpu
[column
] = cpu_number
;
2418 irqs_per_cpu
[cpu_number
] = 0;
2421 /* read /proc/interrupt count lines and sum up irqs per cpu */
2426 retval
= fscanf(fp
, " %s:", buf
); /* flush irq# "N:" */
2430 /* read the count per cpu */
2431 for (column
= 0; column
< topo
.num_cpus
; ++column
) {
2433 int cpu_number
, irq_count
;
2435 retval
= fscanf(fp
, " %d", &irq_count
);
2439 cpu_number
= irq_column_2_cpu
[column
];
2440 irqs_per_cpu
[cpu_number
] += irq_count
;
2444 while (getc(fp
) != '\n')
2445 ; /* flush interrupt description */
2451 * snapshot_gfx_rc6_ms()
2453 * record snapshot of
2454 * /sys/class/drm/card0/power/rc6_residency_ms
2456 * return 1 if config change requires a restart, else return 0
2458 int snapshot_gfx_rc6_ms(void)
2463 fp
= fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r");
2465 retval
= fscanf(fp
, "%lld", &gfx_cur_rc6_ms
);
2474 * snapshot_gfx_mhz()
2476 * record snapshot of
2477 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz
2479 * return 1 if config change requires a restart, else return 0
2481 int snapshot_gfx_mhz(void)
2487 fp
= fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r");
2493 retval
= fscanf(fp
, "%d", &gfx_cur_mhz
);
2501 * snapshot /proc and /sys files
2503 * return 1 if configuration restart needed, else return 0
2505 int snapshot_proc_sysfs_files(void)
2507 if (DO_BIC(BIC_IRQ
))
2508 if (snapshot_proc_interrupts())
2511 if (DO_BIC(BIC_GFX_rc6
))
2512 snapshot_gfx_rc6_ms();
2514 if (DO_BIC(BIC_GFXMHz
))
2520 void turbostat_loop()
2528 snapshot_proc_sysfs_files();
2529 retval
= for_all_cpus(get_counters
, EVEN_COUNTERS
);
2532 } else if (retval
== -1) {
2533 if (restarted
> 1) {
2540 gettimeofday(&tv_even
, (struct timezone
*)NULL
);
2543 if (for_all_proc_cpus(cpu_is_not_present
)) {
2547 nanosleep(&interval_ts
, NULL
);
2548 if (snapshot_proc_sysfs_files())
2550 retval
= for_all_cpus(get_counters
, ODD_COUNTERS
);
2553 } else if (retval
== -1) {
2557 gettimeofday(&tv_odd
, (struct timezone
*)NULL
);
2558 timersub(&tv_odd
, &tv_even
, &tv_delta
);
2559 if (for_all_cpus_2(delta_cpu
, ODD_COUNTERS
, EVEN_COUNTERS
)) {
2563 compute_average(EVEN_COUNTERS
);
2564 format_all_counters(EVEN_COUNTERS
);
2565 flush_output_stdout();
2566 nanosleep(&interval_ts
, NULL
);
2567 if (snapshot_proc_sysfs_files())
2569 retval
= for_all_cpus(get_counters
, EVEN_COUNTERS
);
2572 } else if (retval
== -1) {
2576 gettimeofday(&tv_even
, (struct timezone
*)NULL
);
2577 timersub(&tv_even
, &tv_odd
, &tv_delta
);
2578 if (for_all_cpus_2(delta_cpu
, EVEN_COUNTERS
, ODD_COUNTERS
)) {
2582 compute_average(ODD_COUNTERS
);
2583 format_all_counters(ODD_COUNTERS
);
2584 flush_output_stdout();
2588 void check_dev_msr()
2593 sprintf(pathname
, "/dev/cpu/%d/msr", base_cpu
);
2594 if (stat(pathname
, &sb
))
2595 if (system("/sbin/modprobe msr > /dev/null 2>&1"))
2596 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
2599 void check_permissions()
2601 struct __user_cap_header_struct cap_header_data
;
2602 cap_user_header_t cap_header
= &cap_header_data
;
2603 struct __user_cap_data_struct cap_data_data
;
2604 cap_user_data_t cap_data
= &cap_data_data
;
2605 extern int capget(cap_user_header_t hdrp
, cap_user_data_t datap
);
2609 /* check for CAP_SYS_RAWIO */
2610 cap_header
->pid
= getpid();
2611 cap_header
->version
= _LINUX_CAPABILITY_VERSION
;
2612 if (capget(cap_header
, cap_data
) < 0)
2613 err(-6, "capget(2) failed");
2615 if ((cap_data
->effective
& (1 << CAP_SYS_RAWIO
)) == 0) {
2617 warnx("capget(CAP_SYS_RAWIO) failed,"
2618 " try \"# setcap cap_sys_rawio=ep %s\"", progname
);
2621 /* test file permissions */
2622 sprintf(pathname
, "/dev/cpu/%d/msr", base_cpu
);
2623 if (euidaccess(pathname
, R_OK
)) {
2625 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr");
2628 /* if all else fails, thell them to be root */
2631 warnx("... or simply run as root");
2638 * NHM adds support for additional MSRs:
2640 * MSR_SMI_COUNT 0x00000034
2642 * MSR_PLATFORM_INFO 0x000000ce
2643 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
2645 * MSR_MISC_PWR_MGMT 0x000001aa
2647 * MSR_PKG_C3_RESIDENCY 0x000003f8
2648 * MSR_PKG_C6_RESIDENCY 0x000003f9
2649 * MSR_CORE_C3_RESIDENCY 0x000003fc
2650 * MSR_CORE_C6_RESIDENCY 0x000003fd
2653 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL
2654 * sets has_misc_feature_control
2656 int probe_nhm_msrs(unsigned int family
, unsigned int model
)
2658 unsigned long long msr
;
2659 unsigned int base_ratio
;
2660 int *pkg_cstate_limits
;
2668 bclk
= discover_bclk(family
, model
);
2671 case INTEL_FAM6_NEHALEM_EP
: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
2672 case INTEL_FAM6_NEHALEM
: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
2673 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
2674 case INTEL_FAM6_WESTMERE
: /* Westmere Client - Clarkdale, Arrandale */
2675 case INTEL_FAM6_WESTMERE_EP
: /* Westmere EP - Gulftown */
2676 case INTEL_FAM6_NEHALEM_EX
: /* Nehalem-EX Xeon - Beckton */
2677 case INTEL_FAM6_WESTMERE_EX
: /* Westmere-EX Xeon - Eagleton */
2678 pkg_cstate_limits
= nhm_pkg_cstate_limits
;
2680 case INTEL_FAM6_SANDYBRIDGE
: /* SNB */
2681 case INTEL_FAM6_SANDYBRIDGE_X
: /* SNB Xeon */
2682 case INTEL_FAM6_IVYBRIDGE
: /* IVB */
2683 case INTEL_FAM6_IVYBRIDGE_X
: /* IVB Xeon */
2684 pkg_cstate_limits
= snb_pkg_cstate_limits
;
2685 has_misc_feature_control
= 1;
2687 case INTEL_FAM6_HASWELL_CORE
: /* HSW */
2688 case INTEL_FAM6_HASWELL_X
: /* HSX */
2689 case INTEL_FAM6_HASWELL_ULT
: /* HSW */
2690 case INTEL_FAM6_HASWELL_GT3E
: /* HSW */
2691 case INTEL_FAM6_BROADWELL_CORE
: /* BDW */
2692 case INTEL_FAM6_BROADWELL_GT3E
: /* BDW */
2693 case INTEL_FAM6_BROADWELL_X
: /* BDX */
2694 case INTEL_FAM6_BROADWELL_XEON_D
: /* BDX-DE */
2695 case INTEL_FAM6_SKYLAKE_MOBILE
: /* SKL */
2696 case INTEL_FAM6_SKYLAKE_DESKTOP
: /* SKL */
2697 case INTEL_FAM6_KABYLAKE_MOBILE
: /* KBL */
2698 case INTEL_FAM6_KABYLAKE_DESKTOP
: /* KBL */
2699 pkg_cstate_limits
= hsw_pkg_cstate_limits
;
2700 has_misc_feature_control
= 1;
2702 case INTEL_FAM6_SKYLAKE_X
: /* SKX */
2703 pkg_cstate_limits
= skx_pkg_cstate_limits
;
2704 has_misc_feature_control
= 1;
2706 case INTEL_FAM6_ATOM_SILVERMONT1
: /* BYT */
2707 no_MSR_MISC_PWR_MGMT
= 1;
2708 case INTEL_FAM6_ATOM_SILVERMONT2
: /* AVN */
2709 pkg_cstate_limits
= slv_pkg_cstate_limits
;
2711 case INTEL_FAM6_ATOM_AIRMONT
: /* AMT */
2712 pkg_cstate_limits
= amt_pkg_cstate_limits
;
2713 no_MSR_MISC_PWR_MGMT
= 1;
2715 case INTEL_FAM6_XEON_PHI_KNL
: /* PHI */
2716 case INTEL_FAM6_XEON_PHI_KNM
:
2717 pkg_cstate_limits
= phi_pkg_cstate_limits
;
2719 case INTEL_FAM6_ATOM_GOLDMONT
: /* BXT */
2720 case INTEL_FAM6_ATOM_GEMINI_LAKE
:
2721 case INTEL_FAM6_ATOM_DENVERTON
: /* DNV */
2722 pkg_cstate_limits
= bxt_pkg_cstate_limits
;
2727 get_msr(base_cpu
, MSR_PKG_CST_CONFIG_CONTROL
, &msr
);
2728 pkg_cstate_limit
= pkg_cstate_limits
[msr
& 0xF];
2730 get_msr(base_cpu
, MSR_PLATFORM_INFO
, &msr
);
2731 base_ratio
= (msr
>> 8) & 0xFF;
2733 base_hz
= base_ratio
* bclk
* 1000000;
2738 * SLV client has support for unique MSRs:
2740 * MSR_CC6_DEMOTION_POLICY_CONFIG
2741 * MSR_MC6_DEMOTION_POLICY_CONFIG
2744 int has_slv_msrs(unsigned int family
, unsigned int model
)
2750 case INTEL_FAM6_ATOM_SILVERMONT1
:
2751 case INTEL_FAM6_ATOM_MERRIFIELD
:
2752 case INTEL_FAM6_ATOM_MOOREFIELD
:
2757 int is_dnv(unsigned int family
, unsigned int model
)
2764 case INTEL_FAM6_ATOM_DENVERTON
:
2769 int is_bdx(unsigned int family
, unsigned int model
)
2776 case INTEL_FAM6_BROADWELL_X
:
2777 case INTEL_FAM6_BROADWELL_XEON_D
:
2782 int is_skx(unsigned int family
, unsigned int model
)
2789 case INTEL_FAM6_SKYLAKE_X
:
2795 int has_turbo_ratio_limit(unsigned int family
, unsigned int model
)
2797 if (has_slv_msrs(family
, model
))
2801 /* Nehalem compatible, but do not include turbo-ratio limit support */
2802 case INTEL_FAM6_NEHALEM_EX
: /* Nehalem-EX Xeon - Beckton */
2803 case INTEL_FAM6_WESTMERE_EX
: /* Westmere-EX Xeon - Eagleton */
2804 case INTEL_FAM6_XEON_PHI_KNL
: /* PHI - Knights Landing (different MSR definition) */
2805 case INTEL_FAM6_XEON_PHI_KNM
:
2811 int has_atom_turbo_ratio_limit(unsigned int family
, unsigned int model
)
2813 if (has_slv_msrs(family
, model
))
2818 int has_ivt_turbo_ratio_limit(unsigned int family
, unsigned int model
)
2827 case INTEL_FAM6_IVYBRIDGE_X
: /* IVB Xeon */
2828 case INTEL_FAM6_HASWELL_X
: /* HSW Xeon */
2834 int has_hsw_turbo_ratio_limit(unsigned int family
, unsigned int model
)
2843 case INTEL_FAM6_HASWELL_X
: /* HSW Xeon */
2850 int has_knl_turbo_ratio_limit(unsigned int family
, unsigned int model
)
2859 case INTEL_FAM6_XEON_PHI_KNL
: /* Knights Landing */
2860 case INTEL_FAM6_XEON_PHI_KNM
:
2866 int has_glm_turbo_ratio_limit(unsigned int family
, unsigned int model
)
2875 case INTEL_FAM6_ATOM_GOLDMONT
:
2876 case INTEL_FAM6_SKYLAKE_X
:
2882 int has_config_tdp(unsigned int family
, unsigned int model
)
2891 case INTEL_FAM6_IVYBRIDGE
: /* IVB */
2892 case INTEL_FAM6_HASWELL_CORE
: /* HSW */
2893 case INTEL_FAM6_HASWELL_X
: /* HSX */
2894 case INTEL_FAM6_HASWELL_ULT
: /* HSW */
2895 case INTEL_FAM6_HASWELL_GT3E
: /* HSW */
2896 case INTEL_FAM6_BROADWELL_CORE
: /* BDW */
2897 case INTEL_FAM6_BROADWELL_GT3E
: /* BDW */
2898 case INTEL_FAM6_BROADWELL_X
: /* BDX */
2899 case INTEL_FAM6_BROADWELL_XEON_D
: /* BDX-DE */
2900 case INTEL_FAM6_SKYLAKE_MOBILE
: /* SKL */
2901 case INTEL_FAM6_SKYLAKE_DESKTOP
: /* SKL */
2902 case INTEL_FAM6_KABYLAKE_MOBILE
: /* KBL */
2903 case INTEL_FAM6_KABYLAKE_DESKTOP
: /* KBL */
2904 case INTEL_FAM6_SKYLAKE_X
: /* SKX */
2906 case INTEL_FAM6_XEON_PHI_KNL
: /* Knights Landing */
2907 case INTEL_FAM6_XEON_PHI_KNM
:
2915 dump_cstate_pstate_config_info(unsigned int family
, unsigned int model
)
2917 if (!do_nhm_platform_info
)
2920 dump_nhm_platform_info();
2922 if (has_hsw_turbo_ratio_limit(family
, model
))
2923 dump_hsw_turbo_ratio_limits();
2925 if (has_ivt_turbo_ratio_limit(family
, model
))
2926 dump_ivt_turbo_ratio_limits();
2928 if (has_turbo_ratio_limit(family
, model
))
2929 dump_turbo_ratio_limits(family
, model
);
2931 if (has_atom_turbo_ratio_limit(family
, model
))
2932 dump_atom_turbo_ratio_limits();
2934 if (has_knl_turbo_ratio_limit(family
, model
))
2935 dump_knl_turbo_ratio_limits();
2937 if (has_config_tdp(family
, model
))
2944 dump_sysfs_cstate_config(void)
2953 if (!DO_BIC(BIC_sysfs
))
2956 for (state
= 0; state
< 10; ++state
) {
2958 sprintf(path
, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name",
2960 input
= fopen(path
, "r");
2963 fgets(name_buf
, sizeof(name_buf
), input
);
2965 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
2966 sp
= strchr(name_buf
, '-');
2968 sp
= strchrnul(name_buf
, '\n');
2973 sprintf(path
, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc",
2975 input
= fopen(path
, "r");
2978 fgets(desc
, sizeof(desc
), input
);
2980 fprintf(outf
, "cpu%d: %s: %s", base_cpu
, name_buf
, desc
);
2985 dump_sysfs_pstate_config(void)
2988 char driver_buf
[64];
2989 char governor_buf
[64];
2993 sprintf(path
, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver",
2995 input
= fopen(path
, "r");
2996 if (input
== NULL
) {
2997 fprintf(stderr
, "NSFOD %s\n", path
);
3000 fgets(driver_buf
, sizeof(driver_buf
), input
);
3003 sprintf(path
, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor",
3005 input
= fopen(path
, "r");
3006 if (input
== NULL
) {
3007 fprintf(stderr
, "NSFOD %s\n", path
);
3010 fgets(governor_buf
, sizeof(governor_buf
), input
);
3013 fprintf(outf
, "cpu%d: cpufreq driver: %s", base_cpu
, driver_buf
);
3014 fprintf(outf
, "cpu%d: cpufreq governor: %s", base_cpu
, governor_buf
);
3016 sprintf(path
, "/sys/devices/system/cpu/cpufreq/boost");
3017 input
= fopen(path
, "r");
3018 if (input
!= NULL
) {
3019 fscanf(input
, "%d", &turbo
);
3020 fprintf(outf
, "cpufreq boost: %d\n", turbo
);
3024 sprintf(path
, "/sys/devices/system/cpu/intel_pstate/no_turbo");
3025 input
= fopen(path
, "r");
3026 if (input
!= NULL
) {
3027 fscanf(input
, "%d", &turbo
);
3028 fprintf(outf
, "cpufreq intel_pstate no_turbo: %d\n", turbo
);
3036 * Decode the ENERGY_PERF_BIAS MSR
3038 int print_epb(struct thread_data
*t
, struct core_data
*c
, struct pkg_data
*p
)
3040 unsigned long long msr
;
3049 /* EPB is per-package */
3050 if (!(t
->flags
& CPU_IS_FIRST_THREAD_IN_CORE
) || !(t
->flags
& CPU_IS_FIRST_CORE_IN_PACKAGE
))
3053 if (cpu_migrate(cpu
)) {
3054 fprintf(outf
, "Could not migrate to CPU %d\n", cpu
);
3058 if (get_msr(cpu
, MSR_IA32_ENERGY_PERF_BIAS
, &msr
))
3061 switch (msr
& 0xF) {
3062 case ENERGY_PERF_BIAS_PERFORMANCE
:
3063 epb_string
= "performance";
3065 case ENERGY_PERF_BIAS_NORMAL
:
3066 epb_string
= "balanced";
3068 case ENERGY_PERF_BIAS_POWERSAVE
:
3069 epb_string
= "powersave";
3072 epb_string
= "custom";
3075 fprintf(outf
, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu
, msr
, epb_string
);
3081 * Decode the MSR_HWP_CAPABILITIES
3083 int print_hwp(struct thread_data
*t
, struct core_data
*c
, struct pkg_data
*p
)
3085 unsigned long long msr
;
3093 /* MSR_HWP_CAPABILITIES is per-package */
3094 if (!(t
->flags
& CPU_IS_FIRST_THREAD_IN_CORE
) || !(t
->flags
& CPU_IS_FIRST_CORE_IN_PACKAGE
))
3097 if (cpu_migrate(cpu
)) {
3098 fprintf(outf
, "Could not migrate to CPU %d\n", cpu
);
3102 if (get_msr(cpu
, MSR_PM_ENABLE
, &msr
))
3105 fprintf(outf
, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n",
3106 cpu
, msr
, (msr
& (1 << 0)) ? "" : "No-");
3108 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */
3109 if ((msr
& (1 << 0)) == 0)
3112 if (get_msr(cpu
, MSR_HWP_CAPABILITIES
, &msr
))
3115 fprintf(outf
, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx "
3116 "(high %d guar %d eff %d low %d)\n",
3118 (unsigned int)HWP_HIGHEST_PERF(msr
),
3119 (unsigned int)HWP_GUARANTEED_PERF(msr
),
3120 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr
),
3121 (unsigned int)HWP_LOWEST_PERF(msr
));
3123 if (get_msr(cpu
, MSR_HWP_REQUEST
, &msr
))
3126 fprintf(outf
, "cpu%d: MSR_HWP_REQUEST: 0x%08llx "
3127 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n",
3129 (unsigned int)(((msr
) >> 0) & 0xff),
3130 (unsigned int)(((msr
) >> 8) & 0xff),
3131 (unsigned int)(((msr
) >> 16) & 0xff),
3132 (unsigned int)(((msr
) >> 24) & 0xff),
3133 (unsigned int)(((msr
) >> 32) & 0xff3),
3134 (unsigned int)(((msr
) >> 42) & 0x1));
3137 if (get_msr(cpu
, MSR_HWP_REQUEST_PKG
, &msr
))
3140 fprintf(outf
, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx "
3141 "(min %d max %d des %d epp 0x%x window 0x%x)\n",
3143 (unsigned int)(((msr
) >> 0) & 0xff),
3144 (unsigned int)(((msr
) >> 8) & 0xff),
3145 (unsigned int)(((msr
) >> 16) & 0xff),
3146 (unsigned int)(((msr
) >> 24) & 0xff),
3147 (unsigned int)(((msr
) >> 32) & 0xff3));
3149 if (has_hwp_notify
) {
3150 if (get_msr(cpu
, MSR_HWP_INTERRUPT
, &msr
))
3153 fprintf(outf
, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx "
3154 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n",
3156 ((msr
) & 0x1) ? "EN" : "Dis",
3157 ((msr
) & 0x2) ? "EN" : "Dis");
3159 if (get_msr(cpu
, MSR_HWP_STATUS
, &msr
))
3162 fprintf(outf
, "cpu%d: MSR_HWP_STATUS: 0x%08llx "
3163 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n",
3165 ((msr
) & 0x1) ? "" : "No-",
3166 ((msr
) & 0x2) ? "" : "No-");
3172 * print_perf_limit()
3174 int print_perf_limit(struct thread_data
*t
, struct core_data
*c
, struct pkg_data
*p
)
3176 unsigned long long msr
;
3182 if (!(t
->flags
& CPU_IS_FIRST_THREAD_IN_CORE
) || !(t
->flags
& CPU_IS_FIRST_CORE_IN_PACKAGE
))
3185 if (cpu_migrate(cpu
)) {
3186 fprintf(outf
, "Could not migrate to CPU %d\n", cpu
);
3190 if (do_core_perf_limit_reasons
) {
3191 get_msr(cpu
, MSR_CORE_PERF_LIMIT_REASONS
, &msr
);
3192 fprintf(outf
, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu
, msr
);
3193 fprintf(outf
, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)",
3194 (msr
& 1 << 15) ? "bit15, " : "",
3195 (msr
& 1 << 14) ? "bit14, " : "",
3196 (msr
& 1 << 13) ? "Transitions, " : "",
3197 (msr
& 1 << 12) ? "MultiCoreTurbo, " : "",
3198 (msr
& 1 << 11) ? "PkgPwrL2, " : "",
3199 (msr
& 1 << 10) ? "PkgPwrL1, " : "",
3200 (msr
& 1 << 9) ? "CorePwr, " : "",
3201 (msr
& 1 << 8) ? "Amps, " : "",
3202 (msr
& 1 << 6) ? "VR-Therm, " : "",
3203 (msr
& 1 << 5) ? "Auto-HWP, " : "",
3204 (msr
& 1 << 4) ? "Graphics, " : "",
3205 (msr
& 1 << 2) ? "bit2, " : "",
3206 (msr
& 1 << 1) ? "ThermStatus, " : "",
3207 (msr
& 1 << 0) ? "PROCHOT, " : "");
3208 fprintf(outf
, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
3209 (msr
& 1 << 31) ? "bit31, " : "",
3210 (msr
& 1 << 30) ? "bit30, " : "",
3211 (msr
& 1 << 29) ? "Transitions, " : "",
3212 (msr
& 1 << 28) ? "MultiCoreTurbo, " : "",
3213 (msr
& 1 << 27) ? "PkgPwrL2, " : "",
3214 (msr
& 1 << 26) ? "PkgPwrL1, " : "",
3215 (msr
& 1 << 25) ? "CorePwr, " : "",
3216 (msr
& 1 << 24) ? "Amps, " : "",
3217 (msr
& 1 << 22) ? "VR-Therm, " : "",
3218 (msr
& 1 << 21) ? "Auto-HWP, " : "",
3219 (msr
& 1 << 20) ? "Graphics, " : "",
3220 (msr
& 1 << 18) ? "bit18, " : "",
3221 (msr
& 1 << 17) ? "ThermStatus, " : "",
3222 (msr
& 1 << 16) ? "PROCHOT, " : "");
3225 if (do_gfx_perf_limit_reasons
) {
3226 get_msr(cpu
, MSR_GFX_PERF_LIMIT_REASONS
, &msr
);
3227 fprintf(outf
, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu
, msr
);
3228 fprintf(outf
, " (Active: %s%s%s%s%s%s%s%s)",
3229 (msr
& 1 << 0) ? "PROCHOT, " : "",
3230 (msr
& 1 << 1) ? "ThermStatus, " : "",
3231 (msr
& 1 << 4) ? "Graphics, " : "",
3232 (msr
& 1 << 6) ? "VR-Therm, " : "",
3233 (msr
& 1 << 8) ? "Amps, " : "",
3234 (msr
& 1 << 9) ? "GFXPwr, " : "",
3235 (msr
& 1 << 10) ? "PkgPwrL1, " : "",
3236 (msr
& 1 << 11) ? "PkgPwrL2, " : "");
3237 fprintf(outf
, " (Logged: %s%s%s%s%s%s%s%s)\n",
3238 (msr
& 1 << 16) ? "PROCHOT, " : "",
3239 (msr
& 1 << 17) ? "ThermStatus, " : "",
3240 (msr
& 1 << 20) ? "Graphics, " : "",
3241 (msr
& 1 << 22) ? "VR-Therm, " : "",
3242 (msr
& 1 << 24) ? "Amps, " : "",
3243 (msr
& 1 << 25) ? "GFXPwr, " : "",
3244 (msr
& 1 << 26) ? "PkgPwrL1, " : "",
3245 (msr
& 1 << 27) ? "PkgPwrL2, " : "");
3247 if (do_ring_perf_limit_reasons
) {
3248 get_msr(cpu
, MSR_RING_PERF_LIMIT_REASONS
, &msr
);
3249 fprintf(outf
, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu
, msr
);
3250 fprintf(outf
, " (Active: %s%s%s%s%s%s)",
3251 (msr
& 1 << 0) ? "PROCHOT, " : "",
3252 (msr
& 1 << 1) ? "ThermStatus, " : "",
3253 (msr
& 1 << 6) ? "VR-Therm, " : "",
3254 (msr
& 1 << 8) ? "Amps, " : "",
3255 (msr
& 1 << 10) ? "PkgPwrL1, " : "",
3256 (msr
& 1 << 11) ? "PkgPwrL2, " : "");
3257 fprintf(outf
, " (Logged: %s%s%s%s%s%s)\n",
3258 (msr
& 1 << 16) ? "PROCHOT, " : "",
3259 (msr
& 1 << 17) ? "ThermStatus, " : "",
3260 (msr
& 1 << 22) ? "VR-Therm, " : "",
3261 (msr
& 1 << 24) ? "Amps, " : "",
3262 (msr
& 1 << 26) ? "PkgPwrL1, " : "",
3263 (msr
& 1 << 27) ? "PkgPwrL2, " : "");
3268 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */
3269 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */
3271 double get_tdp(unsigned int model
)
3273 unsigned long long msr
;
3275 if (do_rapl
& RAPL_PKG_POWER_INFO
)
3276 if (!get_msr(base_cpu
, MSR_PKG_POWER_INFO
, &msr
))
3277 return ((msr
>> 0) & RAPL_POWER_GRANULARITY
) * rapl_power_units
;
3280 case INTEL_FAM6_ATOM_SILVERMONT1
:
3281 case INTEL_FAM6_ATOM_SILVERMONT2
:
3289 * rapl_dram_energy_units_probe()
3290 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR.
3293 rapl_dram_energy_units_probe(int model
, double rapl_energy_units
)
3295 /* only called for genuine_intel, family 6 */
3298 case INTEL_FAM6_HASWELL_X
: /* HSX */
3299 case INTEL_FAM6_BROADWELL_X
: /* BDX */
3300 case INTEL_FAM6_BROADWELL_XEON_D
: /* BDX-DE */
3301 case INTEL_FAM6_XEON_PHI_KNL
: /* KNL */
3302 case INTEL_FAM6_XEON_PHI_KNM
:
3303 return (rapl_dram_energy_units
= 15.3 / 1000000);
3305 return (rapl_energy_units
);
3313 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units
3315 void rapl_probe(unsigned int family
, unsigned int model
)
3317 unsigned long long msr
;
3318 unsigned int time_unit
;
3328 case INTEL_FAM6_SANDYBRIDGE
:
3329 case INTEL_FAM6_IVYBRIDGE
:
3330 case INTEL_FAM6_HASWELL_CORE
: /* HSW */
3331 case INTEL_FAM6_HASWELL_ULT
: /* HSW */
3332 case INTEL_FAM6_HASWELL_GT3E
: /* HSW */
3333 case INTEL_FAM6_BROADWELL_CORE
: /* BDW */
3334 case INTEL_FAM6_BROADWELL_GT3E
: /* BDW */
3335 do_rapl
= RAPL_PKG
| RAPL_CORES
| RAPL_CORE_POLICY
| RAPL_GFX
| RAPL_PKG_POWER_INFO
;
3337 BIC_PRESENT(BIC_Pkg_J
);
3338 BIC_PRESENT(BIC_Cor_J
);
3339 BIC_PRESENT(BIC_GFX_J
);
3341 BIC_PRESENT(BIC_PkgWatt
);
3342 BIC_PRESENT(BIC_CorWatt
);
3343 BIC_PRESENT(BIC_GFXWatt
);
3346 case INTEL_FAM6_ATOM_GOLDMONT
: /* BXT */
3347 case INTEL_FAM6_ATOM_GEMINI_LAKE
:
3348 do_rapl
= RAPL_PKG
| RAPL_PKG_POWER_INFO
;
3350 BIC_PRESENT(BIC_Pkg_J
);
3352 BIC_PRESENT(BIC_PkgWatt
);
3354 case INTEL_FAM6_SKYLAKE_MOBILE
: /* SKL */
3355 case INTEL_FAM6_SKYLAKE_DESKTOP
: /* SKL */
3356 case INTEL_FAM6_KABYLAKE_MOBILE
: /* KBL */
3357 case INTEL_FAM6_KABYLAKE_DESKTOP
: /* KBL */
3358 do_rapl
= RAPL_PKG
| RAPL_CORES
| RAPL_CORE_POLICY
| RAPL_DRAM
| RAPL_DRAM_PERF_STATUS
| RAPL_PKG_PERF_STATUS
| RAPL_GFX
| RAPL_PKG_POWER_INFO
;
3359 BIC_PRESENT(BIC_PKG__
);
3360 BIC_PRESENT(BIC_RAM__
);
3362 BIC_PRESENT(BIC_Pkg_J
);
3363 BIC_PRESENT(BIC_Cor_J
);
3364 BIC_PRESENT(BIC_RAM_J
);
3365 BIC_PRESENT(BIC_GFX_J
);
3367 BIC_PRESENT(BIC_PkgWatt
);
3368 BIC_PRESENT(BIC_CorWatt
);
3369 BIC_PRESENT(BIC_RAMWatt
);
3370 BIC_PRESENT(BIC_GFXWatt
);
3373 case INTEL_FAM6_HASWELL_X
: /* HSX */
3374 case INTEL_FAM6_BROADWELL_X
: /* BDX */
3375 case INTEL_FAM6_BROADWELL_XEON_D
: /* BDX-DE */
3376 case INTEL_FAM6_SKYLAKE_X
: /* SKX */
3377 case INTEL_FAM6_XEON_PHI_KNL
: /* KNL */
3378 case INTEL_FAM6_XEON_PHI_KNM
:
3379 do_rapl
= RAPL_PKG
| RAPL_DRAM
| RAPL_DRAM_POWER_INFO
| RAPL_DRAM_PERF_STATUS
| RAPL_PKG_PERF_STATUS
| RAPL_PKG_POWER_INFO
;
3380 BIC_PRESENT(BIC_PKG__
);
3381 BIC_PRESENT(BIC_RAM__
);
3383 BIC_PRESENT(BIC_Pkg_J
);
3384 BIC_PRESENT(BIC_RAM_J
);
3386 BIC_PRESENT(BIC_PkgWatt
);
3387 BIC_PRESENT(BIC_RAMWatt
);
3390 case INTEL_FAM6_SANDYBRIDGE_X
:
3391 case INTEL_FAM6_IVYBRIDGE_X
:
3392 do_rapl
= RAPL_PKG
| RAPL_CORES
| RAPL_CORE_POLICY
| RAPL_DRAM
| RAPL_DRAM_POWER_INFO
| RAPL_PKG_PERF_STATUS
| RAPL_DRAM_PERF_STATUS
| RAPL_PKG_POWER_INFO
;
3393 BIC_PRESENT(BIC_PKG__
);
3394 BIC_PRESENT(BIC_RAM__
);
3396 BIC_PRESENT(BIC_Pkg_J
);
3397 BIC_PRESENT(BIC_Cor_J
);
3398 BIC_PRESENT(BIC_RAM_J
);
3400 BIC_PRESENT(BIC_PkgWatt
);
3401 BIC_PRESENT(BIC_CorWatt
);
3402 BIC_PRESENT(BIC_RAMWatt
);
3405 case INTEL_FAM6_ATOM_SILVERMONT1
: /* BYT */
3406 case INTEL_FAM6_ATOM_SILVERMONT2
: /* AVN */
3407 do_rapl
= RAPL_PKG
| RAPL_CORES
;
3409 BIC_PRESENT(BIC_Pkg_J
);
3410 BIC_PRESENT(BIC_Cor_J
);
3412 BIC_PRESENT(BIC_PkgWatt
);
3413 BIC_PRESENT(BIC_CorWatt
);
3416 case INTEL_FAM6_ATOM_DENVERTON
: /* DNV */
3417 do_rapl
= RAPL_PKG
| RAPL_DRAM
| RAPL_DRAM_POWER_INFO
| RAPL_DRAM_PERF_STATUS
| RAPL_PKG_PERF_STATUS
| RAPL_PKG_POWER_INFO
| RAPL_CORES_ENERGY_STATUS
;
3418 BIC_PRESENT(BIC_PKG__
);
3419 BIC_PRESENT(BIC_RAM__
);
3421 BIC_PRESENT(BIC_Pkg_J
);
3422 BIC_PRESENT(BIC_Cor_J
);
3423 BIC_PRESENT(BIC_RAM_J
);
3425 BIC_PRESENT(BIC_PkgWatt
);
3426 BIC_PRESENT(BIC_CorWatt
);
3427 BIC_PRESENT(BIC_RAMWatt
);
3434 /* units on package 0, verify later other packages match */
3435 if (get_msr(base_cpu
, MSR_RAPL_POWER_UNIT
, &msr
))
3438 rapl_power_units
= 1.0 / (1 << (msr
& 0xF));
3439 if (model
== INTEL_FAM6_ATOM_SILVERMONT1
)
3440 rapl_energy_units
= 1.0 * (1 << (msr
>> 8 & 0x1F)) / 1000000;
3442 rapl_energy_units
= 1.0 / (1 << (msr
>> 8 & 0x1F));
3444 rapl_dram_energy_units
= rapl_dram_energy_units_probe(model
, rapl_energy_units
);
3446 time_unit
= msr
>> 16 & 0xF;
3450 rapl_time_units
= 1.0 / (1 << (time_unit
));
3452 tdp
= get_tdp(model
);
3454 rapl_joule_counter_range
= 0xFFFFFFFF * rapl_energy_units
/ tdp
;
3456 fprintf(outf
, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range
, tdp
);
3461 void perf_limit_reasons_probe(unsigned int family
, unsigned int model
)
3470 case INTEL_FAM6_HASWELL_CORE
: /* HSW */
3471 case INTEL_FAM6_HASWELL_ULT
: /* HSW */
3472 case INTEL_FAM6_HASWELL_GT3E
: /* HSW */
3473 do_gfx_perf_limit_reasons
= 1;
3474 case INTEL_FAM6_HASWELL_X
: /* HSX */
3475 do_core_perf_limit_reasons
= 1;
3476 do_ring_perf_limit_reasons
= 1;
3482 int print_thermal(struct thread_data
*t
, struct core_data
*c
, struct pkg_data
*p
)
3484 unsigned long long msr
;
3485 unsigned int dts
, dts2
;
3488 if (!(do_dts
|| do_ptm
))
3493 /* DTS is per-core, no need to print for each thread */
3494 if (!(t
->flags
& CPU_IS_FIRST_THREAD_IN_CORE
))
3497 if (cpu_migrate(cpu
)) {
3498 fprintf(outf
, "Could not migrate to CPU %d\n", cpu
);
3502 if (do_ptm
&& (t
->flags
& CPU_IS_FIRST_CORE_IN_PACKAGE
)) {
3503 if (get_msr(cpu
, MSR_IA32_PACKAGE_THERM_STATUS
, &msr
))
3506 dts
= (msr
>> 16) & 0x7F;
3507 fprintf(outf
, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n",
3508 cpu
, msr
, tcc_activation_temp
- dts
);
3510 if (get_msr(cpu
, MSR_IA32_PACKAGE_THERM_INTERRUPT
, &msr
))
3513 dts
= (msr
>> 16) & 0x7F;
3514 dts2
= (msr
>> 8) & 0x7F;
3515 fprintf(outf
, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
3516 cpu
, msr
, tcc_activation_temp
- dts
, tcc_activation_temp
- dts2
);
3520 if (do_dts
&& debug
) {
3521 unsigned int resolution
;
3523 if (get_msr(cpu
, MSR_IA32_THERM_STATUS
, &msr
))
3526 dts
= (msr
>> 16) & 0x7F;
3527 resolution
= (msr
>> 27) & 0xF;
3528 fprintf(outf
, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n",
3529 cpu
, msr
, tcc_activation_temp
- dts
, resolution
);
3531 if (get_msr(cpu
, MSR_IA32_THERM_INTERRUPT
, &msr
))
3534 dts
= (msr
>> 16) & 0x7F;
3535 dts2
= (msr
>> 8) & 0x7F;
3536 fprintf(outf
, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
3537 cpu
, msr
, tcc_activation_temp
- dts
, tcc_activation_temp
- dts2
);
3543 void print_power_limit_msr(int cpu
, unsigned long long msr
, char *label
)
3545 fprintf(outf
, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n",
3547 ((msr
>> 15) & 1) ? "EN" : "DIS",
3548 ((msr
>> 0) & 0x7FFF) * rapl_power_units
,
3549 (1.0 + (((msr
>> 22) & 0x3)/4.0)) * (1 << ((msr
>> 17) & 0x1F)) * rapl_time_units
,
3550 (((msr
>> 16) & 1) ? "EN" : "DIS"));
3555 int print_rapl(struct thread_data
*t
, struct core_data
*c
, struct pkg_data
*p
)
3557 unsigned long long msr
;
3563 /* RAPL counters are per package, so print only for 1st thread/package */
3564 if (!(t
->flags
& CPU_IS_FIRST_THREAD_IN_CORE
) || !(t
->flags
& CPU_IS_FIRST_CORE_IN_PACKAGE
))
3568 if (cpu_migrate(cpu
)) {
3569 fprintf(outf
, "Could not migrate to CPU %d\n", cpu
);
3573 if (get_msr(cpu
, MSR_RAPL_POWER_UNIT
, &msr
))
3576 fprintf(outf
, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu
, msr
,
3577 rapl_power_units
, rapl_energy_units
, rapl_time_units
);
3579 if (do_rapl
& RAPL_PKG_POWER_INFO
) {
3581 if (get_msr(cpu
, MSR_PKG_POWER_INFO
, &msr
))
3585 fprintf(outf
, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
3587 ((msr
>> 0) & RAPL_POWER_GRANULARITY
) * rapl_power_units
,
3588 ((msr
>> 16) & RAPL_POWER_GRANULARITY
) * rapl_power_units
,
3589 ((msr
>> 32) & RAPL_POWER_GRANULARITY
) * rapl_power_units
,
3590 ((msr
>> 48) & RAPL_TIME_GRANULARITY
) * rapl_time_units
);
3593 if (do_rapl
& RAPL_PKG
) {
3595 if (get_msr(cpu
, MSR_PKG_POWER_LIMIT
, &msr
))
3598 fprintf(outf
, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n",
3599 cpu
, msr
, (msr
>> 63) & 1 ? "" : "UN");
3601 print_power_limit_msr(cpu
, msr
, "PKG Limit #1");
3602 fprintf(outf
, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n",
3604 ((msr
>> 47) & 1) ? "EN" : "DIS",
3605 ((msr
>> 32) & 0x7FFF) * rapl_power_units
,
3606 (1.0 + (((msr
>> 54) & 0x3)/4.0)) * (1 << ((msr
>> 49) & 0x1F)) * rapl_time_units
,
3607 ((msr
>> 48) & 1) ? "EN" : "DIS");
3610 if (do_rapl
& RAPL_DRAM_POWER_INFO
) {
3611 if (get_msr(cpu
, MSR_DRAM_POWER_INFO
, &msr
))
3614 fprintf(outf
, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
3616 ((msr
>> 0) & RAPL_POWER_GRANULARITY
) * rapl_power_units
,
3617 ((msr
>> 16) & RAPL_POWER_GRANULARITY
) * rapl_power_units
,
3618 ((msr
>> 32) & RAPL_POWER_GRANULARITY
) * rapl_power_units
,
3619 ((msr
>> 48) & RAPL_TIME_GRANULARITY
) * rapl_time_units
);
3621 if (do_rapl
& RAPL_DRAM
) {
3622 if (get_msr(cpu
, MSR_DRAM_POWER_LIMIT
, &msr
))
3624 fprintf(outf
, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
3625 cpu
, msr
, (msr
>> 31) & 1 ? "" : "UN");
3627 print_power_limit_msr(cpu
, msr
, "DRAM Limit");
3629 if (do_rapl
& RAPL_CORE_POLICY
) {
3630 if (get_msr(cpu
, MSR_PP0_POLICY
, &msr
))
3633 fprintf(outf
, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu
, msr
& 0xF);
3635 if (do_rapl
& RAPL_CORES_POWER_LIMIT
) {
3636 if (get_msr(cpu
, MSR_PP0_POWER_LIMIT
, &msr
))
3638 fprintf(outf
, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",
3639 cpu
, msr
, (msr
>> 31) & 1 ? "" : "UN");
3640 print_power_limit_msr(cpu
, msr
, "Cores Limit");
3642 if (do_rapl
& RAPL_GFX
) {
3643 if (get_msr(cpu
, MSR_PP1_POLICY
, &msr
))
3646 fprintf(outf
, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu
, msr
& 0xF);
3648 if (get_msr(cpu
, MSR_PP1_POWER_LIMIT
, &msr
))
3650 fprintf(outf
, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n",
3651 cpu
, msr
, (msr
>> 31) & 1 ? "" : "UN");
3652 print_power_limit_msr(cpu
, msr
, "GFX Limit");
3658 * SNB adds support for additional MSRs:
3660 * MSR_PKG_C7_RESIDENCY 0x000003fa
3661 * MSR_CORE_C7_RESIDENCY 0x000003fe
3662 * MSR_PKG_C2_RESIDENCY 0x0000060d
3665 int has_snb_msrs(unsigned int family
, unsigned int model
)
3671 case INTEL_FAM6_SANDYBRIDGE
:
3672 case INTEL_FAM6_SANDYBRIDGE_X
:
3673 case INTEL_FAM6_IVYBRIDGE
: /* IVB */
3674 case INTEL_FAM6_IVYBRIDGE_X
: /* IVB Xeon */
3675 case INTEL_FAM6_HASWELL_CORE
: /* HSW */
3676 case INTEL_FAM6_HASWELL_X
: /* HSW */
3677 case INTEL_FAM6_HASWELL_ULT
: /* HSW */
3678 case INTEL_FAM6_HASWELL_GT3E
: /* HSW */
3679 case INTEL_FAM6_BROADWELL_CORE
: /* BDW */
3680 case INTEL_FAM6_BROADWELL_GT3E
: /* BDW */
3681 case INTEL_FAM6_BROADWELL_X
: /* BDX */
3682 case INTEL_FAM6_BROADWELL_XEON_D
: /* BDX-DE */
3683 case INTEL_FAM6_SKYLAKE_MOBILE
: /* SKL */
3684 case INTEL_FAM6_SKYLAKE_DESKTOP
: /* SKL */
3685 case INTEL_FAM6_KABYLAKE_MOBILE
: /* KBL */
3686 case INTEL_FAM6_KABYLAKE_DESKTOP
: /* KBL */
3687 case INTEL_FAM6_SKYLAKE_X
: /* SKX */
3688 case INTEL_FAM6_ATOM_GOLDMONT
: /* BXT */
3689 case INTEL_FAM6_ATOM_GEMINI_LAKE
:
3690 case INTEL_FAM6_ATOM_DENVERTON
: /* DNV */
3697 * HSW adds support for additional MSRs:
3699 * MSR_PKG_C8_RESIDENCY 0x00000630
3700 * MSR_PKG_C9_RESIDENCY 0x00000631
3701 * MSR_PKG_C10_RESIDENCY 0x00000632
3703 * MSR_PKGC8_IRTL 0x00000633
3704 * MSR_PKGC9_IRTL 0x00000634
3705 * MSR_PKGC10_IRTL 0x00000635
3708 int has_hsw_msrs(unsigned int family
, unsigned int model
)
3714 case INTEL_FAM6_HASWELL_ULT
: /* HSW */
3715 case INTEL_FAM6_BROADWELL_CORE
: /* BDW */
3716 case INTEL_FAM6_SKYLAKE_MOBILE
: /* SKL */
3717 case INTEL_FAM6_SKYLAKE_DESKTOP
: /* SKL */
3718 case INTEL_FAM6_KABYLAKE_MOBILE
: /* KBL */
3719 case INTEL_FAM6_KABYLAKE_DESKTOP
: /* KBL */
3720 case INTEL_FAM6_ATOM_GOLDMONT
: /* BXT */
3721 case INTEL_FAM6_ATOM_GEMINI_LAKE
:
3728 * SKL adds support for additional MSRS:
3730 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
3731 * MSR_PKG_ANY_CORE_C0_RES 0x00000659
3732 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
3733 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
3735 int has_skl_msrs(unsigned int family
, unsigned int model
)
3741 case INTEL_FAM6_SKYLAKE_MOBILE
: /* SKL */
3742 case INTEL_FAM6_SKYLAKE_DESKTOP
: /* SKL */
3743 case INTEL_FAM6_KABYLAKE_MOBILE
: /* KBL */
3744 case INTEL_FAM6_KABYLAKE_DESKTOP
: /* KBL */
3750 int is_slm(unsigned int family
, unsigned int model
)
3755 case INTEL_FAM6_ATOM_SILVERMONT1
: /* BYT */
3756 case INTEL_FAM6_ATOM_SILVERMONT2
: /* AVN */
3762 int is_knl(unsigned int family
, unsigned int model
)
3767 case INTEL_FAM6_XEON_PHI_KNL
: /* KNL */
3768 case INTEL_FAM6_XEON_PHI_KNM
:
3774 unsigned int get_aperf_mperf_multiplier(unsigned int family
, unsigned int model
)
3776 if (is_knl(family
, model
))
3781 #define SLM_BCLK_FREQS 5
3782 double slm_freq_table
[SLM_BCLK_FREQS
] = { 83.3, 100.0, 133.3, 116.7, 80.0};
3784 double slm_bclk(void)
3786 unsigned long long msr
= 3;
3790 if (get_msr(base_cpu
, MSR_FSB_FREQ
, &msr
))
3791 fprintf(outf
, "SLM BCLK: unknown\n");
3794 if (i
>= SLM_BCLK_FREQS
) {
3795 fprintf(outf
, "SLM BCLK[%d] invalid\n", i
);
3798 freq
= slm_freq_table
[i
];
3801 fprintf(outf
, "SLM BCLK: %.1f Mhz\n", freq
);
3806 double discover_bclk(unsigned int family
, unsigned int model
)
3808 if (has_snb_msrs(family
, model
) || is_knl(family
, model
))
3810 else if (is_slm(family
, model
))
3817 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where
3818 * the Thermal Control Circuit (TCC) activates.
3819 * This is usually equal to tjMax.
3821 * Older processors do not have this MSR, so there we guess,
3822 * but also allow cmdline over-ride with -T.
3824 * Several MSR temperature values are in units of degrees-C
3825 * below this value, including the Digital Thermal Sensor (DTS),
3826 * Package Thermal Management Sensor (PTM), and thermal event thresholds.
3828 int set_temperature_target(struct thread_data
*t
, struct core_data
*c
, struct pkg_data
*p
)
3830 unsigned long long msr
;
3831 unsigned int target_c_local
;
3834 /* tcc_activation_temp is used only for dts or ptm */
3835 if (!(do_dts
|| do_ptm
))
3838 /* this is a per-package concept */
3839 if (!(t
->flags
& CPU_IS_FIRST_THREAD_IN_CORE
) || !(t
->flags
& CPU_IS_FIRST_CORE_IN_PACKAGE
))
3843 if (cpu_migrate(cpu
)) {
3844 fprintf(outf
, "Could not migrate to CPU %d\n", cpu
);
3848 if (tcc_activation_temp_override
!= 0) {
3849 tcc_activation_temp
= tcc_activation_temp_override
;
3850 fprintf(outf
, "cpu%d: Using cmdline TCC Target (%d C)\n",
3851 cpu
, tcc_activation_temp
);
3855 /* Temperature Target MSR is Nehalem and newer only */
3856 if (!do_nhm_platform_info
)
3859 if (get_msr(base_cpu
, MSR_IA32_TEMPERATURE_TARGET
, &msr
))
3862 target_c_local
= (msr
>> 16) & 0xFF;
3865 fprintf(outf
, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n",
3866 cpu
, msr
, target_c_local
);
3868 if (!target_c_local
)
3871 tcc_activation_temp
= target_c_local
;
3876 tcc_activation_temp
= TJMAX_DEFAULT
;
3877 fprintf(outf
, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n",
3878 cpu
, tcc_activation_temp
);
3883 void decode_feature_control_msr(void)
3885 unsigned long long msr
;
3887 if (!get_msr(base_cpu
, MSR_IA32_FEATURE_CONTROL
, &msr
))
3888 fprintf(outf
, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n",
3890 msr
& FEATURE_CONTROL_LOCKED
? "" : "UN-",
3891 msr
& (1 << 18) ? "SGX" : "");
3894 void decode_misc_enable_msr(void)
3896 unsigned long long msr
;
3898 if (!get_msr(base_cpu
, MSR_IA32_MISC_ENABLE
, &msr
))
3899 fprintf(outf
, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n",
3901 msr
& MSR_IA32_MISC_ENABLE_TM1
? "" : "No-",
3902 msr
& MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP
? "" : "No-",
3903 msr
& MSR_IA32_MISC_ENABLE_MWAIT
? "No-" : "",
3904 msr
& MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE
? "No-" : "",
3905 msr
& MSR_IA32_MISC_ENABLE_TURBO_DISABLE
? "No-" : "");
3908 void decode_misc_feature_control(void)
3910 unsigned long long msr
;
3912 if (!has_misc_feature_control
)
3915 if (!get_msr(base_cpu
, MSR_MISC_FEATURE_CONTROL
, &msr
))
3916 fprintf(outf
, "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n",
3918 msr
& (0 << 0) ? "No-" : "",
3919 msr
& (1 << 0) ? "No-" : "",
3920 msr
& (2 << 0) ? "No-" : "",
3921 msr
& (3 << 0) ? "No-" : "");
3924 * Decode MSR_MISC_PWR_MGMT
3926 * Decode the bits according to the Nehalem documentation
3927 * bit[0] seems to continue to have same meaning going forward
3930 void decode_misc_pwr_mgmt_msr(void)
3932 unsigned long long msr
;
3934 if (!do_nhm_platform_info
)
3937 if (no_MSR_MISC_PWR_MGMT
)
3940 if (!get_msr(base_cpu
, MSR_MISC_PWR_MGMT
, &msr
))
3941 fprintf(outf
, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
3943 msr
& (1 << 0) ? "DIS" : "EN",
3944 msr
& (1 << 1) ? "EN" : "DIS",
3945 msr
& (1 << 8) ? "EN" : "DIS");
3948 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG
3950 * This MSRs are present on Silvermont processors,
3951 * Intel Atom processor E3000 series (Baytrail), and friends.
3953 void decode_c6_demotion_policy_msr(void)
3955 unsigned long long msr
;
3957 if (!get_msr(base_cpu
, MSR_CC6_DEMOTION_POLICY_CONFIG
, &msr
))
3958 fprintf(outf
, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n",
3959 base_cpu
, msr
, msr
& (1 << 0) ? "EN" : "DIS");
3961 if (!get_msr(base_cpu
, MSR_MC6_DEMOTION_POLICY_CONFIG
, &msr
))
3962 fprintf(outf
, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n",
3963 base_cpu
, msr
, msr
& (1 << 0) ? "EN" : "DIS");
3966 void process_cpuid()
3968 unsigned int eax
, ebx
, ecx
, edx
, max_level
, max_extended_level
;
3969 unsigned int fms
, family
, model
, stepping
;
3970 unsigned int has_turbo
;
3972 eax
= ebx
= ecx
= edx
= 0;
3974 __cpuid(0, max_level
, ebx
, ecx
, edx
);
3976 if (ebx
== 0x756e6547 && edx
== 0x49656e69 && ecx
== 0x6c65746e)
3980 fprintf(outf
, "CPUID(0): %.4s%.4s%.4s ",
3981 (char *)&ebx
, (char *)&edx
, (char *)&ecx
);
3983 __cpuid(1, fms
, ebx
, ecx
, edx
);
3984 family
= (fms
>> 8) & 0xf;
3985 model
= (fms
>> 4) & 0xf;
3986 stepping
= fms
& 0xf;
3987 if (family
== 6 || family
== 0xf)
3988 model
+= ((fms
>> 16) & 0xf) << 4;
3991 fprintf(outf
, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n",
3992 max_level
, family
, model
, stepping
, family
, model
, stepping
);
3993 fprintf(outf
, "CPUID(1): %s %s %s %s %s %s %s %s %s\n",
3994 ecx
& (1 << 0) ? "SSE3" : "-",
3995 ecx
& (1 << 3) ? "MONITOR" : "-",
3996 ecx
& (1 << 6) ? "SMX" : "-",
3997 ecx
& (1 << 7) ? "EIST" : "-",
3998 ecx
& (1 << 8) ? "TM2" : "-",
3999 edx
& (1 << 4) ? "TSC" : "-",
4000 edx
& (1 << 5) ? "MSR" : "-",
4001 edx
& (1 << 22) ? "ACPI-TM" : "-",
4002 edx
& (1 << 29) ? "TM" : "-");
4005 if (!(edx
& (1 << 5)))
4006 errx(1, "CPUID: no MSR");
4009 * check max extended function levels of CPUID.
4010 * This is needed to check for invariant TSC.
4011 * This check is valid for both Intel and AMD.
4013 ebx
= ecx
= edx
= 0;
4014 __cpuid(0x80000000, max_extended_level
, ebx
, ecx
, edx
);
4016 if (max_extended_level
>= 0x80000007) {
4019 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8
4020 * this check is valid for both Intel and AMD
4022 __cpuid(0x80000007, eax
, ebx
, ecx
, edx
);
4023 has_invariant_tsc
= edx
& (1 << 8);
4027 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0
4028 * this check is valid for both Intel and AMD
4031 __cpuid(0x6, eax
, ebx
, ecx
, edx
);
4032 has_aperf
= ecx
& (1 << 0);
4034 BIC_PRESENT(BIC_Avg_MHz
);
4035 BIC_PRESENT(BIC_Busy
);
4036 BIC_PRESENT(BIC_Bzy_MHz
);
4038 do_dts
= eax
& (1 << 0);
4040 BIC_PRESENT(BIC_CoreTmp
);
4041 has_turbo
= eax
& (1 << 1);
4042 do_ptm
= eax
& (1 << 6);
4044 BIC_PRESENT(BIC_PkgTmp
);
4045 has_hwp
= eax
& (1 << 7);
4046 has_hwp_notify
= eax
& (1 << 8);
4047 has_hwp_activity_window
= eax
& (1 << 9);
4048 has_hwp_epp
= eax
& (1 << 10);
4049 has_hwp_pkg
= eax
& (1 << 11);
4050 has_epb
= ecx
& (1 << 3);
4053 fprintf(outf
, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, "
4054 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n",
4055 has_aperf
? "" : "No-",
4056 has_turbo
? "" : "No-",
4057 do_dts
? "" : "No-",
4058 do_ptm
? "" : "No-",
4059 has_hwp
? "" : "No-",
4060 has_hwp_notify
? "" : "No-",
4061 has_hwp_activity_window
? "" : "No-",
4062 has_hwp_epp
? "" : "No-",
4063 has_hwp_pkg
? "" : "No-",
4064 has_epb
? "" : "No-");
4067 decode_misc_enable_msr();
4070 if (max_level
>= 0x7 && !quiet
) {
4075 __cpuid_count(0x7, 0, eax
, ebx
, ecx
, edx
);
4077 has_sgx
= ebx
& (1 << 2);
4078 fprintf(outf
, "CPUID(7): %sSGX\n", has_sgx
? "" : "No-");
4081 decode_feature_control_msr();
4084 if (max_level
>= 0x15) {
4085 unsigned int eax_crystal
;
4086 unsigned int ebx_tsc
;
4089 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz
4091 eax_crystal
= ebx_tsc
= crystal_hz
= edx
= 0;
4092 __cpuid(0x15, eax_crystal
, ebx_tsc
, crystal_hz
, edx
);
4096 if (!quiet
&& (ebx
!= 0))
4097 fprintf(outf
, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n",
4098 eax_crystal
, ebx_tsc
, crystal_hz
);
4100 if (crystal_hz
== 0)
4102 case INTEL_FAM6_SKYLAKE_MOBILE
: /* SKL */
4103 case INTEL_FAM6_SKYLAKE_DESKTOP
: /* SKL */
4104 case INTEL_FAM6_KABYLAKE_MOBILE
: /* KBL */
4105 case INTEL_FAM6_KABYLAKE_DESKTOP
: /* KBL */
4106 crystal_hz
= 24000000; /* 24.0 MHz */
4108 case INTEL_FAM6_SKYLAKE_X
: /* SKX */
4109 case INTEL_FAM6_ATOM_DENVERTON
: /* DNV */
4110 crystal_hz
= 25000000; /* 25.0 MHz */
4112 case INTEL_FAM6_ATOM_GOLDMONT
: /* BXT */
4113 case INTEL_FAM6_ATOM_GEMINI_LAKE
:
4114 crystal_hz
= 19200000; /* 19.2 MHz */
4121 tsc_hz
= (unsigned long long) crystal_hz
* ebx_tsc
/ eax_crystal
;
4123 fprintf(outf
, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n",
4124 tsc_hz
/ 1000000, crystal_hz
, ebx_tsc
, eax_crystal
);
4128 if (max_level
>= 0x16) {
4129 unsigned int base_mhz
, max_mhz
, bus_mhz
, edx
;
4132 * CPUID 16H Base MHz, Max MHz, Bus MHz
4134 base_mhz
= max_mhz
= bus_mhz
= edx
= 0;
4136 __cpuid(0x16, base_mhz
, max_mhz
, bus_mhz
, edx
);
4138 fprintf(outf
, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n",
4139 base_mhz
, max_mhz
, bus_mhz
);
4143 aperf_mperf_multiplier
= get_aperf_mperf_multiplier(family
, model
);
4145 BIC_PRESENT(BIC_IRQ
);
4146 BIC_PRESENT(BIC_TSC_MHz
);
4148 if (probe_nhm_msrs(family
, model
)) {
4149 do_nhm_platform_info
= 1;
4150 BIC_PRESENT(BIC_CPU_c1
);
4151 BIC_PRESENT(BIC_CPU_c3
);
4152 BIC_PRESENT(BIC_CPU_c6
);
4153 BIC_PRESENT(BIC_SMI
);
4155 do_snb_cstates
= has_snb_msrs(family
, model
);
4158 BIC_PRESENT(BIC_CPU_c7
);
4160 do_irtl_snb
= has_snb_msrs(family
, model
);
4161 if (do_snb_cstates
&& (pkg_cstate_limit
>= PCL__2
))
4162 BIC_PRESENT(BIC_Pkgpc2
);
4163 if (pkg_cstate_limit
>= PCL__3
)
4164 BIC_PRESENT(BIC_Pkgpc3
);
4165 if (pkg_cstate_limit
>= PCL__6
)
4166 BIC_PRESENT(BIC_Pkgpc6
);
4167 if (do_snb_cstates
&& (pkg_cstate_limit
>= PCL__7
))
4168 BIC_PRESENT(BIC_Pkgpc7
);
4169 if (has_slv_msrs(family
, model
)) {
4170 BIC_NOT_PRESENT(BIC_Pkgpc2
);
4171 BIC_NOT_PRESENT(BIC_Pkgpc3
);
4172 BIC_PRESENT(BIC_Pkgpc6
);
4173 BIC_NOT_PRESENT(BIC_Pkgpc7
);
4174 BIC_PRESENT(BIC_Mod_c6
);
4175 use_c1_residency_msr
= 1;
4177 if (is_dnv(family
, model
)) {
4178 BIC_PRESENT(BIC_CPU_c1
);
4179 BIC_NOT_PRESENT(BIC_CPU_c3
);
4180 BIC_NOT_PRESENT(BIC_Pkgpc3
);
4181 BIC_NOT_PRESENT(BIC_CPU_c7
);
4182 BIC_NOT_PRESENT(BIC_Pkgpc7
);
4183 use_c1_residency_msr
= 1;
4185 if (is_skx(family
, model
)) {
4186 BIC_NOT_PRESENT(BIC_CPU_c3
);
4187 BIC_NOT_PRESENT(BIC_Pkgpc3
);
4188 BIC_NOT_PRESENT(BIC_CPU_c7
);
4189 BIC_NOT_PRESENT(BIC_Pkgpc7
);
4191 if (is_bdx(family
, model
)) {
4192 BIC_NOT_PRESENT(BIC_CPU_c7
);
4193 BIC_NOT_PRESENT(BIC_Pkgpc7
);
4195 if (has_hsw_msrs(family
, model
)) {
4196 BIC_PRESENT(BIC_Pkgpc8
);
4197 BIC_PRESENT(BIC_Pkgpc9
);
4198 BIC_PRESENT(BIC_Pkgpc10
);
4200 do_irtl_hsw
= has_hsw_msrs(family
, model
);
4201 do_skl_residency
= has_skl_msrs(family
, model
);
4202 do_slm_cstates
= is_slm(family
, model
);
4203 do_knl_cstates
= is_knl(family
, model
);
4206 decode_misc_pwr_mgmt_msr();
4208 if (!quiet
&& has_slv_msrs(family
, model
))
4209 decode_c6_demotion_policy_msr();
4211 rapl_probe(family
, model
);
4212 perf_limit_reasons_probe(family
, model
);
4215 dump_cstate_pstate_config_info(family
, model
);
4218 dump_sysfs_cstate_config();
4220 dump_sysfs_pstate_config();
4222 if (has_skl_msrs(family
, model
))
4223 calculate_tsc_tweak();
4225 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK
))
4226 BIC_PRESENT(BIC_GFX_rc6
);
4228 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK
))
4229 BIC_PRESENT(BIC_GFXMHz
);
4232 decode_misc_feature_control();
4239 * in /dev/cpu/ return success for names that are numbers
4240 * ie. filter out ".", "..", "microcode".
4242 int dir_filter(const struct dirent
*dirp
)
4244 if (isdigit(dirp
->d_name
[0]))
4250 int open_dev_cpu_msr(int dummy1
)
4255 void topology_probe()
4258 int max_core_id
= 0;
4259 int max_package_id
= 0;
4260 int max_siblings
= 0;
4261 struct cpu_topology
{
4263 int physical_package_id
;
4266 /* Initialize num_cpus, max_cpu_num */
4268 topo
.max_cpu_num
= 0;
4269 for_all_proc_cpus(count_cpus
);
4270 if (!summary_only
&& topo
.num_cpus
> 1)
4271 BIC_PRESENT(BIC_CPU
);
4274 fprintf(outf
, "num_cpus %d max_cpu_num %d\n", topo
.num_cpus
, topo
.max_cpu_num
);
4276 cpus
= calloc(1, (topo
.max_cpu_num
+ 1) * sizeof(struct cpu_topology
));
4278 err(1, "calloc cpus");
4281 * Allocate and initialize cpu_present_set
4283 cpu_present_set
= CPU_ALLOC((topo
.max_cpu_num
+ 1));
4284 if (cpu_present_set
== NULL
)
4285 err(3, "CPU_ALLOC");
4286 cpu_present_setsize
= CPU_ALLOC_SIZE((topo
.max_cpu_num
+ 1));
4287 CPU_ZERO_S(cpu_present_setsize
, cpu_present_set
);
4288 for_all_proc_cpus(mark_cpu_present
);
4291 * Validate that all cpus in cpu_subset are also in cpu_present_set
4293 for (i
= 0; i
< CPU_SUBSET_MAXCPUS
; ++i
) {
4294 if (CPU_ISSET_S(i
, cpu_subset_size
, cpu_subset
))
4295 if (!CPU_ISSET_S(i
, cpu_present_setsize
, cpu_present_set
))
4296 err(1, "cpu%d not present", i
);
4300 * Allocate and initialize cpu_affinity_set
4302 cpu_affinity_set
= CPU_ALLOC((topo
.max_cpu_num
+ 1));
4303 if (cpu_affinity_set
== NULL
)
4304 err(3, "CPU_ALLOC");
4305 cpu_affinity_setsize
= CPU_ALLOC_SIZE((topo
.max_cpu_num
+ 1));
4306 CPU_ZERO_S(cpu_affinity_setsize
, cpu_affinity_set
);
4311 * find max_core_id, max_package_id
4313 for (i
= 0; i
<= topo
.max_cpu_num
; ++i
) {
4316 if (cpu_is_not_present(i
)) {
4318 fprintf(outf
, "cpu%d NOT PRESENT\n", i
);
4321 cpus
[i
].core_id
= get_core_id(i
);
4322 if (cpus
[i
].core_id
> max_core_id
)
4323 max_core_id
= cpus
[i
].core_id
;
4325 cpus
[i
].physical_package_id
= get_physical_package_id(i
);
4326 if (cpus
[i
].physical_package_id
> max_package_id
)
4327 max_package_id
= cpus
[i
].physical_package_id
;
4329 siblings
= get_num_ht_siblings(i
);
4330 if (siblings
> max_siblings
)
4331 max_siblings
= siblings
;
4333 fprintf(outf
, "cpu %d pkg %d core %d\n",
4334 i
, cpus
[i
].physical_package_id
, cpus
[i
].core_id
);
4336 topo
.num_cores_per_pkg
= max_core_id
+ 1;
4338 fprintf(outf
, "max_core_id %d, sizing for %d cores per package\n",
4339 max_core_id
, topo
.num_cores_per_pkg
);
4340 if (!summary_only
&& topo
.num_cores_per_pkg
> 1)
4341 BIC_PRESENT(BIC_Core
);
4343 topo
.num_packages
= max_package_id
+ 1;
4345 fprintf(outf
, "max_package_id %d, sizing for %d packages\n",
4346 max_package_id
, topo
.num_packages
);
4347 if (!summary_only
&& topo
.num_packages
> 1)
4348 BIC_PRESENT(BIC_Package
);
4350 topo
.num_threads_per_core
= max_siblings
;
4352 fprintf(outf
, "max_siblings %d\n", max_siblings
);
4358 allocate_counters(struct thread_data
**t
, struct core_data
**c
, struct pkg_data
**p
)
4362 *t
= calloc(topo
.num_threads_per_core
* topo
.num_cores_per_pkg
*
4363 topo
.num_packages
, sizeof(struct thread_data
));
4367 for (i
= 0; i
< topo
.num_threads_per_core
*
4368 topo
.num_cores_per_pkg
* topo
.num_packages
; i
++)
4369 (*t
)[i
].cpu_id
= -1;
4371 *c
= calloc(topo
.num_cores_per_pkg
* topo
.num_packages
,
4372 sizeof(struct core_data
));
4376 for (i
= 0; i
< topo
.num_cores_per_pkg
* topo
.num_packages
; i
++)
4377 (*c
)[i
].core_id
= -1;
4379 *p
= calloc(topo
.num_packages
, sizeof(struct pkg_data
));
4383 for (i
= 0; i
< topo
.num_packages
; i
++)
4384 (*p
)[i
].package_id
= i
;
4388 err(1, "calloc counters");
4393 * set cpu_id, core_num, pkg_num
4394 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE
4396 * increment topo.num_cores when 1st core in pkg seen
4398 void init_counter(struct thread_data
*thread_base
, struct core_data
*core_base
,
4399 struct pkg_data
*pkg_base
, int thread_num
, int core_num
,
4400 int pkg_num
, int cpu_id
)
4402 struct thread_data
*t
;
4403 struct core_data
*c
;
4406 t
= GET_THREAD(thread_base
, thread_num
, core_num
, pkg_num
);
4407 c
= GET_CORE(core_base
, core_num
, pkg_num
);
4408 p
= GET_PKG(pkg_base
, pkg_num
);
4411 if (thread_num
== 0) {
4412 t
->flags
|= CPU_IS_FIRST_THREAD_IN_CORE
;
4413 if (cpu_is_first_core_in_package(cpu_id
))
4414 t
->flags
|= CPU_IS_FIRST_CORE_IN_PACKAGE
;
4417 c
->core_id
= core_num
;
4418 p
->package_id
= pkg_num
;
4422 int initialize_counters(int cpu_id
)
4424 int my_thread_id
, my_core_id
, my_package_id
;
4426 my_package_id
= get_physical_package_id(cpu_id
);
4427 my_core_id
= get_core_id(cpu_id
);
4428 my_thread_id
= get_cpu_position_in_core(cpu_id
);
4432 init_counter(EVEN_COUNTERS
, my_thread_id
, my_core_id
, my_package_id
, cpu_id
);
4433 init_counter(ODD_COUNTERS
, my_thread_id
, my_core_id
, my_package_id
, cpu_id
);
4437 void allocate_output_buffer()
4439 output_buffer
= calloc(1, (1 + topo
.num_cpus
) * 1024);
4440 outp
= output_buffer
;
4442 err(-1, "calloc output buffer");
4444 void allocate_fd_percpu(void)
4446 fd_percpu
= calloc(topo
.max_cpu_num
+ 1, sizeof(int));
4447 if (fd_percpu
== NULL
)
4448 err(-1, "calloc fd_percpu");
4450 void allocate_irq_buffers(void)
4452 irq_column_2_cpu
= calloc(topo
.num_cpus
, sizeof(int));
4453 if (irq_column_2_cpu
== NULL
)
4454 err(-1, "calloc %d", topo
.num_cpus
);
4456 irqs_per_cpu
= calloc(topo
.max_cpu_num
+ 1, sizeof(int));
4457 if (irqs_per_cpu
== NULL
)
4458 err(-1, "calloc %d", topo
.max_cpu_num
+ 1);
4460 void setup_all_buffers(void)
4463 allocate_irq_buffers();
4464 allocate_fd_percpu();
4465 allocate_counters(&thread_even
, &core_even
, &package_even
);
4466 allocate_counters(&thread_odd
, &core_odd
, &package_odd
);
4467 allocate_output_buffer();
4468 for_all_proc_cpus(initialize_counters
);
4471 void set_base_cpu(void)
4473 base_cpu
= sched_getcpu();
4475 err(-ENODEV
, "No valid cpus found");
4478 fprintf(outf
, "base_cpu = %d\n", base_cpu
);
4481 void turbostat_init()
4483 setup_all_buffers();
4486 check_permissions();
4491 for_all_cpus(print_hwp
, ODD_COUNTERS
);
4494 for_all_cpus(print_epb
, ODD_COUNTERS
);
4497 for_all_cpus(print_perf_limit
, ODD_COUNTERS
);
4500 for_all_cpus(print_rapl
, ODD_COUNTERS
);
4502 for_all_cpus(set_temperature_target
, ODD_COUNTERS
);
4505 for_all_cpus(print_thermal
, ODD_COUNTERS
);
4507 if (!quiet
&& do_irtl_snb
)
4511 int fork_it(char **argv
)
4516 snapshot_proc_sysfs_files();
4517 status
= for_all_cpus(get_counters
, EVEN_COUNTERS
);
4520 /* clear affinity side-effect of get_counters() */
4521 sched_setaffinity(0, cpu_present_setsize
, cpu_present_set
);
4522 gettimeofday(&tv_even
, (struct timezone
*)NULL
);
4527 execvp(argv
[0], argv
);
4528 err(errno
, "exec %s", argv
[0]);
4532 if (child_pid
== -1)
4535 signal(SIGINT
, SIG_IGN
);
4536 signal(SIGQUIT
, SIG_IGN
);
4537 if (waitpid(child_pid
, &status
, 0) == -1)
4538 err(status
, "waitpid");
4541 * n.b. fork_it() does not check for errors from for_all_cpus()
4542 * because re-starting is problematic when forking
4544 snapshot_proc_sysfs_files();
4545 for_all_cpus(get_counters
, ODD_COUNTERS
);
4546 gettimeofday(&tv_odd
, (struct timezone
*)NULL
);
4547 timersub(&tv_odd
, &tv_even
, &tv_delta
);
4548 if (for_all_cpus_2(delta_cpu
, ODD_COUNTERS
, EVEN_COUNTERS
))
4549 fprintf(outf
, "%s: Counter reset detected\n", progname
);
4551 compute_average(EVEN_COUNTERS
);
4552 format_all_counters(EVEN_COUNTERS
);
4555 fprintf(outf
, "%.6f sec\n", tv_delta
.tv_sec
+ tv_delta
.tv_usec
/1000000.0);
4557 flush_output_stderr();
4562 int get_and_dump_counters(void)
4566 snapshot_proc_sysfs_files();
4567 status
= for_all_cpus(get_counters
, ODD_COUNTERS
);
4571 status
= for_all_cpus(dump_counters
, ODD_COUNTERS
);
4575 flush_output_stdout();
4580 void print_version() {
4581 fprintf(outf
, "turbostat version 17.04.12"
4582 " - Len Brown <lenb@kernel.org>\n");
4585 int add_counter(unsigned int msr_num
, char *path
, char *name
,
4586 unsigned int width
, enum counter_scope scope
,
4587 enum counter_type type
, enum counter_format format
, int flags
)
4589 struct msr_counter
*msrp
;
4591 msrp
= calloc(1, sizeof(struct msr_counter
));
4597 msrp
->msr_num
= msr_num
;
4598 strncpy(msrp
->name
, name
, NAME_BYTES
);
4600 strncpy(msrp
->path
, path
, PATH_BYTES
);
4601 msrp
->width
= width
;
4603 msrp
->format
= format
;
4604 msrp
->flags
= flags
;
4609 msrp
->next
= sys
.tp
;
4611 sys
.added_thread_counters
++;
4612 if (sys
.added_thread_counters
> MAX_ADDED_COUNTERS
) {
4613 fprintf(stderr
, "exceeded max %d added thread counters\n",
4614 MAX_ADDED_COUNTERS
);
4620 msrp
->next
= sys
.cp
;
4622 sys
.added_core_counters
++;
4623 if (sys
.added_core_counters
> MAX_ADDED_COUNTERS
) {
4624 fprintf(stderr
, "exceeded max %d added core counters\n",
4625 MAX_ADDED_COUNTERS
);
4631 msrp
->next
= sys
.pp
;
4633 sys
.added_package_counters
++;
4634 if (sys
.added_package_counters
> MAX_ADDED_COUNTERS
) {
4635 fprintf(stderr
, "exceeded max %d added package counters\n",
4636 MAX_ADDED_COUNTERS
);
4645 void parse_add_command(char *add_command
)
4649 char name_buffer
[NAME_BYTES
] = "";
4652 enum counter_scope scope
= SCOPE_CPU
;
4653 enum counter_type type
= COUNTER_CYCLES
;
4654 enum counter_format format
= FORMAT_DELTA
;
4656 while (add_command
) {
4658 if (sscanf(add_command
, "msr0x%x", &msr_num
) == 1)
4661 if (sscanf(add_command
, "msr%d", &msr_num
) == 1)
4664 if (*add_command
== '/') {
4669 if (sscanf(add_command
, "u%d", &width
) == 1) {
4670 if ((width
== 32) || (width
== 64))
4674 if (!strncmp(add_command
, "cpu", strlen("cpu"))) {
4678 if (!strncmp(add_command
, "core", strlen("core"))) {
4682 if (!strncmp(add_command
, "package", strlen("package"))) {
4683 scope
= SCOPE_PACKAGE
;
4686 if (!strncmp(add_command
, "cycles", strlen("cycles"))) {
4687 type
= COUNTER_CYCLES
;
4690 if (!strncmp(add_command
, "seconds", strlen("seconds"))) {
4691 type
= COUNTER_SECONDS
;
4694 if (!strncmp(add_command
, "usec", strlen("usec"))) {
4695 type
= COUNTER_USEC
;
4698 if (!strncmp(add_command
, "raw", strlen("raw"))) {
4699 format
= FORMAT_RAW
;
4702 if (!strncmp(add_command
, "delta", strlen("delta"))) {
4703 format
= FORMAT_DELTA
;
4706 if (!strncmp(add_command
, "percent", strlen("percent"))) {
4707 format
= FORMAT_PERCENT
;
4711 if (sscanf(add_command
, "%18s,%*s", name_buffer
) == 1) { /* 18 < NAME_BYTES */
4714 eos
= strchr(name_buffer
, ',');
4721 add_command
= strchr(add_command
, ',');
4723 *add_command
= '\0';
4728 if ((msr_num
== 0) && (path
== NULL
)) {
4729 fprintf(stderr
, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n");
4733 /* generate default column header */
4734 if (*name_buffer
== '\0') {
4736 sprintf(name_buffer
, "M0x%x%s", msr_num
, format
== FORMAT_PERCENT
? "%" : "");
4738 sprintf(name_buffer
, "M0X%x%s", msr_num
, format
== FORMAT_PERCENT
? "%" : "");
4741 if (add_counter(msr_num
, path
, name_buffer
, width
, scope
, type
, format
, 0))
4750 int is_deferred_skip(char *name
)
4754 for (i
= 0; i
< deferred_skip_index
; ++i
)
4755 if (!strcmp(name
, deferred_skip_names
[i
]))
4760 void probe_sysfs(void)
4768 if (!DO_BIC(BIC_sysfs
))
4771 for (state
= 10; state
> 0; --state
) {
4773 sprintf(path
, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name",
4775 input
= fopen(path
, "r");
4778 fgets(name_buf
, sizeof(name_buf
), input
);
4780 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
4781 sp
= strchr(name_buf
, '-');
4783 sp
= strchrnul(name_buf
, '\n');
4789 sprintf(path
, "cpuidle/state%d/time", state
);
4791 if (is_deferred_skip(name_buf
))
4794 add_counter(0, path
, name_buf
, 64, SCOPE_CPU
, COUNTER_USEC
,
4795 FORMAT_PERCENT
, SYSFS_PERCPU
);
4798 for (state
= 10; state
> 0; --state
) {
4800 sprintf(path
, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name",
4802 input
= fopen(path
, "r");
4805 fgets(name_buf
, sizeof(name_buf
), input
);
4806 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
4807 sp
= strchr(name_buf
, '-');
4809 sp
= strchrnul(name_buf
, '\n');
4813 sprintf(path
, "cpuidle/state%d/usage", state
);
4815 if (is_deferred_skip(name_buf
))
4818 add_counter(0, path
, name_buf
, 64, SCOPE_CPU
, COUNTER_ITEMS
,
4819 FORMAT_DELTA
, SYSFS_PERCPU
);
4826 * parse cpuset with following syntax
4827 * 1,2,4..6,8-10 and set bits in cpu_subset
4829 void parse_cpu_command(char *optarg
)
4831 unsigned int start
, end
;
4834 if (!strcmp(optarg
, "core")) {
4840 if (!strcmp(optarg
, "package")) {
4846 if (show_core_only
|| show_pkg_only
)
4849 cpu_subset
= CPU_ALLOC(CPU_SUBSET_MAXCPUS
);
4850 if (cpu_subset
== NULL
)
4851 err(3, "CPU_ALLOC");
4852 cpu_subset_size
= CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS
);
4854 CPU_ZERO_S(cpu_subset_size
, cpu_subset
);
4858 while (next
&& *next
) {
4860 if (*next
== '-') /* no negative cpu numbers */
4863 start
= strtoul(next
, &next
, 10);
4865 if (start
>= CPU_SUBSET_MAXCPUS
)
4867 CPU_SET_S(start
, cpu_subset_size
, cpu_subset
);
4878 next
+= 1; /* start range */
4879 } else if (*next
== '.') {
4882 next
+= 1; /* start range */
4887 end
= strtoul(next
, &next
, 10);
4891 while (++start
<= end
) {
4892 if (start
>= CPU_SUBSET_MAXCPUS
)
4894 CPU_SET_S(start
, cpu_subset_size
, cpu_subset
);
4899 else if (*next
!= '\0')
4906 fprintf(stderr
, "\"--cpu %s\" malformed\n", optarg
);
4913 * parse_show_hide() - process cmdline to set default counter action
4915 void parse_show_hide(char *optarg
, enum show_hide_mode new_mode
)
4918 * --show: show only those specified
4919 * The 1st invocation will clear and replace the enabled mask
4920 * subsequent invocations can add to it.
4922 if (new_mode
== SHOW_LIST
) {
4924 bic_enabled
= bic_lookup(optarg
, new_mode
);
4926 bic_enabled
|= bic_lookup(optarg
, new_mode
);
4933 * --hide: do not show those specified
4934 * multiple invocations simply clear more bits in enabled mask
4936 bic_enabled
&= ~bic_lookup(optarg
, new_mode
);
4940 void cmdline(int argc
, char **argv
)
4943 int option_index
= 0;
4944 static struct option long_options
[] = {
4945 {"add", required_argument
, 0, 'a'},
4946 {"cpu", required_argument
, 0, 'c'},
4947 {"Dump", no_argument
, 0, 'D'},
4948 {"debug", no_argument
, 0, 'd'}, /* internal, not documented */
4949 {"interval", required_argument
, 0, 'i'},
4950 {"help", no_argument
, 0, 'h'},
4951 {"hide", required_argument
, 0, 'H'}, // meh, -h taken by --help
4952 {"Joules", no_argument
, 0, 'J'},
4953 {"list", no_argument
, 0, 'l'},
4954 {"out", required_argument
, 0, 'o'},
4955 {"quiet", no_argument
, 0, 'q'},
4956 {"show", required_argument
, 0, 's'},
4957 {"Summary", no_argument
, 0, 'S'},
4958 {"TCC", required_argument
, 0, 'T'},
4959 {"version", no_argument
, 0, 'v' },
4965 while ((opt
= getopt_long_only(argc
, argv
, "+C:c:Ddhi:JM:m:o:qST:v",
4966 long_options
, &option_index
)) != -1) {
4969 parse_add_command(optarg
);
4972 parse_cpu_command(optarg
);
4981 parse_show_hide(optarg
, HIDE_LIST
);
4989 double interval
= strtod(optarg
, NULL
);
4991 if (interval
< 0.001) {
4992 fprintf(outf
, "interval %f seconds is too small\n",
4997 interval_ts
.tv_sec
= interval
;
4998 interval_ts
.tv_nsec
= (interval
- interval_ts
.tv_sec
) * 1000000000;
5009 outf
= fopen_or_die(optarg
, "w");
5015 parse_show_hide(optarg
, SHOW_LIST
);
5021 tcc_activation_temp_override
= atoi(optarg
);
5031 int main(int argc
, char **argv
)
5035 cmdline(argc
, argv
);
5044 /* dump counters and exit */
5046 return get_and_dump_counters();
5048 /* list header and exit */
5049 if (list_header_only
) {
5051 flush_output_stdout();
5056 * if any params left, it must be a command to fork
5059 return fork_it(argv
+ optind
);