4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include <sys/types.h>
33 #include "qemu-common.h"
34 #define NO_CPU_IO_DEFS
37 #include "disas/disas.h"
39 #if defined(CONFIG_USER_ONLY)
41 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
42 #include <sys/param.h>
43 #if __FreeBSD_version >= 700104
44 #define HAVE_KINFO_GETVMMAP
45 #define sigqueue sigqueue_freebsd /* avoid redefinition */
48 #include <machine/profile.h>
57 #include "exec/address-spaces.h"
60 #include "exec/cputlb.h"
61 #include "translate-all.h"
62 #include "qemu/bitmap.h"
63 #include "qemu/timer.h"
65 //#define DEBUG_TB_INVALIDATE
67 /* make various TB consistency checks */
68 //#define DEBUG_TB_CHECK
70 #if !defined(CONFIG_USER_ONLY)
71 /* TB consistency checks only implemented for usermode emulation. */
75 #define SMC_BITMAP_USE_THRESHOLD 10
77 typedef struct PageDesc
{
78 /* list of TBs intersecting this ram page */
79 TranslationBlock
*first_tb
;
80 /* in order to optimize self modifying code, we count the number
81 of lookups we do to a given page to use a bitmap */
82 unsigned int code_write_count
;
83 unsigned long *code_bitmap
;
84 #if defined(CONFIG_USER_ONLY)
89 /* In system mode we want L1_MAP to be based on ram offsets,
90 while in user mode we want it to be based on virtual addresses. */
91 #if !defined(CONFIG_USER_ONLY)
92 #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS
93 # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS
95 # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS
98 # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS
101 /* Size of the L2 (and L3, etc) page tables. */
103 #define V_L2_SIZE (1 << V_L2_BITS)
105 /* The bits remaining after N lower levels of page tables. */
106 #define V_L1_BITS_REM \
107 ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % V_L2_BITS)
109 #if V_L1_BITS_REM < 4
110 #define V_L1_BITS (V_L1_BITS_REM + V_L2_BITS)
112 #define V_L1_BITS V_L1_BITS_REM
115 #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS)
117 #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS)
119 uintptr_t qemu_real_host_page_size
;
120 uintptr_t qemu_host_page_size
;
121 uintptr_t qemu_host_page_mask
;
123 /* This is a multi-level map on the virtual address space.
124 The bottom level has pointers to PageDesc. */
125 static void *l1_map
[V_L1_SIZE
];
127 /* code generation context */
130 static void tb_link_page(TranslationBlock
*tb
, tb_page_addr_t phys_pc
,
131 tb_page_addr_t phys_page2
);
132 static TranslationBlock
*tb_find_pc(uintptr_t tc_ptr
);
134 void cpu_gen_init(void)
136 tcg_context_init(&tcg_ctx
);
139 /* return non zero if the very first instruction is invalid so that
140 the virtual CPU can trigger an exception.
142 '*gen_code_size_ptr' contains the size of the generated code (host
145 int cpu_gen_code(CPUArchState
*env
, TranslationBlock
*tb
, int *gen_code_size_ptr
)
147 TCGContext
*s
= &tcg_ctx
;
148 tcg_insn_unit
*gen_code_buf
;
150 #ifdef CONFIG_PROFILER
154 #ifdef CONFIG_PROFILER
155 s
->tb_count1
++; /* includes aborted translations because of
157 ti
= profile_getclock();
161 gen_intermediate_code(env
, tb
);
163 trace_translate_block(tb
, tb
->pc
, tb
->tc_ptr
);
165 /* generate machine code */
166 gen_code_buf
= tb
->tc_ptr
;
167 tb
->tb_next_offset
[0] = 0xffff;
168 tb
->tb_next_offset
[1] = 0xffff;
169 s
->tb_next_offset
= tb
->tb_next_offset
;
170 #ifdef USE_DIRECT_JUMP
171 s
->tb_jmp_offset
= tb
->tb_jmp_offset
;
174 s
->tb_jmp_offset
= NULL
;
175 s
->tb_next
= tb
->tb_next
;
178 #ifdef CONFIG_PROFILER
180 s
->interm_time
+= profile_getclock() - ti
;
181 s
->code_time
-= profile_getclock();
183 gen_code_size
= tcg_gen_code(s
, gen_code_buf
);
184 *gen_code_size_ptr
= gen_code_size
;
185 #ifdef CONFIG_PROFILER
186 s
->code_time
+= profile_getclock();
187 s
->code_in_len
+= tb
->size
;
188 s
->code_out_len
+= gen_code_size
;
192 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM
)) {
193 qemu_log("OUT: [size=%d]\n", gen_code_size
);
194 log_disas(tb
->tc_ptr
, gen_code_size
);
202 /* The cpu state corresponding to 'searched_pc' is restored.
204 static int cpu_restore_state_from_tb(CPUState
*cpu
, TranslationBlock
*tb
,
205 uintptr_t searched_pc
)
207 CPUArchState
*env
= cpu
->env_ptr
;
208 TCGContext
*s
= &tcg_ctx
;
211 #ifdef CONFIG_PROFILER
215 #ifdef CONFIG_PROFILER
216 ti
= profile_getclock();
220 gen_intermediate_code_pc(env
, tb
);
222 if (tb
->cflags
& CF_USE_ICOUNT
) {
223 /* Reset the cycle counter to the start of the block. */
224 cpu
->icount_decr
.u16
.low
+= tb
->icount
;
225 /* Clear the IO flag. */
229 /* find opc index corresponding to search_pc */
230 tc_ptr
= (uintptr_t)tb
->tc_ptr
;
231 if (searched_pc
< tc_ptr
)
234 s
->tb_next_offset
= tb
->tb_next_offset
;
235 #ifdef USE_DIRECT_JUMP
236 s
->tb_jmp_offset
= tb
->tb_jmp_offset
;
239 s
->tb_jmp_offset
= NULL
;
240 s
->tb_next
= tb
->tb_next
;
242 j
= tcg_gen_code_search_pc(s
, (tcg_insn_unit
*)tc_ptr
,
243 searched_pc
- tc_ptr
);
246 /* now find start of instruction before */
247 while (s
->gen_opc_instr_start
[j
] == 0) {
250 cpu
->icount_decr
.u16
.low
-= s
->gen_opc_icount
[j
];
252 restore_state_to_opc(env
, tb
, j
);
254 #ifdef CONFIG_PROFILER
255 s
->restore_time
+= profile_getclock() - ti
;
261 bool cpu_restore_state(CPUState
*cpu
, uintptr_t retaddr
)
263 TranslationBlock
*tb
;
265 tb
= tb_find_pc(retaddr
);
267 cpu_restore_state_from_tb(cpu
, tb
, retaddr
);
268 if (tb
->cflags
& CF_NOCACHE
) {
269 /* one-shot translation, invalidate it immediately */
270 cpu
->current_tb
= NULL
;
271 tb_phys_invalidate(tb
, -1);
280 static __attribute__((unused
)) void map_exec(void *addr
, long size
)
283 VirtualProtect(addr
, size
,
284 PAGE_EXECUTE_READWRITE
, &old_protect
);
287 static __attribute__((unused
)) void map_exec(void *addr
, long size
)
289 unsigned long start
, end
, page_size
;
291 page_size
= getpagesize();
292 start
= (unsigned long)addr
;
293 start
&= ~(page_size
- 1);
295 end
= (unsigned long)addr
+ size
;
296 end
+= page_size
- 1;
297 end
&= ~(page_size
- 1);
299 mprotect((void *)start
, end
- start
,
300 PROT_READ
| PROT_WRITE
| PROT_EXEC
);
304 void page_size_init(void)
306 /* NOTE: we can always suppose that qemu_host_page_size >=
308 qemu_real_host_page_size
= getpagesize();
309 if (qemu_host_page_size
== 0) {
310 qemu_host_page_size
= qemu_real_host_page_size
;
312 if (qemu_host_page_size
< TARGET_PAGE_SIZE
) {
313 qemu_host_page_size
= TARGET_PAGE_SIZE
;
315 qemu_host_page_mask
= ~(qemu_host_page_size
- 1);
318 static void page_init(void)
321 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
323 #ifdef HAVE_KINFO_GETVMMAP
324 struct kinfo_vmentry
*freep
;
327 freep
= kinfo_getvmmap(getpid(), &cnt
);
330 for (i
= 0; i
< cnt
; i
++) {
331 unsigned long startaddr
, endaddr
;
333 startaddr
= freep
[i
].kve_start
;
334 endaddr
= freep
[i
].kve_end
;
335 if (h2g_valid(startaddr
)) {
336 startaddr
= h2g(startaddr
) & TARGET_PAGE_MASK
;
338 if (h2g_valid(endaddr
)) {
339 endaddr
= h2g(endaddr
);
340 page_set_flags(startaddr
, endaddr
, PAGE_RESERVED
);
342 #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS
344 page_set_flags(startaddr
, endaddr
, PAGE_RESERVED
);
355 last_brk
= (unsigned long)sbrk(0);
357 f
= fopen("/compat/linux/proc/self/maps", "r");
362 unsigned long startaddr
, endaddr
;
365 n
= fscanf(f
, "%lx-%lx %*[^\n]\n", &startaddr
, &endaddr
);
367 if (n
== 2 && h2g_valid(startaddr
)) {
368 startaddr
= h2g(startaddr
) & TARGET_PAGE_MASK
;
370 if (h2g_valid(endaddr
)) {
371 endaddr
= h2g(endaddr
);
375 page_set_flags(startaddr
, endaddr
, PAGE_RESERVED
);
387 static PageDesc
*page_find_alloc(tb_page_addr_t index
, int alloc
)
393 /* Level 1. Always allocated. */
394 lp
= l1_map
+ ((index
>> V_L1_SHIFT
) & (V_L1_SIZE
- 1));
397 for (i
= V_L1_SHIFT
/ V_L2_BITS
- 1; i
> 0; i
--) {
404 p
= g_new0(void *, V_L2_SIZE
);
408 lp
= p
+ ((index
>> (i
* V_L2_BITS
)) & (V_L2_SIZE
- 1));
416 pd
= g_new0(PageDesc
, V_L2_SIZE
);
420 return pd
+ (index
& (V_L2_SIZE
- 1));
423 static inline PageDesc
*page_find(tb_page_addr_t index
)
425 return page_find_alloc(index
, 0);
428 #if !defined(CONFIG_USER_ONLY)
429 #define mmap_lock() do { } while (0)
430 #define mmap_unlock() do { } while (0)
433 #if defined(CONFIG_USER_ONLY)
434 /* Currently it is not recommended to allocate big chunks of data in
435 user mode. It will change when a dedicated libc will be used. */
436 /* ??? 64-bit hosts ought to have no problem mmaping data outside the
437 region in which the guest needs to run. Revisit this. */
438 #define USE_STATIC_CODE_GEN_BUFFER
441 /* ??? Should configure for this, not list operating systems here. */
442 #if (defined(__linux__) \
443 || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \
444 || defined(__DragonFly__) || defined(__OpenBSD__) \
445 || defined(__NetBSD__))
449 /* Minimum size of the code gen buffer. This number is randomly chosen,
450 but not so small that we can't have a fair number of TB's live. */
451 #define MIN_CODE_GEN_BUFFER_SIZE (1024u * 1024)
453 /* Maximum size of the code gen buffer we'd like to use. Unless otherwise
454 indicated, this is constrained by the range of direct branches on the
455 host cpu, as used by the TCG implementation of goto_tb. */
456 #if defined(__x86_64__)
457 # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024)
458 #elif defined(__sparc__)
459 # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024)
460 #elif defined(__aarch64__)
461 # define MAX_CODE_GEN_BUFFER_SIZE (128ul * 1024 * 1024)
462 #elif defined(__arm__)
463 # define MAX_CODE_GEN_BUFFER_SIZE (16u * 1024 * 1024)
464 #elif defined(__s390x__)
465 /* We have a +- 4GB range on the branches; leave some slop. */
466 # define MAX_CODE_GEN_BUFFER_SIZE (3ul * 1024 * 1024 * 1024)
467 #elif defined(__mips__)
468 /* We have a 256MB branch region, but leave room to make sure the
469 main executable is also within that region. */
470 # define MAX_CODE_GEN_BUFFER_SIZE (128ul * 1024 * 1024)
472 # define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
475 #define DEFAULT_CODE_GEN_BUFFER_SIZE_1 (32u * 1024 * 1024)
477 #define DEFAULT_CODE_GEN_BUFFER_SIZE \
478 (DEFAULT_CODE_GEN_BUFFER_SIZE_1 < MAX_CODE_GEN_BUFFER_SIZE \
479 ? DEFAULT_CODE_GEN_BUFFER_SIZE_1 : MAX_CODE_GEN_BUFFER_SIZE)
481 static inline size_t size_code_gen_buffer(size_t tb_size
)
483 /* Size the buffer. */
485 #ifdef USE_STATIC_CODE_GEN_BUFFER
486 tb_size
= DEFAULT_CODE_GEN_BUFFER_SIZE
;
488 /* ??? Needs adjustments. */
489 /* ??? If we relax the requirement that CONFIG_USER_ONLY use the
490 static buffer, we could size this on RESERVED_VA, on the text
491 segment size of the executable, or continue to use the default. */
492 tb_size
= (unsigned long)(ram_size
/ 4);
495 if (tb_size
< MIN_CODE_GEN_BUFFER_SIZE
) {
496 tb_size
= MIN_CODE_GEN_BUFFER_SIZE
;
498 if (tb_size
> MAX_CODE_GEN_BUFFER_SIZE
) {
499 tb_size
= MAX_CODE_GEN_BUFFER_SIZE
;
501 tcg_ctx
.code_gen_buffer_size
= tb_size
;
506 /* In order to use J and JAL within the code_gen_buffer, we require
507 that the buffer not cross a 256MB boundary. */
508 static inline bool cross_256mb(void *addr
, size_t size
)
510 return ((uintptr_t)addr
^ ((uintptr_t)addr
+ size
)) & 0xf0000000;
513 /* We weren't able to allocate a buffer without crossing that boundary,
514 so make do with the larger portion of the buffer that doesn't cross.
515 Returns the new base of the buffer, and adjusts code_gen_buffer_size. */
516 static inline void *split_cross_256mb(void *buf1
, size_t size1
)
518 void *buf2
= (void *)(((uintptr_t)buf1
+ size1
) & 0xf0000000);
519 size_t size2
= buf1
+ size1
- buf2
;
527 tcg_ctx
.code_gen_buffer_size
= size1
;
532 #ifdef USE_STATIC_CODE_GEN_BUFFER
533 static uint8_t static_code_gen_buffer
[DEFAULT_CODE_GEN_BUFFER_SIZE
]
534 __attribute__((aligned(CODE_GEN_ALIGN
)));
536 static inline void *alloc_code_gen_buffer(void)
538 void *buf
= static_code_gen_buffer
;
540 if (cross_256mb(buf
, tcg_ctx
.code_gen_buffer_size
)) {
541 buf
= split_cross_256mb(buf
, tcg_ctx
.code_gen_buffer_size
);
544 map_exec(buf
, tcg_ctx
.code_gen_buffer_size
);
547 #elif defined(USE_MMAP)
548 static inline void *alloc_code_gen_buffer(void)
550 int flags
= MAP_PRIVATE
| MAP_ANONYMOUS
;
554 /* Constrain the position of the buffer based on the host cpu.
555 Note that these addresses are chosen in concert with the
556 addresses assigned in the relevant linker script file. */
557 # if defined(__PIE__) || defined(__PIC__)
558 /* Don't bother setting a preferred location if we're building
559 a position-independent executable. We're more likely to get
560 an address near the main executable if we let the kernel
561 choose the address. */
562 # elif defined(__x86_64__) && defined(MAP_32BIT)
563 /* Force the memory down into low memory with the executable.
564 Leave the choice of exact location with the kernel. */
566 /* Cannot expect to map more than 800MB in low memory. */
567 if (tcg_ctx
.code_gen_buffer_size
> 800u * 1024 * 1024) {
568 tcg_ctx
.code_gen_buffer_size
= 800u * 1024 * 1024;
570 # elif defined(__sparc__)
571 start
= 0x40000000ul
;
572 # elif defined(__s390x__)
573 start
= 0x90000000ul
;
574 # elif defined(__mips__)
575 /* ??? We ought to more explicitly manage layout for softmmu too. */
576 # ifdef CONFIG_USER_ONLY
577 start
= 0x68000000ul
;
578 # elif _MIPS_SIM == _ABI64
579 start
= 0x128000000ul
;
581 start
= 0x08000000ul
;
585 buf
= mmap((void *)start
, tcg_ctx
.code_gen_buffer_size
,
586 PROT_WRITE
| PROT_READ
| PROT_EXEC
, flags
, -1, 0);
587 if (buf
== MAP_FAILED
) {
592 if (cross_256mb(buf
, tcg_ctx
.code_gen_buffer_size
)) {
593 /* Try again, with the original still mapped, to avoid re-acquiring
594 that 256mb crossing. This time don't specify an address. */
595 size_t size2
, size1
= tcg_ctx
.code_gen_buffer_size
;
596 void *buf2
= mmap(NULL
, size1
, PROT_WRITE
| PROT_READ
| PROT_EXEC
,
598 if (buf2
!= MAP_FAILED
) {
599 if (!cross_256mb(buf2
, size1
)) {
600 /* Success! Use the new buffer. */
604 /* Failure. Work with what we had. */
608 /* Split the original buffer. Free the smaller half. */
609 buf2
= split_cross_256mb(buf
, size1
);
610 size2
= tcg_ctx
.code_gen_buffer_size
;
611 munmap(buf
+ (buf
== buf2
? size2
: 0), size1
- size2
);
619 static inline void *alloc_code_gen_buffer(void)
621 void *buf
= g_try_malloc(tcg_ctx
.code_gen_buffer_size
);
628 if (cross_256mb(buf
, tcg_ctx
.code_gen_buffer_size
)) {
629 void *buf2
= g_malloc(tcg_ctx
.code_gen_buffer_size
);
630 if (buf2
!= NULL
&& !cross_256mb(buf2
, size1
)) {
631 /* Success! Use the new buffer. */
635 /* Failure. Work with what we had. Since this is malloc
636 and not mmap, we can't free the other half. */
638 buf
= split_cross_256mb(buf
, tcg_ctx
.code_gen_buffer_size
);
643 map_exec(buf
, tcg_ctx
.code_gen_buffer_size
);
646 #endif /* USE_STATIC_CODE_GEN_BUFFER, USE_MMAP */
648 static inline void code_gen_alloc(size_t tb_size
)
650 tcg_ctx
.code_gen_buffer_size
= size_code_gen_buffer(tb_size
);
651 tcg_ctx
.code_gen_buffer
= alloc_code_gen_buffer();
652 if (tcg_ctx
.code_gen_buffer
== NULL
) {
653 fprintf(stderr
, "Could not allocate dynamic translator buffer\n");
657 qemu_madvise(tcg_ctx
.code_gen_buffer
, tcg_ctx
.code_gen_buffer_size
,
660 /* Steal room for the prologue at the end of the buffer. This ensures
661 (via the MAX_CODE_GEN_BUFFER_SIZE limits above) that direct branches
662 from TB's to the prologue are going to be in range. It also means
663 that we don't need to mark (additional) portions of the data segment
665 tcg_ctx
.code_gen_prologue
= tcg_ctx
.code_gen_buffer
+
666 tcg_ctx
.code_gen_buffer_size
- 1024;
667 tcg_ctx
.code_gen_buffer_size
-= 1024;
669 tcg_ctx
.code_gen_buffer_max_size
= tcg_ctx
.code_gen_buffer_size
-
670 (TCG_MAX_OP_SIZE
* OPC_BUF_SIZE
);
671 tcg_ctx
.code_gen_max_blocks
= tcg_ctx
.code_gen_buffer_size
/
672 CODE_GEN_AVG_BLOCK_SIZE
;
674 g_malloc(tcg_ctx
.code_gen_max_blocks
* sizeof(TranslationBlock
));
677 /* Must be called before using the QEMU cpus. 'tb_size' is the size
678 (in bytes) allocated to the translation buffer. Zero means default
680 void tcg_exec_init(unsigned long tb_size
)
683 code_gen_alloc(tb_size
);
684 tcg_ctx
.code_gen_ptr
= tcg_ctx
.code_gen_buffer
;
685 tcg_register_jit(tcg_ctx
.code_gen_buffer
, tcg_ctx
.code_gen_buffer_size
);
687 #if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE)
688 /* There's no guest base to take into account, so go ahead and
689 initialize the prologue now. */
690 tcg_prologue_init(&tcg_ctx
);
694 bool tcg_enabled(void)
696 return tcg_ctx
.code_gen_buffer
!= NULL
;
699 /* Allocate a new translation block. Flush the translation buffer if
700 too many translation blocks or too much generated code. */
701 static TranslationBlock
*tb_alloc(target_ulong pc
)
703 TranslationBlock
*tb
;
705 if (tcg_ctx
.tb_ctx
.nb_tbs
>= tcg_ctx
.code_gen_max_blocks
||
706 (tcg_ctx
.code_gen_ptr
- tcg_ctx
.code_gen_buffer
) >=
707 tcg_ctx
.code_gen_buffer_max_size
) {
710 tb
= &tcg_ctx
.tb_ctx
.tbs
[tcg_ctx
.tb_ctx
.nb_tbs
++];
716 void tb_free(TranslationBlock
*tb
)
718 /* In practice this is mostly used for single use temporary TB
719 Ignore the hard cases and just back up if this TB happens to
720 be the last one generated. */
721 if (tcg_ctx
.tb_ctx
.nb_tbs
> 0 &&
722 tb
== &tcg_ctx
.tb_ctx
.tbs
[tcg_ctx
.tb_ctx
.nb_tbs
- 1]) {
723 tcg_ctx
.code_gen_ptr
= tb
->tc_ptr
;
724 tcg_ctx
.tb_ctx
.nb_tbs
--;
728 static inline void invalidate_page_bitmap(PageDesc
*p
)
730 if (p
->code_bitmap
) {
731 g_free(p
->code_bitmap
);
732 p
->code_bitmap
= NULL
;
734 p
->code_write_count
= 0;
737 /* Set to NULL all the 'first_tb' fields in all PageDescs. */
738 static void page_flush_tb_1(int level
, void **lp
)
748 for (i
= 0; i
< V_L2_SIZE
; ++i
) {
749 pd
[i
].first_tb
= NULL
;
750 invalidate_page_bitmap(pd
+ i
);
755 for (i
= 0; i
< V_L2_SIZE
; ++i
) {
756 page_flush_tb_1(level
- 1, pp
+ i
);
761 static void page_flush_tb(void)
765 for (i
= 0; i
< V_L1_SIZE
; i
++) {
766 page_flush_tb_1(V_L1_SHIFT
/ V_L2_BITS
- 1, l1_map
+ i
);
770 /* flush all the translation blocks */
771 /* XXX: tb_flush is currently not thread safe */
772 void tb_flush(CPUArchState
*env1
)
774 CPUState
*cpu
= ENV_GET_CPU(env1
);
776 #if defined(DEBUG_FLUSH)
777 printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
778 (unsigned long)(tcg_ctx
.code_gen_ptr
- tcg_ctx
.code_gen_buffer
),
779 tcg_ctx
.tb_ctx
.nb_tbs
, tcg_ctx
.tb_ctx
.nb_tbs
> 0 ?
780 ((unsigned long)(tcg_ctx
.code_gen_ptr
- tcg_ctx
.code_gen_buffer
)) /
781 tcg_ctx
.tb_ctx
.nb_tbs
: 0);
783 if ((unsigned long)(tcg_ctx
.code_gen_ptr
- tcg_ctx
.code_gen_buffer
)
784 > tcg_ctx
.code_gen_buffer_size
) {
785 cpu_abort(cpu
, "Internal error: code buffer overflow\n");
787 tcg_ctx
.tb_ctx
.nb_tbs
= 0;
790 memset(cpu
->tb_jmp_cache
, 0, sizeof(cpu
->tb_jmp_cache
));
793 memset(tcg_ctx
.tb_ctx
.tb_phys_hash
, 0, sizeof(tcg_ctx
.tb_ctx
.tb_phys_hash
));
796 tcg_ctx
.code_gen_ptr
= tcg_ctx
.code_gen_buffer
;
797 /* XXX: flush processor icache at this point if cache flush is
799 tcg_ctx
.tb_ctx
.tb_flush_count
++;
802 #ifdef DEBUG_TB_CHECK
804 static void tb_invalidate_check(target_ulong address
)
806 TranslationBlock
*tb
;
809 address
&= TARGET_PAGE_MASK
;
810 for (i
= 0; i
< CODE_GEN_PHYS_HASH_SIZE
; i
++) {
811 for (tb
= tb_ctx
.tb_phys_hash
[i
]; tb
!= NULL
; tb
= tb
->phys_hash_next
) {
812 if (!(address
+ TARGET_PAGE_SIZE
<= tb
->pc
||
813 address
>= tb
->pc
+ tb
->size
)) {
814 printf("ERROR invalidate: address=" TARGET_FMT_lx
815 " PC=%08lx size=%04x\n",
816 address
, (long)tb
->pc
, tb
->size
);
822 /* verify that all the pages have correct rights for code */
823 static void tb_page_check(void)
825 TranslationBlock
*tb
;
826 int i
, flags1
, flags2
;
828 for (i
= 0; i
< CODE_GEN_PHYS_HASH_SIZE
; i
++) {
829 for (tb
= tcg_ctx
.tb_ctx
.tb_phys_hash
[i
]; tb
!= NULL
;
830 tb
= tb
->phys_hash_next
) {
831 flags1
= page_get_flags(tb
->pc
);
832 flags2
= page_get_flags(tb
->pc
+ tb
->size
- 1);
833 if ((flags1
& PAGE_WRITE
) || (flags2
& PAGE_WRITE
)) {
834 printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
835 (long)tb
->pc
, tb
->size
, flags1
, flags2
);
843 static inline void tb_hash_remove(TranslationBlock
**ptb
, TranslationBlock
*tb
)
845 TranslationBlock
*tb1
;
850 *ptb
= tb1
->phys_hash_next
;
853 ptb
= &tb1
->phys_hash_next
;
857 static inline void tb_page_remove(TranslationBlock
**ptb
, TranslationBlock
*tb
)
859 TranslationBlock
*tb1
;
864 n1
= (uintptr_t)tb1
& 3;
865 tb1
= (TranslationBlock
*)((uintptr_t)tb1
& ~3);
867 *ptb
= tb1
->page_next
[n1
];
870 ptb
= &tb1
->page_next
[n1
];
874 static inline void tb_jmp_remove(TranslationBlock
*tb
, int n
)
876 TranslationBlock
*tb1
, **ptb
;
879 ptb
= &tb
->jmp_next
[n
];
882 /* find tb(n) in circular list */
885 n1
= (uintptr_t)tb1
& 3;
886 tb1
= (TranslationBlock
*)((uintptr_t)tb1
& ~3);
887 if (n1
== n
&& tb1
== tb
) {
891 ptb
= &tb1
->jmp_first
;
893 ptb
= &tb1
->jmp_next
[n1
];
896 /* now we can suppress tb(n) from the list */
897 *ptb
= tb
->jmp_next
[n
];
899 tb
->jmp_next
[n
] = NULL
;
903 /* reset the jump entry 'n' of a TB so that it is not chained to
905 static inline void tb_reset_jump(TranslationBlock
*tb
, int n
)
907 tb_set_jmp_target(tb
, n
, (uintptr_t)(tb
->tc_ptr
+ tb
->tb_next_offset
[n
]));
910 /* invalidate one TB */
911 void tb_phys_invalidate(TranslationBlock
*tb
, tb_page_addr_t page_addr
)
916 tb_page_addr_t phys_pc
;
917 TranslationBlock
*tb1
, *tb2
;
919 /* remove the TB from the hash list */
920 phys_pc
= tb
->page_addr
[0] + (tb
->pc
& ~TARGET_PAGE_MASK
);
921 h
= tb_phys_hash_func(phys_pc
);
922 tb_hash_remove(&tcg_ctx
.tb_ctx
.tb_phys_hash
[h
], tb
);
924 /* remove the TB from the page list */
925 if (tb
->page_addr
[0] != page_addr
) {
926 p
= page_find(tb
->page_addr
[0] >> TARGET_PAGE_BITS
);
927 tb_page_remove(&p
->first_tb
, tb
);
928 invalidate_page_bitmap(p
);
930 if (tb
->page_addr
[1] != -1 && tb
->page_addr
[1] != page_addr
) {
931 p
= page_find(tb
->page_addr
[1] >> TARGET_PAGE_BITS
);
932 tb_page_remove(&p
->first_tb
, tb
);
933 invalidate_page_bitmap(p
);
936 tcg_ctx
.tb_ctx
.tb_invalidated_flag
= 1;
938 /* remove the TB from the hash list */
939 h
= tb_jmp_cache_hash_func(tb
->pc
);
941 if (cpu
->tb_jmp_cache
[h
] == tb
) {
942 cpu
->tb_jmp_cache
[h
] = NULL
;
946 /* suppress this TB from the two jump lists */
947 tb_jmp_remove(tb
, 0);
948 tb_jmp_remove(tb
, 1);
950 /* suppress any remaining jumps to this TB */
953 n1
= (uintptr_t)tb1
& 3;
957 tb1
= (TranslationBlock
*)((uintptr_t)tb1
& ~3);
958 tb2
= tb1
->jmp_next
[n1
];
959 tb_reset_jump(tb1
, n1
);
960 tb1
->jmp_next
[n1
] = NULL
;
963 tb
->jmp_first
= (TranslationBlock
*)((uintptr_t)tb
| 2); /* fail safe */
965 tcg_ctx
.tb_ctx
.tb_phys_invalidate_count
++;
968 static void build_page_bitmap(PageDesc
*p
)
970 int n
, tb_start
, tb_end
;
971 TranslationBlock
*tb
;
973 p
->code_bitmap
= bitmap_new(TARGET_PAGE_SIZE
);
977 n
= (uintptr_t)tb
& 3;
978 tb
= (TranslationBlock
*)((uintptr_t)tb
& ~3);
979 /* NOTE: this is subtle as a TB may span two physical pages */
981 /* NOTE: tb_end may be after the end of the page, but
982 it is not a problem */
983 tb_start
= tb
->pc
& ~TARGET_PAGE_MASK
;
984 tb_end
= tb_start
+ tb
->size
;
985 if (tb_end
> TARGET_PAGE_SIZE
) {
986 tb_end
= TARGET_PAGE_SIZE
;
990 tb_end
= ((tb
->pc
+ tb
->size
) & ~TARGET_PAGE_MASK
);
992 bitmap_set(p
->code_bitmap
, tb_start
, tb_end
- tb_start
);
993 tb
= tb
->page_next
[n
];
997 TranslationBlock
*tb_gen_code(CPUState
*cpu
,
998 target_ulong pc
, target_ulong cs_base
,
999 int flags
, int cflags
)
1001 CPUArchState
*env
= cpu
->env_ptr
;
1002 TranslationBlock
*tb
;
1003 tb_page_addr_t phys_pc
, phys_page2
;
1004 target_ulong virt_page2
;
1007 phys_pc
= get_page_addr_code(env
, pc
);
1009 cflags
|= CF_USE_ICOUNT
;
1013 /* flush must be done */
1015 /* cannot fail at this point */
1017 /* Don't forget to invalidate previous TB info. */
1018 tcg_ctx
.tb_ctx
.tb_invalidated_flag
= 1;
1020 tb
->tc_ptr
= tcg_ctx
.code_gen_ptr
;
1021 tb
->cs_base
= cs_base
;
1023 tb
->cflags
= cflags
;
1024 cpu_gen_code(env
, tb
, &code_gen_size
);
1025 tcg_ctx
.code_gen_ptr
= (void *)(((uintptr_t)tcg_ctx
.code_gen_ptr
+
1026 code_gen_size
+ CODE_GEN_ALIGN
- 1) & ~(CODE_GEN_ALIGN
- 1));
1028 /* check next page if needed */
1029 virt_page2
= (pc
+ tb
->size
- 1) & TARGET_PAGE_MASK
;
1031 if ((pc
& TARGET_PAGE_MASK
) != virt_page2
) {
1032 phys_page2
= get_page_addr_code(env
, virt_page2
);
1034 tb_link_page(tb
, phys_pc
, phys_page2
);
1039 * Invalidate all TBs which intersect with the target physical address range
1040 * [start;end[. NOTE: start and end may refer to *different* physical pages.
1041 * 'is_cpu_write_access' should be true if called from a real cpu write
1042 * access: the virtual CPU will exit the current TB if code is modified inside
1045 void tb_invalidate_phys_range(tb_page_addr_t start
, tb_page_addr_t end
)
1047 while (start
< end
) {
1048 tb_invalidate_phys_page_range(start
, end
, 0);
1049 start
&= TARGET_PAGE_MASK
;
1050 start
+= TARGET_PAGE_SIZE
;
1055 * Invalidate all TBs which intersect with the target physical address range
1056 * [start;end[. NOTE: start and end must refer to the *same* physical page.
1057 * 'is_cpu_write_access' should be true if called from a real cpu write
1058 * access: the virtual CPU will exit the current TB if code is modified inside
1061 void tb_invalidate_phys_page_range(tb_page_addr_t start
, tb_page_addr_t end
,
1062 int is_cpu_write_access
)
1064 TranslationBlock
*tb
, *tb_next
, *saved_tb
;
1065 CPUState
*cpu
= current_cpu
;
1066 #if defined(TARGET_HAS_PRECISE_SMC)
1067 CPUArchState
*env
= NULL
;
1069 tb_page_addr_t tb_start
, tb_end
;
1072 #ifdef TARGET_HAS_PRECISE_SMC
1073 int current_tb_not_found
= is_cpu_write_access
;
1074 TranslationBlock
*current_tb
= NULL
;
1075 int current_tb_modified
= 0;
1076 target_ulong current_pc
= 0;
1077 target_ulong current_cs_base
= 0;
1078 int current_flags
= 0;
1079 #endif /* TARGET_HAS_PRECISE_SMC */
1081 p
= page_find(start
>> TARGET_PAGE_BITS
);
1085 if (!p
->code_bitmap
&&
1086 ++p
->code_write_count
>= SMC_BITMAP_USE_THRESHOLD
&&
1087 is_cpu_write_access
) {
1088 /* build code bitmap */
1089 build_page_bitmap(p
);
1091 #if defined(TARGET_HAS_PRECISE_SMC)
1097 /* we remove all the TBs in the range [start, end[ */
1098 /* XXX: see if in some cases it could be faster to invalidate all
1101 while (tb
!= NULL
) {
1102 n
= (uintptr_t)tb
& 3;
1103 tb
= (TranslationBlock
*)((uintptr_t)tb
& ~3);
1104 tb_next
= tb
->page_next
[n
];
1105 /* NOTE: this is subtle as a TB may span two physical pages */
1107 /* NOTE: tb_end may be after the end of the page, but
1108 it is not a problem */
1109 tb_start
= tb
->page_addr
[0] + (tb
->pc
& ~TARGET_PAGE_MASK
);
1110 tb_end
= tb_start
+ tb
->size
;
1112 tb_start
= tb
->page_addr
[1];
1113 tb_end
= tb_start
+ ((tb
->pc
+ tb
->size
) & ~TARGET_PAGE_MASK
);
1115 if (!(tb_end
<= start
|| tb_start
>= end
)) {
1116 #ifdef TARGET_HAS_PRECISE_SMC
1117 if (current_tb_not_found
) {
1118 current_tb_not_found
= 0;
1120 if (cpu
->mem_io_pc
) {
1121 /* now we have a real cpu fault */
1122 current_tb
= tb_find_pc(cpu
->mem_io_pc
);
1125 if (current_tb
== tb
&&
1126 (current_tb
->cflags
& CF_COUNT_MASK
) != 1) {
1127 /* If we are modifying the current TB, we must stop
1128 its execution. We could be more precise by checking
1129 that the modification is after the current PC, but it
1130 would require a specialized function to partially
1131 restore the CPU state */
1133 current_tb_modified
= 1;
1134 cpu_restore_state_from_tb(cpu
, current_tb
, cpu
->mem_io_pc
);
1135 cpu_get_tb_cpu_state(env
, ¤t_pc
, ¤t_cs_base
,
1138 #endif /* TARGET_HAS_PRECISE_SMC */
1139 /* we need to do that to handle the case where a signal
1140 occurs while doing tb_phys_invalidate() */
1143 saved_tb
= cpu
->current_tb
;
1144 cpu
->current_tb
= NULL
;
1146 tb_phys_invalidate(tb
, -1);
1148 cpu
->current_tb
= saved_tb
;
1149 if (cpu
->interrupt_request
&& cpu
->current_tb
) {
1150 cpu_interrupt(cpu
, cpu
->interrupt_request
);
1156 #if !defined(CONFIG_USER_ONLY)
1157 /* if no code remaining, no need to continue to use slow writes */
1159 invalidate_page_bitmap(p
);
1160 if (is_cpu_write_access
) {
1161 tlb_unprotect_code(start
);
1165 #ifdef TARGET_HAS_PRECISE_SMC
1166 if (current_tb_modified
) {
1167 /* we generate a block containing just the instruction
1168 modifying the memory. It will ensure that it cannot modify
1170 cpu
->current_tb
= NULL
;
1171 tb_gen_code(cpu
, current_pc
, current_cs_base
, current_flags
, 1);
1172 cpu_resume_from_signal(cpu
, NULL
);
1177 /* len must be <= 8 and start must be a multiple of len */
1178 void tb_invalidate_phys_page_fast(tb_page_addr_t start
, int len
)
1184 qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
1185 cpu_single_env
->mem_io_vaddr
, len
,
1186 cpu_single_env
->eip
,
1187 cpu_single_env
->eip
+
1188 (intptr_t)cpu_single_env
->segs
[R_CS
].base
);
1191 p
= page_find(start
>> TARGET_PAGE_BITS
);
1195 if (p
->code_bitmap
) {
1199 nr
= start
& ~TARGET_PAGE_MASK
;
1200 b
= p
->code_bitmap
[BIT_WORD(nr
)] >> (nr
& (BITS_PER_LONG
- 1));
1201 if (b
& ((1 << len
) - 1)) {
1206 tb_invalidate_phys_page_range(start
, start
+ len
, 1);
1210 #if !defined(CONFIG_SOFTMMU)
1211 static void tb_invalidate_phys_page(tb_page_addr_t addr
,
1212 uintptr_t pc
, void *puc
,
1215 TranslationBlock
*tb
;
1218 #ifdef TARGET_HAS_PRECISE_SMC
1219 TranslationBlock
*current_tb
= NULL
;
1220 CPUState
*cpu
= current_cpu
;
1221 CPUArchState
*env
= NULL
;
1222 int current_tb_modified
= 0;
1223 target_ulong current_pc
= 0;
1224 target_ulong current_cs_base
= 0;
1225 int current_flags
= 0;
1228 addr
&= TARGET_PAGE_MASK
;
1229 p
= page_find(addr
>> TARGET_PAGE_BITS
);
1234 #ifdef TARGET_HAS_PRECISE_SMC
1235 if (tb
&& pc
!= 0) {
1236 current_tb
= tb_find_pc(pc
);
1242 while (tb
!= NULL
) {
1243 n
= (uintptr_t)tb
& 3;
1244 tb
= (TranslationBlock
*)((uintptr_t)tb
& ~3);
1245 #ifdef TARGET_HAS_PRECISE_SMC
1246 if (current_tb
== tb
&&
1247 (current_tb
->cflags
& CF_COUNT_MASK
) != 1) {
1248 /* If we are modifying the current TB, we must stop
1249 its execution. We could be more precise by checking
1250 that the modification is after the current PC, but it
1251 would require a specialized function to partially
1252 restore the CPU state */
1254 current_tb_modified
= 1;
1255 cpu_restore_state_from_tb(cpu
, current_tb
, pc
);
1256 cpu_get_tb_cpu_state(env
, ¤t_pc
, ¤t_cs_base
,
1259 #endif /* TARGET_HAS_PRECISE_SMC */
1260 tb_phys_invalidate(tb
, addr
);
1261 tb
= tb
->page_next
[n
];
1264 #ifdef TARGET_HAS_PRECISE_SMC
1265 if (current_tb_modified
) {
1266 /* we generate a block containing just the instruction
1267 modifying the memory. It will ensure that it cannot modify
1269 cpu
->current_tb
= NULL
;
1270 tb_gen_code(cpu
, current_pc
, current_cs_base
, current_flags
, 1);
1274 cpu_resume_from_signal(cpu
, puc
);
1280 /* add the tb in the target page and protect it if necessary */
1281 static inline void tb_alloc_page(TranslationBlock
*tb
,
1282 unsigned int n
, tb_page_addr_t page_addr
)
1285 #ifndef CONFIG_USER_ONLY
1286 bool page_already_protected
;
1289 tb
->page_addr
[n
] = page_addr
;
1290 p
= page_find_alloc(page_addr
>> TARGET_PAGE_BITS
, 1);
1291 tb
->page_next
[n
] = p
->first_tb
;
1292 #ifndef CONFIG_USER_ONLY
1293 page_already_protected
= p
->first_tb
!= NULL
;
1295 p
->first_tb
= (TranslationBlock
*)((uintptr_t)tb
| n
);
1296 invalidate_page_bitmap(p
);
1298 #if defined(CONFIG_USER_ONLY)
1299 if (p
->flags
& PAGE_WRITE
) {
1304 /* force the host page as non writable (writes will have a
1305 page fault + mprotect overhead) */
1306 page_addr
&= qemu_host_page_mask
;
1308 for (addr
= page_addr
; addr
< page_addr
+ qemu_host_page_size
;
1309 addr
+= TARGET_PAGE_SIZE
) {
1311 p2
= page_find(addr
>> TARGET_PAGE_BITS
);
1316 p2
->flags
&= ~PAGE_WRITE
;
1318 mprotect(g2h(page_addr
), qemu_host_page_size
,
1319 (prot
& PAGE_BITS
) & ~PAGE_WRITE
);
1320 #ifdef DEBUG_TB_INVALIDATE
1321 printf("protecting code page: 0x" TARGET_FMT_lx
"\n",
1326 /* if some code is already present, then the pages are already
1327 protected. So we handle the case where only the first TB is
1328 allocated in a physical page */
1329 if (!page_already_protected
) {
1330 tlb_protect_code(page_addr
);
1335 /* add a new TB and link it to the physical page tables. phys_page2 is
1336 (-1) to indicate that only one page contains the TB. */
1337 static void tb_link_page(TranslationBlock
*tb
, tb_page_addr_t phys_pc
,
1338 tb_page_addr_t phys_page2
)
1341 TranslationBlock
**ptb
;
1343 /* Grab the mmap lock to stop another thread invalidating this TB
1344 before we are done. */
1346 /* add in the physical hash table */
1347 h
= tb_phys_hash_func(phys_pc
);
1348 ptb
= &tcg_ctx
.tb_ctx
.tb_phys_hash
[h
];
1349 tb
->phys_hash_next
= *ptb
;
1352 /* add in the page list */
1353 tb_alloc_page(tb
, 0, phys_pc
& TARGET_PAGE_MASK
);
1354 if (phys_page2
!= -1) {
1355 tb_alloc_page(tb
, 1, phys_page2
);
1357 tb
->page_addr
[1] = -1;
1360 tb
->jmp_first
= (TranslationBlock
*)((uintptr_t)tb
| 2);
1361 tb
->jmp_next
[0] = NULL
;
1362 tb
->jmp_next
[1] = NULL
;
1364 /* init original jump addresses */
1365 if (tb
->tb_next_offset
[0] != 0xffff) {
1366 tb_reset_jump(tb
, 0);
1368 if (tb
->tb_next_offset
[1] != 0xffff) {
1369 tb_reset_jump(tb
, 1);
1372 #ifdef DEBUG_TB_CHECK
1378 /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
1379 tb[1].tc_ptr. Return NULL if not found */
1380 static TranslationBlock
*tb_find_pc(uintptr_t tc_ptr
)
1382 int m_min
, m_max
, m
;
1384 TranslationBlock
*tb
;
1386 if (tcg_ctx
.tb_ctx
.nb_tbs
<= 0) {
1389 if (tc_ptr
< (uintptr_t)tcg_ctx
.code_gen_buffer
||
1390 tc_ptr
>= (uintptr_t)tcg_ctx
.code_gen_ptr
) {
1393 /* binary search (cf Knuth) */
1395 m_max
= tcg_ctx
.tb_ctx
.nb_tbs
- 1;
1396 while (m_min
<= m_max
) {
1397 m
= (m_min
+ m_max
) >> 1;
1398 tb
= &tcg_ctx
.tb_ctx
.tbs
[m
];
1399 v
= (uintptr_t)tb
->tc_ptr
;
1402 } else if (tc_ptr
< v
) {
1408 return &tcg_ctx
.tb_ctx
.tbs
[m_max
];
1411 #if !defined(CONFIG_USER_ONLY)
1412 void tb_invalidate_phys_addr(AddressSpace
*as
, hwaddr addr
)
1414 ram_addr_t ram_addr
;
1419 mr
= address_space_translate(as
, addr
, &addr
, &l
, false);
1420 if (!(memory_region_is_ram(mr
)
1421 || memory_region_is_romd(mr
))) {
1425 ram_addr
= (memory_region_get_ram_addr(mr
) & TARGET_PAGE_MASK
)
1427 tb_invalidate_phys_page_range(ram_addr
, ram_addr
+ 1, 0);
1430 #endif /* !defined(CONFIG_USER_ONLY) */
1432 void tb_check_watchpoint(CPUState
*cpu
)
1434 TranslationBlock
*tb
;
1436 tb
= tb_find_pc(cpu
->mem_io_pc
);
1438 cpu_abort(cpu
, "check_watchpoint: could not find TB for pc=%p",
1439 (void *)cpu
->mem_io_pc
);
1441 cpu_restore_state_from_tb(cpu
, tb
, cpu
->mem_io_pc
);
1442 tb_phys_invalidate(tb
, -1);
1445 #ifndef CONFIG_USER_ONLY
1446 /* mask must never be zero, except for A20 change call */
1447 static void tcg_handle_interrupt(CPUState
*cpu
, int mask
)
1451 old_mask
= cpu
->interrupt_request
;
1452 cpu
->interrupt_request
|= mask
;
1455 * If called from iothread context, wake the target cpu in
1458 if (!qemu_cpu_is_self(cpu
)) {
1464 cpu
->icount_decr
.u16
.high
= 0xffff;
1465 if (!cpu_can_do_io(cpu
)
1466 && (mask
& ~old_mask
) != 0) {
1467 cpu_abort(cpu
, "Raised interrupt while not in I/O function");
1470 cpu
->tcg_exit_req
= 1;
1474 CPUInterruptHandler cpu_interrupt_handler
= tcg_handle_interrupt
;
1476 /* in deterministic execution mode, instructions doing device I/Os
1477 must be at the end of the TB */
1478 void cpu_io_recompile(CPUState
*cpu
, uintptr_t retaddr
)
1480 #if defined(TARGET_MIPS) || defined(TARGET_SH4)
1481 CPUArchState
*env
= cpu
->env_ptr
;
1483 TranslationBlock
*tb
;
1485 target_ulong pc
, cs_base
;
1488 tb
= tb_find_pc(retaddr
);
1490 cpu_abort(cpu
, "cpu_io_recompile: could not find TB for pc=%p",
1493 n
= cpu
->icount_decr
.u16
.low
+ tb
->icount
;
1494 cpu_restore_state_from_tb(cpu
, tb
, retaddr
);
1495 /* Calculate how many instructions had been executed before the fault
1497 n
= n
- cpu
->icount_decr
.u16
.low
;
1498 /* Generate a new TB ending on the I/O insn. */
1500 /* On MIPS and SH, delay slot instructions can only be restarted if
1501 they were already the first instruction in the TB. If this is not
1502 the first instruction in a TB then re-execute the preceding
1504 #if defined(TARGET_MIPS)
1505 if ((env
->hflags
& MIPS_HFLAG_BMASK
) != 0 && n
> 1) {
1506 env
->active_tc
.PC
-= (env
->hflags
& MIPS_HFLAG_B16
? 2 : 4);
1507 cpu
->icount_decr
.u16
.low
++;
1508 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
1510 #elif defined(TARGET_SH4)
1511 if ((env
->flags
& ((DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
))) != 0
1514 cpu
->icount_decr
.u16
.low
++;
1515 env
->flags
&= ~(DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
);
1518 /* This should never happen. */
1519 if (n
> CF_COUNT_MASK
) {
1520 cpu_abort(cpu
, "TB too big during recompile");
1523 cflags
= n
| CF_LAST_IO
;
1525 cs_base
= tb
->cs_base
;
1527 tb_phys_invalidate(tb
, -1);
1528 /* FIXME: In theory this could raise an exception. In practice
1529 we have already translated the block once so it's probably ok. */
1530 tb_gen_code(cpu
, pc
, cs_base
, flags
, cflags
);
1531 /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
1532 the first in the TB) then we end up generating a whole new TB and
1533 repeating the fault, which is horribly inefficient.
1534 Better would be to execute just this insn uncached, or generate a
1536 cpu_resume_from_signal(cpu
, NULL
);
1539 void tb_flush_jmp_cache(CPUState
*cpu
, target_ulong addr
)
1543 /* Discard jump cache entries for any tb which might potentially
1544 overlap the flushed page. */
1545 i
= tb_jmp_cache_hash_page(addr
- TARGET_PAGE_SIZE
);
1546 memset(&cpu
->tb_jmp_cache
[i
], 0,
1547 TB_JMP_PAGE_SIZE
* sizeof(TranslationBlock
*));
1549 i
= tb_jmp_cache_hash_page(addr
);
1550 memset(&cpu
->tb_jmp_cache
[i
], 0,
1551 TB_JMP_PAGE_SIZE
* sizeof(TranslationBlock
*));
1554 void dump_exec_info(FILE *f
, fprintf_function cpu_fprintf
)
1556 int i
, target_code_size
, max_target_code_size
;
1557 int direct_jmp_count
, direct_jmp2_count
, cross_page
;
1558 TranslationBlock
*tb
;
1560 target_code_size
= 0;
1561 max_target_code_size
= 0;
1563 direct_jmp_count
= 0;
1564 direct_jmp2_count
= 0;
1565 for (i
= 0; i
< tcg_ctx
.tb_ctx
.nb_tbs
; i
++) {
1566 tb
= &tcg_ctx
.tb_ctx
.tbs
[i
];
1567 target_code_size
+= tb
->size
;
1568 if (tb
->size
> max_target_code_size
) {
1569 max_target_code_size
= tb
->size
;
1571 if (tb
->page_addr
[1] != -1) {
1574 if (tb
->tb_next_offset
[0] != 0xffff) {
1576 if (tb
->tb_next_offset
[1] != 0xffff) {
1577 direct_jmp2_count
++;
1581 /* XXX: avoid using doubles ? */
1582 cpu_fprintf(f
, "Translation buffer state:\n");
1583 cpu_fprintf(f
, "gen code size %td/%zd\n",
1584 tcg_ctx
.code_gen_ptr
- tcg_ctx
.code_gen_buffer
,
1585 tcg_ctx
.code_gen_buffer_max_size
);
1586 cpu_fprintf(f
, "TB count %d/%d\n",
1587 tcg_ctx
.tb_ctx
.nb_tbs
, tcg_ctx
.code_gen_max_blocks
);
1588 cpu_fprintf(f
, "TB avg target size %d max=%d bytes\n",
1589 tcg_ctx
.tb_ctx
.nb_tbs
? target_code_size
/
1590 tcg_ctx
.tb_ctx
.nb_tbs
: 0,
1591 max_target_code_size
);
1592 cpu_fprintf(f
, "TB avg host size %td bytes (expansion ratio: %0.1f)\n",
1593 tcg_ctx
.tb_ctx
.nb_tbs
? (tcg_ctx
.code_gen_ptr
-
1594 tcg_ctx
.code_gen_buffer
) /
1595 tcg_ctx
.tb_ctx
.nb_tbs
: 0,
1596 target_code_size
? (double) (tcg_ctx
.code_gen_ptr
-
1597 tcg_ctx
.code_gen_buffer
) /
1598 target_code_size
: 0);
1599 cpu_fprintf(f
, "cross page TB count %d (%d%%)\n", cross_page
,
1600 tcg_ctx
.tb_ctx
.nb_tbs
? (cross_page
* 100) /
1601 tcg_ctx
.tb_ctx
.nb_tbs
: 0);
1602 cpu_fprintf(f
, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n",
1604 tcg_ctx
.tb_ctx
.nb_tbs
? (direct_jmp_count
* 100) /
1605 tcg_ctx
.tb_ctx
.nb_tbs
: 0,
1607 tcg_ctx
.tb_ctx
.nb_tbs
? (direct_jmp2_count
* 100) /
1608 tcg_ctx
.tb_ctx
.nb_tbs
: 0);
1609 cpu_fprintf(f
, "\nStatistics:\n");
1610 cpu_fprintf(f
, "TB flush count %d\n", tcg_ctx
.tb_ctx
.tb_flush_count
);
1611 cpu_fprintf(f
, "TB invalidate count %d\n",
1612 tcg_ctx
.tb_ctx
.tb_phys_invalidate_count
);
1613 cpu_fprintf(f
, "TLB flush count %d\n", tlb_flush_count
);
1614 tcg_dump_info(f
, cpu_fprintf
);
1617 void dump_opcount_info(FILE *f
, fprintf_function cpu_fprintf
)
1619 tcg_dump_op_count(f
, cpu_fprintf
);
1622 #else /* CONFIG_USER_ONLY */
1624 void cpu_interrupt(CPUState
*cpu
, int mask
)
1626 cpu
->interrupt_request
|= mask
;
1627 cpu
->tcg_exit_req
= 1;
1631 * Walks guest process memory "regions" one by one
1632 * and calls callback function 'fn' for each region.
1634 struct walk_memory_regions_data
{
1635 walk_memory_regions_fn fn
;
1641 static int walk_memory_regions_end(struct walk_memory_regions_data
*data
,
1642 target_ulong end
, int new_prot
)
1644 if (data
->start
!= -1u) {
1645 int rc
= data
->fn(data
->priv
, data
->start
, end
, data
->prot
);
1651 data
->start
= (new_prot
? end
: -1u);
1652 data
->prot
= new_prot
;
1657 static int walk_memory_regions_1(struct walk_memory_regions_data
*data
,
1658 target_ulong base
, int level
, void **lp
)
1664 return walk_memory_regions_end(data
, base
, 0);
1670 for (i
= 0; i
< V_L2_SIZE
; ++i
) {
1671 int prot
= pd
[i
].flags
;
1673 pa
= base
| (i
<< TARGET_PAGE_BITS
);
1674 if (prot
!= data
->prot
) {
1675 rc
= walk_memory_regions_end(data
, pa
, prot
);
1684 for (i
= 0; i
< V_L2_SIZE
; ++i
) {
1685 pa
= base
| ((target_ulong
)i
<<
1686 (TARGET_PAGE_BITS
+ V_L2_BITS
* level
));
1687 rc
= walk_memory_regions_1(data
, pa
, level
- 1, pp
+ i
);
1697 int walk_memory_regions(void *priv
, walk_memory_regions_fn fn
)
1699 struct walk_memory_regions_data data
;
1707 for (i
= 0; i
< V_L1_SIZE
; i
++) {
1708 int rc
= walk_memory_regions_1(&data
, (target_ulong
)i
<< (V_L1_SHIFT
+ TARGET_PAGE_BITS
),
1709 V_L1_SHIFT
/ V_L2_BITS
- 1, l1_map
+ i
);
1715 return walk_memory_regions_end(&data
, 0, 0);
1718 static int dump_region(void *priv
, target_ulong start
,
1719 target_ulong end
, unsigned long prot
)
1721 FILE *f
= (FILE *)priv
;
1723 (void) fprintf(f
, TARGET_FMT_lx
"-"TARGET_FMT_lx
1724 " "TARGET_FMT_lx
" %c%c%c\n",
1725 start
, end
, end
- start
,
1726 ((prot
& PAGE_READ
) ? 'r' : '-'),
1727 ((prot
& PAGE_WRITE
) ? 'w' : '-'),
1728 ((prot
& PAGE_EXEC
) ? 'x' : '-'));
1733 /* dump memory mappings */
1734 void page_dump(FILE *f
)
1736 const int length
= sizeof(target_ulong
) * 2;
1737 (void) fprintf(f
, "%-*s %-*s %-*s %s\n",
1738 length
, "start", length
, "end", length
, "size", "prot");
1739 walk_memory_regions(f
, dump_region
);
1742 int page_get_flags(target_ulong address
)
1746 p
= page_find(address
>> TARGET_PAGE_BITS
);
1753 /* Modify the flags of a page and invalidate the code if necessary.
1754 The flag PAGE_WRITE_ORG is positioned automatically depending
1755 on PAGE_WRITE. The mmap_lock should already be held. */
1756 void page_set_flags(target_ulong start
, target_ulong end
, int flags
)
1758 target_ulong addr
, len
;
1760 /* This function should never be called with addresses outside the
1761 guest address space. If this assert fires, it probably indicates
1762 a missing call to h2g_valid. */
1763 #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS
1764 assert(end
< ((target_ulong
)1 << L1_MAP_ADDR_SPACE_BITS
));
1766 assert(start
< end
);
1768 start
= start
& TARGET_PAGE_MASK
;
1769 end
= TARGET_PAGE_ALIGN(end
);
1771 if (flags
& PAGE_WRITE
) {
1772 flags
|= PAGE_WRITE_ORG
;
1775 for (addr
= start
, len
= end
- start
;
1777 len
-= TARGET_PAGE_SIZE
, addr
+= TARGET_PAGE_SIZE
) {
1778 PageDesc
*p
= page_find_alloc(addr
>> TARGET_PAGE_BITS
, 1);
1780 /* If the write protection bit is set, then we invalidate
1782 if (!(p
->flags
& PAGE_WRITE
) &&
1783 (flags
& PAGE_WRITE
) &&
1785 tb_invalidate_phys_page(addr
, 0, NULL
, false);
1791 int page_check_range(target_ulong start
, target_ulong len
, int flags
)
1797 /* This function should never be called with addresses outside the
1798 guest address space. If this assert fires, it probably indicates
1799 a missing call to h2g_valid. */
1800 #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS
1801 assert(start
< ((target_ulong
)1 << L1_MAP_ADDR_SPACE_BITS
));
1807 if (start
+ len
- 1 < start
) {
1808 /* We've wrapped around. */
1812 /* must do before we loose bits in the next step */
1813 end
= TARGET_PAGE_ALIGN(start
+ len
);
1814 start
= start
& TARGET_PAGE_MASK
;
1816 for (addr
= start
, len
= end
- start
;
1818 len
-= TARGET_PAGE_SIZE
, addr
+= TARGET_PAGE_SIZE
) {
1819 p
= page_find(addr
>> TARGET_PAGE_BITS
);
1823 if (!(p
->flags
& PAGE_VALID
)) {
1827 if ((flags
& PAGE_READ
) && !(p
->flags
& PAGE_READ
)) {
1830 if (flags
& PAGE_WRITE
) {
1831 if (!(p
->flags
& PAGE_WRITE_ORG
)) {
1834 /* unprotect the page if it was put read-only because it
1835 contains translated code */
1836 if (!(p
->flags
& PAGE_WRITE
)) {
1837 if (!page_unprotect(addr
, 0, NULL
)) {
1846 /* called from signal handler: invalidate the code and unprotect the
1847 page. Return TRUE if the fault was successfully handled. */
1848 int page_unprotect(target_ulong address
, uintptr_t pc
, void *puc
)
1852 target_ulong host_start
, host_end
, addr
;
1854 /* Technically this isn't safe inside a signal handler. However we
1855 know this only ever happens in a synchronous SEGV handler, so in
1856 practice it seems to be ok. */
1859 p
= page_find(address
>> TARGET_PAGE_BITS
);
1865 /* if the page was really writable, then we change its
1866 protection back to writable */
1867 if ((p
->flags
& PAGE_WRITE_ORG
) && !(p
->flags
& PAGE_WRITE
)) {
1868 host_start
= address
& qemu_host_page_mask
;
1869 host_end
= host_start
+ qemu_host_page_size
;
1872 for (addr
= host_start
; addr
< host_end
; addr
+= TARGET_PAGE_SIZE
) {
1873 p
= page_find(addr
>> TARGET_PAGE_BITS
);
1874 p
->flags
|= PAGE_WRITE
;
1877 /* and since the content will be modified, we must invalidate
1878 the corresponding translated code. */
1879 tb_invalidate_phys_page(addr
, pc
, puc
, true);
1880 #ifdef DEBUG_TB_CHECK
1881 tb_invalidate_check(addr
);
1884 mprotect((void *)g2h(host_start
), qemu_host_page_size
,
1893 #endif /* CONFIG_USER_ONLY */