util/cpuinfo-i386.c

   1 /*
   2  * SPDX-License-Identifier: GPL-2.0-or-later
   3  * Host specific cpu indentification for x86.
   4  */
   5
   6 #include "qemu/osdep.h"
   7 #include "host/cpuinfo.h"
   8 #ifdef CONFIG_CPUID_H
   9 # include "qemu/cpuid.h"
  10 #endif
  11
  12 unsigned cpuinfo;
  13
  14 /* Called both as constructor and (possibly) via other constructors. */
  15 unsigned __attribute__((constructor)) cpuinfo_init(void)
  16 {
  17     unsigned info = cpuinfo;
  18
  19     if (info) {
  20         return info;
  21     }
  22
  23 #ifdef CONFIG_CPUID_H
  24     unsigned max, a, b, c, d, b7 = 0, c7 = 0;
  25
  26     max = __get_cpuid_max(0, 0);
  27
  28     if (max >= 7) {
  29         __cpuid_count(7, 0, a, b7, c7, d);
  30         info |= (b7 & bit_BMI ? CPUINFO_BMI1 : 0);
  31         info |= (b7 & bit_BMI2 ? CPUINFO_BMI2 : 0);
  32     }
  33
  34     if (max >= 1) {
  35         __cpuid(1, a, b, c, d);
  36
  37         info |= (d & bit_CMOV ? CPUINFO_CMOV : 0);
  38         info |= (d & bit_SSE2 ? CPUINFO_SSE2 : 0);
  39         info |= (c & bit_SSE4_1 ? CPUINFO_SSE4 : 0);
  40         info |= (c & bit_MOVBE ? CPUINFO_MOVBE : 0);
  41         info |= (c & bit_POPCNT ? CPUINFO_POPCNT : 0);
  42
  43         /* For AVX features, we must check available and usable. */
  44         if ((c & bit_AVX) && (c & bit_OSXSAVE)) {
  45             unsigned bv = xgetbv_low(0);
  46
  47             if ((bv & 6) == 6) {
  48                 info |= CPUINFO_AVX1;
  49                 info |= (b7 & bit_AVX2 ? CPUINFO_AVX2 : 0);
  50
  51                 if ((bv & 0xe0) == 0xe0) {
  52                     info |= (b7 & bit_AVX512F ? CPUINFO_AVX512F : 0);
  53                     info |= (b7 & bit_AVX512VL ? CPUINFO_AVX512VL : 0);
  54                     info |= (b7 & bit_AVX512BW ? CPUINFO_AVX512BW : 0);
  55                     info |= (b7 & bit_AVX512DQ ? CPUINFO_AVX512DQ : 0);
  56                     info |= (c7 & bit_AVX512VBMI2 ? CPUINFO_AVX512VBMI2 : 0);
  57                 }
  58
  59                 /*
  60                  * The Intel SDM has added:
  61                  *   Processors that enumerate support for Intel® AVX
  62                  *   (by setting the feature flag CPUID.01H:ECX.AVX[bit 28])
  63                  *   guarantee that the 16-byte memory operations performed
  64                  *   by the following instructions will always be carried
  65                  *   out atomically:
  66                  *   - MOVAPD, MOVAPS, and MOVDQA.
  67                  *   - VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX.128.
  68                  *   - VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when encoded
  69                  *     with EVEX.128 and k0 (masking disabled).
  70                  * Note that these instructions require the linear addresses
  71                  * of their memory operands to be 16-byte aligned.
  72                  *
  73                  * AMD has provided an even stronger guarantee that processors
  74                  * with AVX provide 16-byte atomicity for all cachable,
  75                  * naturally aligned single loads and stores, e.g. MOVDQU.
  76                  *
  77                  * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688
  78                  */
  79                 __cpuid(0, a, b, c, d);
  80                 if (c == signature_INTEL_ecx) {
  81                     info |= CPUINFO_ATOMIC_VMOVDQA;
  82                 } else if (c == signature_AMD_ecx) {
  83                     info |= CPUINFO_ATOMIC_VMOVDQA | CPUINFO_ATOMIC_VMOVDQU;
  84                 }
  85             }
  86         }
  87     }
  88
  89     max = __get_cpuid_max(0x8000000, 0);
  90     if (max >= 1) {
  91         __cpuid(0x80000001, a, b, c, d);
  92         info |= (c & bit_LZCNT ? CPUINFO_LZCNT : 0);
  93     }
  94 #endif
  95
  96     info |= CPUINFO_ALWAYS;
  97     cpuinfo = info;
  98     return info;
  99 }