vendor/portable-atomic/src/gen/utils.rs

   1 // This file is @generated by target_spec.sh.
   2 // It is not intended for manual editing.
   3
   4 #![allow(unused_macros)]
   5
   6 // On AArch64, the base register of load/store/atomic instructions must be 64-bit.
   7 // Passing a 32-bit value to `in(reg)` on AArch64 results in the upper bits
   8 // having an undefined value, but to work correctly with ILP32 ABI, the upper
   9 // bits must be zero, which is handled here by casting to u64. Another way to
  10 // handle this is to pass it as a pointer and clear the upper bits inside asm,
  11 // but it is easier to overlook than cast, which can catch overlooks by
  12 // asm_sub_register lint.
  13 // See also https://github.com/ARM-software/abi-aa/blob/2023Q1/aapcs64/aapcs64.rst#57pointers
  14 //
  15 // Except for x86_64, which can use 32-bit registers in the destination operand
  16 // (on x86_64, we use the ptr_modifier macro to handle this), we need to do the
  17 // same for ILP32 ABI on other 64-bit architectures. (At least, as far as I can
  18 // see from the assembly generated by LLVM, this is also required for MIPS64 N32
  19 // ABI. I don't know about the RISC-V s64ilp32 ABI for which a patch was
  20 // recently submitted to the kernel, but in any case, this should be a safe
  21 // default for such ABIs).
  22 //
  23 // Known architectures that have such ABI are x86_64 (X32), aarch64 (ILP32),
  24 // mips64 (N32), and riscv64 (s64ilp32, not merged yet though). (As of
  25 // 2023-06-05, only the former two are supported by rustc.) However, we list all
  26 // known 64-bit architectures because similar ABIs may exist or future added for
  27 // other architectures.
  28 #[cfg(all(
  29     target_pointer_width = "32",
  30     any(
  31         target_arch = "aarch64",
  32         target_arch = "bpf",
  33         target_arch = "loongarch64",
  34         target_arch = "mips64",
  35         target_arch = "mips64r6",
  36         target_arch = "nvptx64",
  37         target_arch = "powerpc64",
  38         target_arch = "riscv64",
  39         target_arch = "s390x",
  40         target_arch = "sparc64",
  41         target_arch = "wasm64",
  42         target_arch = "x86_64",
  43     ),
  44 ))]
  45 macro_rules! ptr_reg {
  46     ($ptr:ident) => {{
  47         let _: *const _ = $ptr; // ensure $ptr is a pointer (*mut _ or *const _)
  48         $ptr as u64
  49     }};
  50 }
  51 #[cfg(not(all(
  52     target_pointer_width = "32",
  53     any(
  54         target_arch = "aarch64",
  55         target_arch = "bpf",
  56         target_arch = "loongarch64",
  57         target_arch = "mips64",
  58         target_arch = "mips64r6",
  59         target_arch = "nvptx64",
  60         target_arch = "powerpc64",
  61         target_arch = "riscv64",
  62         target_arch = "s390x",
  63         target_arch = "sparc64",
  64         target_arch = "wasm64",
  65         target_arch = "x86_64",
  66     ),
  67 )))]
  68 macro_rules! ptr_reg {
  69     ($ptr:ident) => {{
  70         let _: *const _ = $ptr; // ensure $ptr is a pointer (*mut _ or *const _)
  71         $ptr // cast is unnecessary here.
  72     }};
  73 }
  74
  75 // Some 64-bit architectures have ABI with 32-bit pointer width (e.g., x86_64 X32 ABI,
  76 // AArch64 ILP32 ABI, MIPS64 N32 ABI). On those targets, AtomicU64 is available
  77 // and fast, so use it to implement normal sequence lock.
  78 //
  79 // See ptr_reg macro for the reason why all known 64-bit architectures are listed.
  80 #[cfg(feature = "fallback")]
  81 #[cfg(any(
  82     not(any(target_pointer_width = "16", target_pointer_width = "32")), // i.e., 64-bit or greater
  83     target_arch = "aarch64",
  84     target_arch = "bpf",
  85     target_arch = "loongarch64",
  86     target_arch = "mips64",
  87     target_arch = "mips64r6",
  88     target_arch = "nvptx64",
  89     target_arch = "powerpc64",
  90     target_arch = "riscv64",
  91     target_arch = "s390x",
  92     target_arch = "sparc64",
  93     target_arch = "wasm64",
  94     target_arch = "x86_64",
  95 ))]
  96 #[macro_use]
  97 mod fast_atomic_64_macros {
  98     macro_rules! cfg_has_fast_atomic_64 {
  99         ($($tt:tt)*) => {
 100             $($tt)*
 101         };
 102     }
 103     macro_rules! cfg_no_fast_atomic_64 {
 104         ($($tt:tt)*) => {};
 105     }
 106 }
 107 #[cfg(feature = "fallback")]
 108 #[cfg(not(any(
 109     not(any(target_pointer_width = "16", target_pointer_width = "32")), // i.e., 64-bit or greater
 110     target_arch = "aarch64",
 111     target_arch = "bpf",
 112     target_arch = "loongarch64",
 113     target_arch = "mips64",
 114     target_arch = "mips64r6",
 115     target_arch = "nvptx64",
 116     target_arch = "powerpc64",
 117     target_arch = "riscv64",
 118     target_arch = "s390x",
 119     target_arch = "sparc64",
 120     target_arch = "wasm64",
 121     target_arch = "x86_64",
 122 )))]
 123 #[macro_use]
 124 mod fast_atomic_64_macros {
 125     macro_rules! cfg_has_fast_atomic_64 {
 126         ($($tt:tt)*) => {};
 127     }
 128     macro_rules! cfg_no_fast_atomic_64 {
 129         ($($tt:tt)*) => {
 130             $($tt)*
 131         };
 132     }
 133 }