2 * Copyright (C) 2012-2015 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/compiler.h>
19 #include <linux/irqchip/arm-gic-v3.h>
20 #include <linux/kvm_host.h>
22 #include <asm/kvm_emulate.h>
23 #include <asm/kvm_hyp.h>
25 #define vtr_to_max_lr_idx(v) ((v) & 0xf)
26 #define vtr_to_nr_pre_bits(v) ((((u32)(v) >> 26) & 7) + 1)
27 #define vtr_to_nr_apr_regs(v) (1 << (vtr_to_nr_pre_bits(v) - 5))
29 static u64 __hyp_text
__gic_v3_get_lr(unsigned int lr
)
33 return read_gicreg(ICH_LR0_EL2
);
35 return read_gicreg(ICH_LR1_EL2
);
37 return read_gicreg(ICH_LR2_EL2
);
39 return read_gicreg(ICH_LR3_EL2
);
41 return read_gicreg(ICH_LR4_EL2
);
43 return read_gicreg(ICH_LR5_EL2
);
45 return read_gicreg(ICH_LR6_EL2
);
47 return read_gicreg(ICH_LR7_EL2
);
49 return read_gicreg(ICH_LR8_EL2
);
51 return read_gicreg(ICH_LR9_EL2
);
53 return read_gicreg(ICH_LR10_EL2
);
55 return read_gicreg(ICH_LR11_EL2
);
57 return read_gicreg(ICH_LR12_EL2
);
59 return read_gicreg(ICH_LR13_EL2
);
61 return read_gicreg(ICH_LR14_EL2
);
63 return read_gicreg(ICH_LR15_EL2
);
69 static void __hyp_text
__gic_v3_set_lr(u64 val
, int lr
)
73 write_gicreg(val
, ICH_LR0_EL2
);
76 write_gicreg(val
, ICH_LR1_EL2
);
79 write_gicreg(val
, ICH_LR2_EL2
);
82 write_gicreg(val
, ICH_LR3_EL2
);
85 write_gicreg(val
, ICH_LR4_EL2
);
88 write_gicreg(val
, ICH_LR5_EL2
);
91 write_gicreg(val
, ICH_LR6_EL2
);
94 write_gicreg(val
, ICH_LR7_EL2
);
97 write_gicreg(val
, ICH_LR8_EL2
);
100 write_gicreg(val
, ICH_LR9_EL2
);
103 write_gicreg(val
, ICH_LR10_EL2
);
106 write_gicreg(val
, ICH_LR11_EL2
);
109 write_gicreg(val
, ICH_LR12_EL2
);
112 write_gicreg(val
, ICH_LR13_EL2
);
115 write_gicreg(val
, ICH_LR14_EL2
);
118 write_gicreg(val
, ICH_LR15_EL2
);
123 static void __hyp_text
save_maint_int_state(struct kvm_vcpu
*vcpu
, int nr_lr
)
125 struct vgic_v3_cpu_if
*cpu_if
= &vcpu
->arch
.vgic_cpu
.vgic_v3
;
129 expect_mi
= !!(cpu_if
->vgic_hcr
& ICH_HCR_UIE
);
131 for (i
= 0; i
< nr_lr
; i
++) {
132 if (!(vcpu
->arch
.vgic_cpu
.live_lrs
& (1UL << i
)))
135 expect_mi
|= (!(cpu_if
->vgic_lr
[i
] & ICH_LR_HW
) &&
136 (cpu_if
->vgic_lr
[i
] & ICH_LR_EOI
));
140 cpu_if
->vgic_misr
= read_gicreg(ICH_MISR_EL2
);
142 if (cpu_if
->vgic_misr
& ICH_MISR_EOI
)
143 cpu_if
->vgic_eisr
= read_gicreg(ICH_EISR_EL2
);
145 cpu_if
->vgic_eisr
= 0;
147 cpu_if
->vgic_misr
= 0;
148 cpu_if
->vgic_eisr
= 0;
152 static void __hyp_text
__vgic_v3_write_ap0rn(u32 val
, int n
)
156 write_gicreg(val
, ICH_AP0R0_EL2
);
159 write_gicreg(val
, ICH_AP0R1_EL2
);
162 write_gicreg(val
, ICH_AP0R2_EL2
);
165 write_gicreg(val
, ICH_AP0R3_EL2
);
170 static void __hyp_text
__vgic_v3_write_ap1rn(u32 val
, int n
)
174 write_gicreg(val
, ICH_AP1R0_EL2
);
177 write_gicreg(val
, ICH_AP1R1_EL2
);
180 write_gicreg(val
, ICH_AP1R2_EL2
);
183 write_gicreg(val
, ICH_AP1R3_EL2
);
188 static u32 __hyp_text
__vgic_v3_read_ap0rn(int n
)
194 val
= read_gicreg(ICH_AP0R0_EL2
);
197 val
= read_gicreg(ICH_AP0R1_EL2
);
200 val
= read_gicreg(ICH_AP0R2_EL2
);
203 val
= read_gicreg(ICH_AP0R3_EL2
);
212 static u32 __hyp_text
__vgic_v3_read_ap1rn(int n
)
218 val
= read_gicreg(ICH_AP1R0_EL2
);
221 val
= read_gicreg(ICH_AP1R1_EL2
);
224 val
= read_gicreg(ICH_AP1R2_EL2
);
227 val
= read_gicreg(ICH_AP1R3_EL2
);
236 void __hyp_text
__vgic_v3_save_state(struct kvm_vcpu
*vcpu
)
238 struct vgic_v3_cpu_if
*cpu_if
= &vcpu
->arch
.vgic_cpu
.vgic_v3
;
242 * Make sure stores to the GIC via the memory mapped interface
243 * are now visible to the system register interface.
245 if (!cpu_if
->vgic_sre
)
248 cpu_if
->vgic_vmcr
= read_gicreg(ICH_VMCR_EL2
);
250 if (vcpu
->arch
.vgic_cpu
.live_lrs
) {
252 u32 max_lr_idx
, nr_pre_bits
;
254 cpu_if
->vgic_elrsr
= read_gicreg(ICH_ELSR_EL2
);
256 write_gicreg(0, ICH_HCR_EL2
);
257 val
= read_gicreg(ICH_VTR_EL2
);
258 max_lr_idx
= vtr_to_max_lr_idx(val
);
259 nr_pre_bits
= vtr_to_nr_pre_bits(val
);
261 save_maint_int_state(vcpu
, max_lr_idx
+ 1);
263 for (i
= 0; i
<= max_lr_idx
; i
++) {
264 if (!(vcpu
->arch
.vgic_cpu
.live_lrs
& (1UL << i
)))
267 if (cpu_if
->vgic_elrsr
& (1 << i
))
268 cpu_if
->vgic_lr
[i
] &= ~ICH_LR_STATE
;
270 cpu_if
->vgic_lr
[i
] = __gic_v3_get_lr(i
);
272 __gic_v3_set_lr(0, i
);
275 switch (nr_pre_bits
) {
277 cpu_if
->vgic_ap0r
[3] = __vgic_v3_read_ap0rn(3);
278 cpu_if
->vgic_ap0r
[2] = __vgic_v3_read_ap0rn(2);
280 cpu_if
->vgic_ap0r
[1] = __vgic_v3_read_ap0rn(1);
282 cpu_if
->vgic_ap0r
[0] = __vgic_v3_read_ap0rn(0);
285 switch (nr_pre_bits
) {
287 cpu_if
->vgic_ap1r
[3] = __vgic_v3_read_ap1rn(3);
288 cpu_if
->vgic_ap1r
[2] = __vgic_v3_read_ap1rn(2);
290 cpu_if
->vgic_ap1r
[1] = __vgic_v3_read_ap1rn(1);
292 cpu_if
->vgic_ap1r
[0] = __vgic_v3_read_ap1rn(0);
295 vcpu
->arch
.vgic_cpu
.live_lrs
= 0;
297 cpu_if
->vgic_misr
= 0;
298 cpu_if
->vgic_eisr
= 0;
299 cpu_if
->vgic_elrsr
= 0xffff;
300 cpu_if
->vgic_ap0r
[0] = 0;
301 cpu_if
->vgic_ap0r
[1] = 0;
302 cpu_if
->vgic_ap0r
[2] = 0;
303 cpu_if
->vgic_ap0r
[3] = 0;
304 cpu_if
->vgic_ap1r
[0] = 0;
305 cpu_if
->vgic_ap1r
[1] = 0;
306 cpu_if
->vgic_ap1r
[2] = 0;
307 cpu_if
->vgic_ap1r
[3] = 0;
310 val
= read_gicreg(ICC_SRE_EL2
);
311 write_gicreg(val
| ICC_SRE_EL2_ENABLE
, ICC_SRE_EL2
);
313 if (!cpu_if
->vgic_sre
) {
314 /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */
316 write_gicreg(1, ICC_SRE_EL1
);
320 void __hyp_text
__vgic_v3_restore_state(struct kvm_vcpu
*vcpu
)
322 struct vgic_v3_cpu_if
*cpu_if
= &vcpu
->arch
.vgic_cpu
.vgic_v3
;
324 u32 max_lr_idx
, nr_pre_bits
;
329 * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a
330 * Group0 interrupt (as generated in GICv2 mode) to be
331 * delivered as a FIQ to the guest, with potentially fatal
332 * consequences. So we must make sure that ICC_SRE_EL1 has
333 * been actually programmed with the value we want before
334 * starting to mess with the rest of the GIC.
336 if (!cpu_if
->vgic_sre
) {
337 write_gicreg(0, ICC_SRE_EL1
);
341 val
= read_gicreg(ICH_VTR_EL2
);
342 max_lr_idx
= vtr_to_max_lr_idx(val
);
343 nr_pre_bits
= vtr_to_nr_pre_bits(val
);
345 for (i
= 0; i
<= max_lr_idx
; i
++) {
346 if (cpu_if
->vgic_lr
[i
] & ICH_LR_STATE
)
347 live_lrs
|= (1 << i
);
350 write_gicreg(cpu_if
->vgic_vmcr
, ICH_VMCR_EL2
);
353 write_gicreg(cpu_if
->vgic_hcr
, ICH_HCR_EL2
);
355 switch (nr_pre_bits
) {
357 __vgic_v3_write_ap0rn(cpu_if
->vgic_ap0r
[3], 3);
358 __vgic_v3_write_ap0rn(cpu_if
->vgic_ap0r
[2], 2);
360 __vgic_v3_write_ap0rn(cpu_if
->vgic_ap0r
[1], 1);
362 __vgic_v3_write_ap0rn(cpu_if
->vgic_ap0r
[0], 0);
365 switch (nr_pre_bits
) {
367 __vgic_v3_write_ap1rn(cpu_if
->vgic_ap1r
[3], 3);
368 __vgic_v3_write_ap1rn(cpu_if
->vgic_ap1r
[2], 2);
370 __vgic_v3_write_ap1rn(cpu_if
->vgic_ap1r
[1], 1);
372 __vgic_v3_write_ap1rn(cpu_if
->vgic_ap1r
[0], 0);
375 for (i
= 0; i
<= max_lr_idx
; i
++) {
376 if (!(live_lrs
& (1 << i
)))
379 __gic_v3_set_lr(cpu_if
->vgic_lr
[i
], i
);
384 * Ensures that the above will have reached the
385 * (re)distributors. This ensure the guest will read the
386 * correct values from the memory-mapped interface.
388 if (!cpu_if
->vgic_sre
) {
392 vcpu
->arch
.vgic_cpu
.live_lrs
= live_lrs
;
395 * Prevent the guest from touching the GIC system registers if
396 * SRE isn't enabled for GICv3 emulation.
398 write_gicreg(read_gicreg(ICC_SRE_EL2
) & ~ICC_SRE_EL2_ENABLE
,
402 void __hyp_text
__vgic_v3_init_lrs(void)
404 int max_lr_idx
= vtr_to_max_lr_idx(read_gicreg(ICH_VTR_EL2
));
407 for (i
= 0; i
<= max_lr_idx
; i
++)
408 __gic_v3_set_lr(0, i
);
411 u64 __hyp_text
__vgic_v3_get_ich_vtr_el2(void)
413 return read_gicreg(ICH_VTR_EL2
);
416 u64 __hyp_text
__vgic_v3_read_vmcr(void)
418 return read_gicreg(ICH_VMCR_EL2
);
421 void __hyp_text
__vgic_v3_write_vmcr(u32 vmcr
)
423 write_gicreg(vmcr
, ICH_VMCR_EL2
);
428 static int __hyp_text
__vgic_v3_bpr_min(void)
430 /* See Pseudocode for VPriorityGroup */
431 return 8 - vtr_to_nr_pre_bits(read_gicreg(ICH_VTR_EL2
));
434 static int __hyp_text
__vgic_v3_get_group(struct kvm_vcpu
*vcpu
)
436 u32 esr
= kvm_vcpu_get_hsr(vcpu
);
437 u8 crm
= (esr
& ESR_ELx_SYS64_ISS_CRM_MASK
) >> ESR_ELx_SYS64_ISS_CRM_SHIFT
;
442 #define GICv3_IDLE_PRIORITY 0xff
444 static int __hyp_text
__vgic_v3_highest_priority_lr(struct kvm_vcpu
*vcpu
,
448 unsigned int used_lrs
= vcpu
->arch
.vgic_cpu
.used_lrs
;
449 u8 priority
= GICv3_IDLE_PRIORITY
;
452 for (i
= 0; i
< used_lrs
; i
++) {
453 u64 val
= __gic_v3_get_lr(i
);
454 u8 lr_prio
= (val
& ICH_LR_PRIORITY_MASK
) >> ICH_LR_PRIORITY_SHIFT
;
456 /* Not pending in the state? */
457 if ((val
& ICH_LR_STATE
) != ICH_LR_PENDING_BIT
)
460 /* Group-0 interrupt, but Group-0 disabled? */
461 if (!(val
& ICH_LR_GROUP
) && !(vmcr
& ICH_VMCR_ENG0_MASK
))
464 /* Group-1 interrupt, but Group-1 disabled? */
465 if ((val
& ICH_LR_GROUP
) && !(vmcr
& ICH_VMCR_ENG1_MASK
))
468 /* Not the highest priority? */
469 if (lr_prio
>= priority
)
472 /* This is a candidate */
479 *lr_val
= ICC_IAR1_EL1_SPURIOUS
;
484 static int __hyp_text
__vgic_v3_get_highest_active_priority(void)
486 u8 nr_apr_regs
= vtr_to_nr_apr_regs(read_gicreg(ICH_VTR_EL2
));
490 for (i
= 0; i
< nr_apr_regs
; i
++) {
494 * The ICH_AP0Rn_EL2 and ICH_AP1Rn_EL2 registers
495 * contain the active priority levels for this VCPU
496 * for the maximum number of supported priority
497 * levels, and we return the full priority level only
498 * if the BPR is programmed to its minimum, otherwise
499 * we return a combination of the priority level and
500 * subpriority, as determined by the setting of the
501 * BPR, but without the full subpriority.
503 val
= __vgic_v3_read_ap0rn(i
);
504 val
|= __vgic_v3_read_ap1rn(i
);
510 return (hap
+ __ffs(val
)) << __vgic_v3_bpr_min();
513 return GICv3_IDLE_PRIORITY
;
516 static unsigned int __hyp_text
__vgic_v3_get_bpr0(u32 vmcr
)
518 return (vmcr
& ICH_VMCR_BPR0_MASK
) >> ICH_VMCR_BPR0_SHIFT
;
521 static unsigned int __hyp_text
__vgic_v3_get_bpr1(u32 vmcr
)
525 if (vmcr
& ICH_VMCR_CBPR_MASK
) {
526 bpr
= __vgic_v3_get_bpr0(vmcr
);
530 bpr
= (vmcr
& ICH_VMCR_BPR1_MASK
) >> ICH_VMCR_BPR1_SHIFT
;
537 * Convert a priority to a preemption level, taking the relevant BPR
538 * into account by zeroing the sub-priority bits.
540 static u8 __hyp_text
__vgic_v3_pri_to_pre(u8 pri
, u32 vmcr
, int grp
)
545 bpr
= __vgic_v3_get_bpr0(vmcr
) + 1;
547 bpr
= __vgic_v3_get_bpr1(vmcr
);
549 return pri
& (GENMASK(7, 0) << bpr
);
553 * The priority value is independent of any of the BPR values, so we
554 * normalize it using the minumal BPR value. This guarantees that no
555 * matter what the guest does with its BPR, we can always set/get the
556 * same value of a priority.
558 static void __hyp_text
__vgic_v3_set_active_priority(u8 pri
, u32 vmcr
, int grp
)
564 pre
= __vgic_v3_pri_to_pre(pri
, vmcr
, grp
);
565 ap
= pre
>> __vgic_v3_bpr_min();
569 val
= __vgic_v3_read_ap0rn(apr
);
570 __vgic_v3_write_ap0rn(val
| BIT(ap
% 32), apr
);
572 val
= __vgic_v3_read_ap1rn(apr
);
573 __vgic_v3_write_ap1rn(val
| BIT(ap
% 32), apr
);
577 static void __hyp_text
__vgic_v3_read_iar(struct kvm_vcpu
*vcpu
, u32 vmcr
, int rt
)
583 grp
= __vgic_v3_get_group(vcpu
);
585 lr
= __vgic_v3_highest_priority_lr(vcpu
, vmcr
, &lr_val
);
589 if (grp
!= !!(lr_val
& ICH_LR_GROUP
))
592 pmr
= (vmcr
& ICH_VMCR_PMR_MASK
) >> ICH_VMCR_PMR_SHIFT
;
593 lr_prio
= (lr_val
& ICH_LR_PRIORITY_MASK
) >> ICH_LR_PRIORITY_SHIFT
;
597 if (__vgic_v3_get_highest_active_priority() <= __vgic_v3_pri_to_pre(lr_prio
, vmcr
, grp
))
600 lr_val
&= ~ICH_LR_STATE
;
601 /* No active state for LPIs */
602 if ((lr_val
& ICH_LR_VIRTUAL_ID_MASK
) <= VGIC_MAX_SPI
)
603 lr_val
|= ICH_LR_ACTIVE_BIT
;
604 __gic_v3_set_lr(lr_val
, lr
);
605 __vgic_v3_set_active_priority(lr_prio
, vmcr
, grp
);
606 vcpu_set_reg(vcpu
, rt
, lr_val
& ICH_LR_VIRTUAL_ID_MASK
);
610 vcpu_set_reg(vcpu
, rt
, ICC_IAR1_EL1_SPURIOUS
);
613 static void __hyp_text
__vgic_v3_read_igrpen1(struct kvm_vcpu
*vcpu
, u32 vmcr
, int rt
)
615 vcpu_set_reg(vcpu
, rt
, !!(vmcr
& ICH_VMCR_ENG1_MASK
));
618 static void __hyp_text
__vgic_v3_write_igrpen1(struct kvm_vcpu
*vcpu
, u32 vmcr
, int rt
)
620 u64 val
= vcpu_get_reg(vcpu
, rt
);
623 vmcr
|= ICH_VMCR_ENG1_MASK
;
625 vmcr
&= ~ICH_VMCR_ENG1_MASK
;
627 __vgic_v3_write_vmcr(vmcr
);
630 static void __hyp_text
__vgic_v3_read_bpr1(struct kvm_vcpu
*vcpu
, u32 vmcr
, int rt
)
632 vcpu_set_reg(vcpu
, rt
, __vgic_v3_get_bpr1(vmcr
));
635 static void __hyp_text
__vgic_v3_write_bpr1(struct kvm_vcpu
*vcpu
, u32 vmcr
, int rt
)
637 u64 val
= vcpu_get_reg(vcpu
, rt
);
638 u8 bpr_min
= __vgic_v3_bpr_min();
640 if (vmcr
& ICH_VMCR_CBPR_MASK
)
643 /* Enforce BPR limiting */
647 val
<<= ICH_VMCR_BPR1_SHIFT
;
648 val
&= ICH_VMCR_BPR1_MASK
;
649 vmcr
&= ~ICH_VMCR_BPR1_MASK
;
652 __vgic_v3_write_vmcr(vmcr
);
655 int __hyp_text
__vgic_v3_perform_cpuif_access(struct kvm_vcpu
*vcpu
)
660 void (*fn
)(struct kvm_vcpu
*, u32
, int);
664 esr
= kvm_vcpu_get_hsr(vcpu
);
665 if (vcpu_mode_is_32bit(vcpu
)) {
666 if (!kvm_condition_valid(vcpu
))
669 sysreg
= esr_cp15_to_sysreg(esr
);
671 sysreg
= esr_sys64_to_sysreg(esr
);
674 is_read
= (esr
& ESR_ELx_SYS64_ISS_DIR_MASK
) == ESR_ELx_SYS64_ISS_DIR_READ
;
678 fn
= __vgic_v3_read_iar
;
682 fn
= __vgic_v3_read_igrpen1
;
684 fn
= __vgic_v3_write_igrpen1
;
688 fn
= __vgic_v3_read_bpr1
;
690 fn
= __vgic_v3_write_bpr1
;
696 vmcr
= __vgic_v3_read_vmcr();
697 rt
= kvm_vcpu_sys_get_rt(vcpu
);