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git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - virt/kvm/arm/hyp/vgic-v3-sr.c
2 * Copyright (C) 2012-2015 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/compiler.h>
19 #include <linux/irqchip/arm-gic-v3.h>
20 #include <linux/kvm_host.h>
22 #include <asm/kvm_hyp.h>
24 #define vtr_to_max_lr_idx(v) ((v) & 0xf)
25 #define vtr_to_nr_pri_bits(v) (((u32)(v) >> 29) + 1)
27 static u64 __hyp_text
__gic_v3_get_lr(unsigned int lr
)
31 return read_gicreg(ICH_LR0_EL2
);
33 return read_gicreg(ICH_LR1_EL2
);
35 return read_gicreg(ICH_LR2_EL2
);
37 return read_gicreg(ICH_LR3_EL2
);
39 return read_gicreg(ICH_LR4_EL2
);
41 return read_gicreg(ICH_LR5_EL2
);
43 return read_gicreg(ICH_LR6_EL2
);
45 return read_gicreg(ICH_LR7_EL2
);
47 return read_gicreg(ICH_LR8_EL2
);
49 return read_gicreg(ICH_LR9_EL2
);
51 return read_gicreg(ICH_LR10_EL2
);
53 return read_gicreg(ICH_LR11_EL2
);
55 return read_gicreg(ICH_LR12_EL2
);
57 return read_gicreg(ICH_LR13_EL2
);
59 return read_gicreg(ICH_LR14_EL2
);
61 return read_gicreg(ICH_LR15_EL2
);
67 static void __hyp_text
__gic_v3_set_lr(u64 val
, int lr
)
71 write_gicreg(val
, ICH_LR0_EL2
);
74 write_gicreg(val
, ICH_LR1_EL2
);
77 write_gicreg(val
, ICH_LR2_EL2
);
80 write_gicreg(val
, ICH_LR3_EL2
);
83 write_gicreg(val
, ICH_LR4_EL2
);
86 write_gicreg(val
, ICH_LR5_EL2
);
89 write_gicreg(val
, ICH_LR6_EL2
);
92 write_gicreg(val
, ICH_LR7_EL2
);
95 write_gicreg(val
, ICH_LR8_EL2
);
98 write_gicreg(val
, ICH_LR9_EL2
);
101 write_gicreg(val
, ICH_LR10_EL2
);
104 write_gicreg(val
, ICH_LR11_EL2
);
107 write_gicreg(val
, ICH_LR12_EL2
);
110 write_gicreg(val
, ICH_LR13_EL2
);
113 write_gicreg(val
, ICH_LR14_EL2
);
116 write_gicreg(val
, ICH_LR15_EL2
);
121 static void __hyp_text
save_maint_int_state(struct kvm_vcpu
*vcpu
, int nr_lr
)
123 struct vgic_v3_cpu_if
*cpu_if
= &vcpu
->arch
.vgic_cpu
.vgic_v3
;
127 expect_mi
= !!(cpu_if
->vgic_hcr
& ICH_HCR_UIE
);
129 for (i
= 0; i
< nr_lr
; i
++) {
130 if (!(vcpu
->arch
.vgic_cpu
.live_lrs
& (1UL << i
)))
133 expect_mi
|= (!(cpu_if
->vgic_lr
[i
] & ICH_LR_HW
) &&
134 (cpu_if
->vgic_lr
[i
] & ICH_LR_EOI
));
138 cpu_if
->vgic_misr
= read_gicreg(ICH_MISR_EL2
);
140 if (cpu_if
->vgic_misr
& ICH_MISR_EOI
)
141 cpu_if
->vgic_eisr
= read_gicreg(ICH_EISR_EL2
);
143 cpu_if
->vgic_eisr
= 0;
145 cpu_if
->vgic_misr
= 0;
146 cpu_if
->vgic_eisr
= 0;
150 void __hyp_text
__vgic_v3_save_state(struct kvm_vcpu
*vcpu
)
152 struct vgic_v3_cpu_if
*cpu_if
= &vcpu
->arch
.vgic_cpu
.vgic_v3
;
156 * Make sure stores to the GIC via the memory mapped interface
157 * are now visible to the system register interface.
159 if (!cpu_if
->vgic_sre
)
162 cpu_if
->vgic_vmcr
= read_gicreg(ICH_VMCR_EL2
);
164 if (vcpu
->arch
.vgic_cpu
.live_lrs
) {
166 u32 max_lr_idx
, nr_pri_bits
;
168 cpu_if
->vgic_elrsr
= read_gicreg(ICH_ELSR_EL2
);
170 write_gicreg(0, ICH_HCR_EL2
);
171 val
= read_gicreg(ICH_VTR_EL2
);
172 max_lr_idx
= vtr_to_max_lr_idx(val
);
173 nr_pri_bits
= vtr_to_nr_pri_bits(val
);
175 save_maint_int_state(vcpu
, max_lr_idx
+ 1);
177 for (i
= 0; i
<= max_lr_idx
; i
++) {
178 if (!(vcpu
->arch
.vgic_cpu
.live_lrs
& (1UL << i
)))
181 if (cpu_if
->vgic_elrsr
& (1 << i
))
182 cpu_if
->vgic_lr
[i
] &= ~ICH_LR_STATE
;
184 cpu_if
->vgic_lr
[i
] = __gic_v3_get_lr(i
);
186 __gic_v3_set_lr(0, i
);
189 switch (nr_pri_bits
) {
191 cpu_if
->vgic_ap0r
[3] = read_gicreg(ICH_AP0R3_EL2
);
192 cpu_if
->vgic_ap0r
[2] = read_gicreg(ICH_AP0R2_EL2
);
194 cpu_if
->vgic_ap0r
[1] = read_gicreg(ICH_AP0R1_EL2
);
196 cpu_if
->vgic_ap0r
[0] = read_gicreg(ICH_AP0R0_EL2
);
199 switch (nr_pri_bits
) {
201 cpu_if
->vgic_ap1r
[3] = read_gicreg(ICH_AP1R3_EL2
);
202 cpu_if
->vgic_ap1r
[2] = read_gicreg(ICH_AP1R2_EL2
);
204 cpu_if
->vgic_ap1r
[1] = read_gicreg(ICH_AP1R1_EL2
);
206 cpu_if
->vgic_ap1r
[0] = read_gicreg(ICH_AP1R0_EL2
);
209 vcpu
->arch
.vgic_cpu
.live_lrs
= 0;
211 cpu_if
->vgic_misr
= 0;
212 cpu_if
->vgic_eisr
= 0;
213 cpu_if
->vgic_elrsr
= 0xffff;
214 cpu_if
->vgic_ap0r
[0] = 0;
215 cpu_if
->vgic_ap0r
[1] = 0;
216 cpu_if
->vgic_ap0r
[2] = 0;
217 cpu_if
->vgic_ap0r
[3] = 0;
218 cpu_if
->vgic_ap1r
[0] = 0;
219 cpu_if
->vgic_ap1r
[1] = 0;
220 cpu_if
->vgic_ap1r
[2] = 0;
221 cpu_if
->vgic_ap1r
[3] = 0;
224 val
= read_gicreg(ICC_SRE_EL2
);
225 write_gicreg(val
| ICC_SRE_EL2_ENABLE
, ICC_SRE_EL2
);
227 if (!cpu_if
->vgic_sre
) {
228 /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */
230 write_gicreg(1, ICC_SRE_EL1
);
234 void __hyp_text
__vgic_v3_restore_state(struct kvm_vcpu
*vcpu
)
236 struct vgic_v3_cpu_if
*cpu_if
= &vcpu
->arch
.vgic_cpu
.vgic_v3
;
238 u32 max_lr_idx
, nr_pri_bits
;
243 * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a
244 * Group0 interrupt (as generated in GICv2 mode) to be
245 * delivered as a FIQ to the guest, with potentially fatal
246 * consequences. So we must make sure that ICC_SRE_EL1 has
247 * been actually programmed with the value we want before
248 * starting to mess with the rest of the GIC.
250 if (!cpu_if
->vgic_sre
) {
251 write_gicreg(0, ICC_SRE_EL1
);
255 val
= read_gicreg(ICH_VTR_EL2
);
256 max_lr_idx
= vtr_to_max_lr_idx(val
);
257 nr_pri_bits
= vtr_to_nr_pri_bits(val
);
259 for (i
= 0; i
<= max_lr_idx
; i
++) {
260 if (cpu_if
->vgic_lr
[i
] & ICH_LR_STATE
)
261 live_lrs
|= (1 << i
);
264 write_gicreg(cpu_if
->vgic_vmcr
, ICH_VMCR_EL2
);
267 write_gicreg(cpu_if
->vgic_hcr
, ICH_HCR_EL2
);
269 switch (nr_pri_bits
) {
271 write_gicreg(cpu_if
->vgic_ap0r
[3], ICH_AP0R3_EL2
);
272 write_gicreg(cpu_if
->vgic_ap0r
[2], ICH_AP0R2_EL2
);
274 write_gicreg(cpu_if
->vgic_ap0r
[1], ICH_AP0R1_EL2
);
276 write_gicreg(cpu_if
->vgic_ap0r
[0], ICH_AP0R0_EL2
);
279 switch (nr_pri_bits
) {
281 write_gicreg(cpu_if
->vgic_ap1r
[3], ICH_AP1R3_EL2
);
282 write_gicreg(cpu_if
->vgic_ap1r
[2], ICH_AP1R2_EL2
);
284 write_gicreg(cpu_if
->vgic_ap1r
[1], ICH_AP1R1_EL2
);
286 write_gicreg(cpu_if
->vgic_ap1r
[0], ICH_AP1R0_EL2
);
289 for (i
= 0; i
<= max_lr_idx
; i
++) {
290 if (!(live_lrs
& (1 << i
)))
293 __gic_v3_set_lr(cpu_if
->vgic_lr
[i
], i
);
298 * Ensures that the above will have reached the
299 * (re)distributors. This ensure the guest will read the
300 * correct values from the memory-mapped interface.
302 if (!cpu_if
->vgic_sre
) {
306 vcpu
->arch
.vgic_cpu
.live_lrs
= live_lrs
;
309 * Prevent the guest from touching the GIC system registers if
310 * SRE isn't enabled for GICv3 emulation.
312 write_gicreg(read_gicreg(ICC_SRE_EL2
) & ~ICC_SRE_EL2_ENABLE
,
316 void __hyp_text
__vgic_v3_init_lrs(void)
318 int max_lr_idx
= vtr_to_max_lr_idx(read_gicreg(ICH_VTR_EL2
));
321 for (i
= 0; i
<= max_lr_idx
; i
++)
322 __gic_v3_set_lr(0, i
);
325 u64 __hyp_text
__vgic_v3_get_ich_vtr_el2(void)
327 return read_gicreg(ICH_VTR_EL2
);