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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - virt/kvm/arm/hyp/vgic-v3-sr.c
2 * Copyright (C) 2012-2015 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/compiler.h>
19 #include <linux/irqchip/arm-gic-v3.h>
20 #include <linux/kvm_host.h>
22 #include <asm/kvm_hyp.h>
24 #define vtr_to_max_lr_idx(v) ((v) & 0xf)
25 #define vtr_to_nr_pre_bits(v) (((u32)(v) >> 26) + 1)
27 static u64 __hyp_text
__gic_v3_get_lr(unsigned int lr
)
31 return read_gicreg(ICH_LR0_EL2
);
33 return read_gicreg(ICH_LR1_EL2
);
35 return read_gicreg(ICH_LR2_EL2
);
37 return read_gicreg(ICH_LR3_EL2
);
39 return read_gicreg(ICH_LR4_EL2
);
41 return read_gicreg(ICH_LR5_EL2
);
43 return read_gicreg(ICH_LR6_EL2
);
45 return read_gicreg(ICH_LR7_EL2
);
47 return read_gicreg(ICH_LR8_EL2
);
49 return read_gicreg(ICH_LR9_EL2
);
51 return read_gicreg(ICH_LR10_EL2
);
53 return read_gicreg(ICH_LR11_EL2
);
55 return read_gicreg(ICH_LR12_EL2
);
57 return read_gicreg(ICH_LR13_EL2
);
59 return read_gicreg(ICH_LR14_EL2
);
61 return read_gicreg(ICH_LR15_EL2
);
67 static void __hyp_text
__gic_v3_set_lr(u64 val
, int lr
)
71 write_gicreg(val
, ICH_LR0_EL2
);
74 write_gicreg(val
, ICH_LR1_EL2
);
77 write_gicreg(val
, ICH_LR2_EL2
);
80 write_gicreg(val
, ICH_LR3_EL2
);
83 write_gicreg(val
, ICH_LR4_EL2
);
86 write_gicreg(val
, ICH_LR5_EL2
);
89 write_gicreg(val
, ICH_LR6_EL2
);
92 write_gicreg(val
, ICH_LR7_EL2
);
95 write_gicreg(val
, ICH_LR8_EL2
);
98 write_gicreg(val
, ICH_LR9_EL2
);
101 write_gicreg(val
, ICH_LR10_EL2
);
104 write_gicreg(val
, ICH_LR11_EL2
);
107 write_gicreg(val
, ICH_LR12_EL2
);
110 write_gicreg(val
, ICH_LR13_EL2
);
113 write_gicreg(val
, ICH_LR14_EL2
);
116 write_gicreg(val
, ICH_LR15_EL2
);
121 void __hyp_text
__vgic_v3_save_state(struct kvm_vcpu
*vcpu
)
123 struct vgic_v3_cpu_if
*cpu_if
= &vcpu
->arch
.vgic_cpu
.vgic_v3
;
124 u64 used_lrs
= vcpu
->arch
.vgic_cpu
.used_lrs
;
128 * Make sure stores to the GIC via the memory mapped interface
129 * are now visible to the system register interface.
131 if (!cpu_if
->vgic_sre
) {
133 cpu_if
->vgic_vmcr
= read_gicreg(ICH_VMCR_EL2
);
140 cpu_if
->vgic_elrsr
= read_gicreg(ICH_ELSR_EL2
);
142 write_gicreg(0, ICH_HCR_EL2
);
143 val
= read_gicreg(ICH_VTR_EL2
);
144 nr_pre_bits
= vtr_to_nr_pre_bits(val
);
146 for (i
= 0; i
< used_lrs
; i
++) {
147 if (cpu_if
->vgic_elrsr
& (1 << i
))
148 cpu_if
->vgic_lr
[i
] &= ~ICH_LR_STATE
;
150 cpu_if
->vgic_lr
[i
] = __gic_v3_get_lr(i
);
152 __gic_v3_set_lr(0, i
);
155 switch (nr_pre_bits
) {
157 cpu_if
->vgic_ap0r
[3] = read_gicreg(ICH_AP0R3_EL2
);
158 cpu_if
->vgic_ap0r
[2] = read_gicreg(ICH_AP0R2_EL2
);
160 cpu_if
->vgic_ap0r
[1] = read_gicreg(ICH_AP0R1_EL2
);
162 cpu_if
->vgic_ap0r
[0] = read_gicreg(ICH_AP0R0_EL2
);
165 switch (nr_pre_bits
) {
167 cpu_if
->vgic_ap1r
[3] = read_gicreg(ICH_AP1R3_EL2
);
168 cpu_if
->vgic_ap1r
[2] = read_gicreg(ICH_AP1R2_EL2
);
170 cpu_if
->vgic_ap1r
[1] = read_gicreg(ICH_AP1R1_EL2
);
172 cpu_if
->vgic_ap1r
[0] = read_gicreg(ICH_AP1R0_EL2
);
175 cpu_if
->vgic_elrsr
= 0xffff;
176 cpu_if
->vgic_ap0r
[0] = 0;
177 cpu_if
->vgic_ap0r
[1] = 0;
178 cpu_if
->vgic_ap0r
[2] = 0;
179 cpu_if
->vgic_ap0r
[3] = 0;
180 cpu_if
->vgic_ap1r
[0] = 0;
181 cpu_if
->vgic_ap1r
[1] = 0;
182 cpu_if
->vgic_ap1r
[2] = 0;
183 cpu_if
->vgic_ap1r
[3] = 0;
186 val
= read_gicreg(ICC_SRE_EL2
);
187 write_gicreg(val
| ICC_SRE_EL2_ENABLE
, ICC_SRE_EL2
);
189 if (!cpu_if
->vgic_sre
) {
190 /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */
192 write_gicreg(1, ICC_SRE_EL1
);
196 void __hyp_text
__vgic_v3_restore_state(struct kvm_vcpu
*vcpu
)
198 struct vgic_v3_cpu_if
*cpu_if
= &vcpu
->arch
.vgic_cpu
.vgic_v3
;
199 u64 used_lrs
= vcpu
->arch
.vgic_cpu
.used_lrs
;
205 * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a
206 * Group0 interrupt (as generated in GICv2 mode) to be
207 * delivered as a FIQ to the guest, with potentially fatal
208 * consequences. So we must make sure that ICC_SRE_EL1 has
209 * been actually programmed with the value we want before
210 * starting to mess with the rest of the GIC, and VMCR_EL2 in
213 if (!cpu_if
->vgic_sre
) {
214 write_gicreg(0, ICC_SRE_EL1
);
216 write_gicreg(cpu_if
->vgic_vmcr
, ICH_VMCR_EL2
);
219 val
= read_gicreg(ICH_VTR_EL2
);
220 nr_pre_bits
= vtr_to_nr_pre_bits(val
);
223 write_gicreg(cpu_if
->vgic_hcr
, ICH_HCR_EL2
);
225 switch (nr_pre_bits
) {
227 write_gicreg(cpu_if
->vgic_ap0r
[3], ICH_AP0R3_EL2
);
228 write_gicreg(cpu_if
->vgic_ap0r
[2], ICH_AP0R2_EL2
);
230 write_gicreg(cpu_if
->vgic_ap0r
[1], ICH_AP0R1_EL2
);
232 write_gicreg(cpu_if
->vgic_ap0r
[0], ICH_AP0R0_EL2
);
235 switch (nr_pre_bits
) {
237 write_gicreg(cpu_if
->vgic_ap1r
[3], ICH_AP1R3_EL2
);
238 write_gicreg(cpu_if
->vgic_ap1r
[2], ICH_AP1R2_EL2
);
240 write_gicreg(cpu_if
->vgic_ap1r
[1], ICH_AP1R1_EL2
);
242 write_gicreg(cpu_if
->vgic_ap1r
[0], ICH_AP1R0_EL2
);
245 for (i
= 0; i
< used_lrs
; i
++)
246 __gic_v3_set_lr(cpu_if
->vgic_lr
[i
], i
);
250 * Ensures that the above will have reached the
251 * (re)distributors. This ensure the guest will read the
252 * correct values from the memory-mapped interface.
254 if (!cpu_if
->vgic_sre
) {
260 * Prevent the guest from touching the GIC system registers if
261 * SRE isn't enabled for GICv3 emulation.
263 write_gicreg(read_gicreg(ICC_SRE_EL2
) & ~ICC_SRE_EL2_ENABLE
,
267 void __hyp_text
__vgic_v3_init_lrs(void)
269 int max_lr_idx
= vtr_to_max_lr_idx(read_gicreg(ICH_VTR_EL2
));
272 for (i
= 0; i
<= max_lr_idx
; i
++)
273 __gic_v3_set_lr(0, i
);
276 u64 __hyp_text
__vgic_v3_get_ich_vtr_el2(void)
278 return read_gicreg(ICH_VTR_EL2
);
281 u64 __hyp_text
__vgic_v3_read_vmcr(void)
283 return read_gicreg(ICH_VMCR_EL2
);
286 void __hyp_text
__vgic_v3_write_vmcr(u32 vmcr
)
288 write_gicreg(vmcr
, ICH_VMCR_EL2
);