virt/kvm/arm/vgic/vgic-mmio-v2.c

   1 /*
   2  * VGICv2 MMIO handling functions
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/irqchip/arm-gic.h>
  15 #include <linux/kvm.h>
  16 #include <linux/kvm_host.h>
  17 #include <kvm/iodev.h>
  18 #include <kvm/arm_vgic.h>
  19
  20 #include "vgic.h"
  21 #include "vgic-mmio.h"
  22
  23 static unsigned long vgic_mmio_read_v2_misc(struct kvm_vcpu *vcpu,
  24                                             gpa_t addr, unsigned int len)
  25 {
  26         u32 value;
  27
  28         switch (addr & 0x0c) {
  29         case GIC_DIST_CTRL:
  30                 value = vcpu->kvm->arch.vgic.enabled ? GICD_ENABLE : 0;
  31                 break;
  32         case GIC_DIST_CTR:
  33                 value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
  34                 value = (value >> 5) - 1;
  35                 value |= (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
  36                 break;
  37         case GIC_DIST_IIDR:
  38                 value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
  39                 break;
  40         default:
  41                 return 0;
  42         }
  43
  44         return value;
  45 }
  46
  47 static void vgic_mmio_write_v2_misc(struct kvm_vcpu *vcpu,
  48                                     gpa_t addr, unsigned int len,
  49                                     unsigned long val)
  50 {
  51         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
  52         bool was_enabled = dist->enabled;
  53
  54         switch (addr & 0x0c) {
  55         case GIC_DIST_CTRL:
  56                 dist->enabled = val & GICD_ENABLE;
  57                 if (!was_enabled && dist->enabled)
  58                         vgic_kick_vcpus(vcpu->kvm);
  59                 break;
  60         case GIC_DIST_CTR:
  61         case GIC_DIST_IIDR:
  62                 /* Nothing to do */
  63                 return;
  64         }
  65 }
  66
  67 static void vgic_mmio_write_sgir(struct kvm_vcpu *source_vcpu,
  68                                  gpa_t addr, unsigned int len,
  69                                  unsigned long val)
  70 {
  71         int nr_vcpus = atomic_read(&source_vcpu->kvm->online_vcpus);
  72         int intid = val & 0xf;
  73         int targets = (val >> 16) & 0xff;
  74         int mode = (val >> 24) & 0x03;
  75         int c;
  76         struct kvm_vcpu *vcpu;
  77
  78         switch (mode) {
  79         case 0x0:               /* as specified by targets */
  80                 break;
  81         case 0x1:
  82                 targets = (1U << nr_vcpus) - 1;                 /* all, ... */
  83                 targets &= ~(1U << source_vcpu->vcpu_id);       /* but self */
  84                 break;
  85         case 0x2:               /* this very vCPU only */
  86                 targets = (1U << source_vcpu->vcpu_id);
  87                 break;
  88         case 0x3:               /* reserved */
  89                 return;
  90         }
  91
  92         kvm_for_each_vcpu(c, vcpu, source_vcpu->kvm) {
  93                 struct vgic_irq *irq;
  94
  95                 if (!(targets & (1U << c)))
  96                         continue;
  97
  98                 irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid);
  99
 100                 spin_lock(&irq->irq_lock);
 101                 irq->pending = true;
 102                 irq->source |= 1U << source_vcpu->vcpu_id;
 103
 104                 vgic_queue_irq_unlock(source_vcpu->kvm, irq);
 105         }
 106 }
 107
 108 static unsigned long vgic_mmio_read_target(struct kvm_vcpu *vcpu,
 109                                            gpa_t addr, unsigned int len)
 110 {
 111         u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
 112         int i;
 113         u64 val = 0;
 114
 115         for (i = 0; i < len; i++) {
 116                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 117
 118                 val |= (u64)irq->targets << (i * 8);
 119         }
 120
 121         return val;
 122 }
 123
 124 static void vgic_mmio_write_target(struct kvm_vcpu *vcpu,
 125                                    gpa_t addr, unsigned int len,
 126                                    unsigned long val)
 127 {
 128         u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
 129         int i;
 130
 131         /* GICD_ITARGETSR[0-7] are read-only */
 132         if (intid < VGIC_NR_PRIVATE_IRQS)
 133                 return;
 134
 135         for (i = 0; i < len; i++) {
 136                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid + i);
 137                 int target;
 138
 139                 spin_lock(&irq->irq_lock);
 140
 141                 irq->targets = (val >> (i * 8)) & 0xff;
 142                 target = irq->targets ? __ffs(irq->targets) : 0;
 143                 irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target);
 144
 145                 spin_unlock(&irq->irq_lock);
 146         }
 147 }
 148
 149 static unsigned long vgic_mmio_read_sgipend(struct kvm_vcpu *vcpu,
 150                                             gpa_t addr, unsigned int len)
 151 {
 152         u32 intid = addr & 0x0f;
 153         int i;
 154         u64 val = 0;
 155
 156         for (i = 0; i < len; i++) {
 157                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 158
 159                 val |= (u64)irq->source << (i * 8);
 160         }
 161         return val;
 162 }
 163
 164 static void vgic_mmio_write_sgipendc(struct kvm_vcpu *vcpu,
 165                                      gpa_t addr, unsigned int len,
 166                                      unsigned long val)
 167 {
 168         u32 intid = addr & 0x0f;
 169         int i;
 170
 171         for (i = 0; i < len; i++) {
 172                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 173
 174                 spin_lock(&irq->irq_lock);
 175
 176                 irq->source &= ~((val >> (i * 8)) & 0xff);
 177                 if (!irq->source)
 178                         irq->pending = false;
 179
 180                 spin_unlock(&irq->irq_lock);
 181         }
 182 }
 183
 184 static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu,
 185                                      gpa_t addr, unsigned int len,
 186                                      unsigned long val)
 187 {
 188         u32 intid = addr & 0x0f;
 189         int i;
 190
 191         for (i = 0; i < len; i++) {
 192                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 193
 194                 spin_lock(&irq->irq_lock);
 195
 196                 irq->source |= (val >> (i * 8)) & 0xff;
 197
 198                 if (irq->source) {
 199                         irq->pending = true;
 200                         vgic_queue_irq_unlock(vcpu->kvm, irq);
 201                 } else {
 202                         spin_unlock(&irq->irq_lock);
 203                 }
 204         }
 205 }
 206
 207 static const struct vgic_register_region vgic_v2_dist_registers[] = {
 208         REGISTER_DESC_WITH_LENGTH(GIC_DIST_CTRL,
 209                 vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12,
 210                 VGIC_ACCESS_32bit),
 211         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP,
 212                 vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
 213                 VGIC_ACCESS_32bit),
 214         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET,
 215                 vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
 216                 VGIC_ACCESS_32bit),
 217         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR,
 218                 vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
 219                 VGIC_ACCESS_32bit),
 220         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET,
 221                 vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
 222                 VGIC_ACCESS_32bit),
 223         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR,
 224                 vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
 225                 VGIC_ACCESS_32bit),
 226         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET,
 227                 vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
 228                 VGIC_ACCESS_32bit),
 229         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_CLEAR,
 230                 vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
 231                 VGIC_ACCESS_32bit),
 232         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PRI,
 233                 vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
 234                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 235         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_TARGET,
 236                 vgic_mmio_read_target, vgic_mmio_write_target, 8,
 237                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 238         REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_CONFIG,
 239                 vgic_mmio_read_config, vgic_mmio_write_config, 2,
 240                 VGIC_ACCESS_32bit),
 241         REGISTER_DESC_WITH_LENGTH(GIC_DIST_SOFTINT,
 242                 vgic_mmio_read_raz, vgic_mmio_write_sgir, 4,
 243                 VGIC_ACCESS_32bit),
 244         REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_CLEAR,
 245                 vgic_mmio_read_sgipend, vgic_mmio_write_sgipendc, 16,
 246                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 247         REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_SET,
 248                 vgic_mmio_read_sgipend, vgic_mmio_write_sgipends, 16,
 249                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 250 };
 251
 252 unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev)
 253 {
 254         dev->regions = vgic_v2_dist_registers;
 255         dev->nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
 256
 257         kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
 258
 259         return SZ_4K;
 260 }