2 * VGIC MMIO handling functions
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/bitops.h>
15 #include <linux/bsearch.h>
16 #include <linux/kvm.h>
17 #include <linux/kvm_host.h>
18 #include <kvm/iodev.h>
19 #include <kvm/arm_vgic.h>
22 #include "vgic-mmio.h"
24 unsigned long vgic_mmio_read_raz(struct kvm_vcpu
*vcpu
,
25 gpa_t addr
, unsigned int len
)
30 unsigned long vgic_mmio_read_rao(struct kvm_vcpu
*vcpu
,
31 gpa_t addr
, unsigned int len
)
36 void vgic_mmio_write_wi(struct kvm_vcpu
*vcpu
, gpa_t addr
,
37 unsigned int len
, unsigned long val
)
43 * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value
44 * of the enabled bit, so there is only one function for both here.
46 unsigned long vgic_mmio_read_enable(struct kvm_vcpu
*vcpu
,
47 gpa_t addr
, unsigned int len
)
49 u32 intid
= VGIC_ADDR_TO_INTID(addr
, 1);
53 /* Loop over all IRQs affected by this read */
54 for (i
= 0; i
< len
* 8; i
++) {
55 struct vgic_irq
*irq
= vgic_get_irq(vcpu
->kvm
, vcpu
, intid
+ i
);
60 vgic_put_irq(vcpu
->kvm
, irq
);
66 void vgic_mmio_write_senable(struct kvm_vcpu
*vcpu
,
67 gpa_t addr
, unsigned int len
,
70 u32 intid
= VGIC_ADDR_TO_INTID(addr
, 1);
74 for_each_set_bit(i
, &val
, len
* 8) {
75 struct vgic_irq
*irq
= vgic_get_irq(vcpu
->kvm
, vcpu
, intid
+ i
);
77 spin_lock_irqsave(&irq
->irq_lock
, flags
);
79 vgic_queue_irq_unlock(vcpu
->kvm
, irq
, flags
);
81 vgic_put_irq(vcpu
->kvm
, irq
);
85 void vgic_mmio_write_cenable(struct kvm_vcpu
*vcpu
,
86 gpa_t addr
, unsigned int len
,
89 u32 intid
= VGIC_ADDR_TO_INTID(addr
, 1);
93 for_each_set_bit(i
, &val
, len
* 8) {
94 struct vgic_irq
*irq
= vgic_get_irq(vcpu
->kvm
, vcpu
, intid
+ i
);
96 spin_lock_irqsave(&irq
->irq_lock
, flags
);
100 spin_unlock_irqrestore(&irq
->irq_lock
, flags
);
101 vgic_put_irq(vcpu
->kvm
, irq
);
105 unsigned long vgic_mmio_read_pending(struct kvm_vcpu
*vcpu
,
106 gpa_t addr
, unsigned int len
)
108 u32 intid
= VGIC_ADDR_TO_INTID(addr
, 1);
112 /* Loop over all IRQs affected by this read */
113 for (i
= 0; i
< len
* 8; i
++) {
114 struct vgic_irq
*irq
= vgic_get_irq(vcpu
->kvm
, vcpu
, intid
+ i
);
117 spin_lock_irqsave(&irq
->irq_lock
, flags
);
118 if (irq_is_pending(irq
))
120 spin_unlock_irqrestore(&irq
->irq_lock
, flags
);
122 vgic_put_irq(vcpu
->kvm
, irq
);
128 void vgic_mmio_write_spending(struct kvm_vcpu
*vcpu
,
129 gpa_t addr
, unsigned int len
,
132 u32 intid
= VGIC_ADDR_TO_INTID(addr
, 1);
136 for_each_set_bit(i
, &val
, len
* 8) {
137 struct vgic_irq
*irq
= vgic_get_irq(vcpu
->kvm
, vcpu
, intid
+ i
);
139 spin_lock_irqsave(&irq
->irq_lock
, flags
);
140 irq
->pending_latch
= true;
142 vgic_queue_irq_unlock(vcpu
->kvm
, irq
, flags
);
143 vgic_put_irq(vcpu
->kvm
, irq
);
147 void vgic_mmio_write_cpending(struct kvm_vcpu
*vcpu
,
148 gpa_t addr
, unsigned int len
,
151 u32 intid
= VGIC_ADDR_TO_INTID(addr
, 1);
155 for_each_set_bit(i
, &val
, len
* 8) {
156 struct vgic_irq
*irq
= vgic_get_irq(vcpu
->kvm
, vcpu
, intid
+ i
);
158 spin_lock_irqsave(&irq
->irq_lock
, flags
);
160 irq
->pending_latch
= false;
162 spin_unlock_irqrestore(&irq
->irq_lock
, flags
);
163 vgic_put_irq(vcpu
->kvm
, irq
);
167 unsigned long vgic_mmio_read_active(struct kvm_vcpu
*vcpu
,
168 gpa_t addr
, unsigned int len
)
170 u32 intid
= VGIC_ADDR_TO_INTID(addr
, 1);
174 /* Loop over all IRQs affected by this read */
175 for (i
= 0; i
< len
* 8; i
++) {
176 struct vgic_irq
*irq
= vgic_get_irq(vcpu
->kvm
, vcpu
, intid
+ i
);
181 vgic_put_irq(vcpu
->kvm
, irq
);
187 static void vgic_mmio_change_active(struct kvm_vcpu
*vcpu
, struct vgic_irq
*irq
,
188 bool new_active_state
)
190 struct kvm_vcpu
*requester_vcpu
;
192 spin_lock_irqsave(&irq
->irq_lock
, flags
);
195 * The vcpu parameter here can mean multiple things depending on how
196 * this function is called; when handling a trap from the kernel it
197 * depends on the GIC version, and these functions are also called as
198 * part of save/restore from userspace.
200 * Therefore, we have to figure out the requester in a reliable way.
202 * When accessing VGIC state from user space, the requester_vcpu is
203 * NULL, which is fine, because we guarantee that no VCPUs are running
204 * when accessing VGIC state from user space so irq->vcpu->cpu is
207 requester_vcpu
= kvm_arm_get_running_vcpu();
209 irq
->active
= new_active_state
;
210 if (new_active_state
)
211 vgic_queue_irq_unlock(vcpu
->kvm
, irq
, flags
);
213 spin_unlock_irqrestore(&irq
->irq_lock
, flags
);
217 * If we are fiddling with an IRQ's active state, we have to make sure the IRQ
218 * is not queued on some running VCPU's LRs, because then the change to the
219 * active state can be overwritten when the VCPU's state is synced coming back
222 * For shared interrupts, we have to stop all the VCPUs because interrupts can
223 * be migrated while we don't hold the IRQ locks and we don't want to be
224 * chasing moving targets.
226 * For private interrupts we don't have to do anything because userspace
227 * accesses to the VGIC state already require all VCPUs to be stopped, and
228 * only the VCPU itself can modify its private interrupts active state, which
229 * guarantees that the VCPU is not running.
231 static void vgic_change_active_prepare(struct kvm_vcpu
*vcpu
, u32 intid
)
233 if (vcpu
->kvm
->arch
.vgic
.vgic_model
== KVM_DEV_TYPE_ARM_VGIC_V3
||
234 intid
> VGIC_NR_PRIVATE_IRQS
)
235 kvm_arm_halt_guest(vcpu
->kvm
);
238 /* See vgic_change_active_prepare */
239 static void vgic_change_active_finish(struct kvm_vcpu
*vcpu
, u32 intid
)
241 if (vcpu
->kvm
->arch
.vgic
.vgic_model
== KVM_DEV_TYPE_ARM_VGIC_V3
||
242 intid
> VGIC_NR_PRIVATE_IRQS
)
243 kvm_arm_resume_guest(vcpu
->kvm
);
246 static void __vgic_mmio_write_cactive(struct kvm_vcpu
*vcpu
,
247 gpa_t addr
, unsigned int len
,
250 u32 intid
= VGIC_ADDR_TO_INTID(addr
, 1);
253 for_each_set_bit(i
, &val
, len
* 8) {
254 struct vgic_irq
*irq
= vgic_get_irq(vcpu
->kvm
, vcpu
, intid
+ i
);
255 vgic_mmio_change_active(vcpu
, irq
, false);
256 vgic_put_irq(vcpu
->kvm
, irq
);
260 void vgic_mmio_write_cactive(struct kvm_vcpu
*vcpu
,
261 gpa_t addr
, unsigned int len
,
264 u32 intid
= VGIC_ADDR_TO_INTID(addr
, 1);
266 mutex_lock(&vcpu
->kvm
->lock
);
267 vgic_change_active_prepare(vcpu
, intid
);
269 __vgic_mmio_write_cactive(vcpu
, addr
, len
, val
);
271 vgic_change_active_finish(vcpu
, intid
);
272 mutex_unlock(&vcpu
->kvm
->lock
);
275 void vgic_mmio_uaccess_write_cactive(struct kvm_vcpu
*vcpu
,
276 gpa_t addr
, unsigned int len
,
279 __vgic_mmio_write_cactive(vcpu
, addr
, len
, val
);
282 static void __vgic_mmio_write_sactive(struct kvm_vcpu
*vcpu
,
283 gpa_t addr
, unsigned int len
,
286 u32 intid
= VGIC_ADDR_TO_INTID(addr
, 1);
289 for_each_set_bit(i
, &val
, len
* 8) {
290 struct vgic_irq
*irq
= vgic_get_irq(vcpu
->kvm
, vcpu
, intid
+ i
);
291 vgic_mmio_change_active(vcpu
, irq
, true);
292 vgic_put_irq(vcpu
->kvm
, irq
);
296 void vgic_mmio_write_sactive(struct kvm_vcpu
*vcpu
,
297 gpa_t addr
, unsigned int len
,
300 u32 intid
= VGIC_ADDR_TO_INTID(addr
, 1);
302 mutex_lock(&vcpu
->kvm
->lock
);
303 vgic_change_active_prepare(vcpu
, intid
);
305 __vgic_mmio_write_sactive(vcpu
, addr
, len
, val
);
307 vgic_change_active_finish(vcpu
, intid
);
308 mutex_unlock(&vcpu
->kvm
->lock
);
311 void vgic_mmio_uaccess_write_sactive(struct kvm_vcpu
*vcpu
,
312 gpa_t addr
, unsigned int len
,
315 __vgic_mmio_write_sactive(vcpu
, addr
, len
, val
);
318 unsigned long vgic_mmio_read_priority(struct kvm_vcpu
*vcpu
,
319 gpa_t addr
, unsigned int len
)
321 u32 intid
= VGIC_ADDR_TO_INTID(addr
, 8);
325 for (i
= 0; i
< len
; i
++) {
326 struct vgic_irq
*irq
= vgic_get_irq(vcpu
->kvm
, vcpu
, intid
+ i
);
328 val
|= (u64
)irq
->priority
<< (i
* 8);
330 vgic_put_irq(vcpu
->kvm
, irq
);
337 * We currently don't handle changing the priority of an interrupt that
338 * is already pending on a VCPU. If there is a need for this, we would
339 * need to make this VCPU exit and re-evaluate the priorities, potentially
340 * leading to this interrupt getting presented now to the guest (if it has
341 * been masked by the priority mask before).
343 void vgic_mmio_write_priority(struct kvm_vcpu
*vcpu
,
344 gpa_t addr
, unsigned int len
,
347 u32 intid
= VGIC_ADDR_TO_INTID(addr
, 8);
351 for (i
= 0; i
< len
; i
++) {
352 struct vgic_irq
*irq
= vgic_get_irq(vcpu
->kvm
, vcpu
, intid
+ i
);
354 spin_lock_irqsave(&irq
->irq_lock
, flags
);
355 /* Narrow the priority range to what we actually support */
356 irq
->priority
= (val
>> (i
* 8)) & GENMASK(7, 8 - VGIC_PRI_BITS
);
357 spin_unlock_irqrestore(&irq
->irq_lock
, flags
);
359 vgic_put_irq(vcpu
->kvm
, irq
);
363 unsigned long vgic_mmio_read_config(struct kvm_vcpu
*vcpu
,
364 gpa_t addr
, unsigned int len
)
366 u32 intid
= VGIC_ADDR_TO_INTID(addr
, 2);
370 for (i
= 0; i
< len
* 4; i
++) {
371 struct vgic_irq
*irq
= vgic_get_irq(vcpu
->kvm
, vcpu
, intid
+ i
);
373 if (irq
->config
== VGIC_CONFIG_EDGE
)
374 value
|= (2U << (i
* 2));
376 vgic_put_irq(vcpu
->kvm
, irq
);
382 void vgic_mmio_write_config(struct kvm_vcpu
*vcpu
,
383 gpa_t addr
, unsigned int len
,
386 u32 intid
= VGIC_ADDR_TO_INTID(addr
, 2);
390 for (i
= 0; i
< len
* 4; i
++) {
391 struct vgic_irq
*irq
;
394 * The configuration cannot be changed for SGIs in general,
395 * for PPIs this is IMPLEMENTATION DEFINED. The arch timer
396 * code relies on PPIs being level triggered, so we also
397 * make them read-only here.
399 if (intid
+ i
< VGIC_NR_PRIVATE_IRQS
)
402 irq
= vgic_get_irq(vcpu
->kvm
, vcpu
, intid
+ i
);
403 spin_lock_irqsave(&irq
->irq_lock
, flags
);
405 if (test_bit(i
* 2 + 1, &val
))
406 irq
->config
= VGIC_CONFIG_EDGE
;
408 irq
->config
= VGIC_CONFIG_LEVEL
;
410 spin_unlock_irqrestore(&irq
->irq_lock
, flags
);
411 vgic_put_irq(vcpu
->kvm
, irq
);
415 u64
vgic_read_irq_line_level_info(struct kvm_vcpu
*vcpu
, u32 intid
)
419 int nr_irqs
= vcpu
->kvm
->arch
.vgic
.nr_spis
+ VGIC_NR_PRIVATE_IRQS
;
421 for (i
= 0; i
< 32; i
++) {
422 struct vgic_irq
*irq
;
424 if ((intid
+ i
) < VGIC_NR_SGIS
|| (intid
+ i
) >= nr_irqs
)
427 irq
= vgic_get_irq(vcpu
->kvm
, vcpu
, intid
+ i
);
428 if (irq
->config
== VGIC_CONFIG_LEVEL
&& irq
->line_level
)
431 vgic_put_irq(vcpu
->kvm
, irq
);
437 void vgic_write_irq_line_level_info(struct kvm_vcpu
*vcpu
, u32 intid
,
441 int nr_irqs
= vcpu
->kvm
->arch
.vgic
.nr_spis
+ VGIC_NR_PRIVATE_IRQS
;
444 for (i
= 0; i
< 32; i
++) {
445 struct vgic_irq
*irq
;
448 if ((intid
+ i
) < VGIC_NR_SGIS
|| (intid
+ i
) >= nr_irqs
)
451 irq
= vgic_get_irq(vcpu
->kvm
, vcpu
, intid
+ i
);
454 * Line level is set irrespective of irq type
455 * (level or edge) to avoid dependency that VM should
456 * restore irq config before line level.
458 new_level
= !!(val
& (1U << i
));
459 spin_lock_irqsave(&irq
->irq_lock
, flags
);
460 irq
->line_level
= new_level
;
462 vgic_queue_irq_unlock(vcpu
->kvm
, irq
, flags
);
464 spin_unlock_irqrestore(&irq
->irq_lock
, flags
);
466 vgic_put_irq(vcpu
->kvm
, irq
);
470 static int match_region(const void *key
, const void *elt
)
472 const unsigned int offset
= (unsigned long)key
;
473 const struct vgic_register_region
*region
= elt
;
475 if (offset
< region
->reg_offset
)
478 if (offset
>= region
->reg_offset
+ region
->len
)
484 const struct vgic_register_region
*
485 vgic_find_mmio_region(const struct vgic_register_region
*regions
,
486 int nr_regions
, unsigned int offset
)
488 return bsearch((void *)(uintptr_t)offset
, regions
, nr_regions
,
489 sizeof(regions
[0]), match_region
);
492 void vgic_set_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
)
494 if (kvm_vgic_global_state
.type
== VGIC_V2
)
495 vgic_v2_set_vmcr(vcpu
, vmcr
);
497 vgic_v3_set_vmcr(vcpu
, vmcr
);
500 void vgic_get_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
)
502 if (kvm_vgic_global_state
.type
== VGIC_V2
)
503 vgic_v2_get_vmcr(vcpu
, vmcr
);
505 vgic_v3_get_vmcr(vcpu
, vmcr
);
509 * kvm_mmio_read_buf() returns a value in a format where it can be converted
510 * to a byte array and be directly observed as the guest wanted it to appear
511 * in memory if it had done the store itself, which is LE for the GIC, as the
512 * guest knows the GIC is always LE.
514 * We convert this value to the CPUs native format to deal with it as a data
517 unsigned long vgic_data_mmio_bus_to_host(const void *val
, unsigned int len
)
519 unsigned long data
= kvm_mmio_read_buf(val
, len
);
525 return le16_to_cpu(data
);
527 return le32_to_cpu(data
);
529 return le64_to_cpu(data
);
534 * kvm_mmio_write_buf() expects a value in a format such that if converted to
535 * a byte array it is observed as the guest would see it if it could perform
536 * the load directly. Since the GIC is LE, and the guest knows this, the
537 * guest expects a value in little endian format.
539 * We convert the data value from the CPUs native format to LE so that the
540 * value is returned in the proper format.
542 void vgic_data_host_to_mmio_bus(void *buf
, unsigned int len
,
549 data
= cpu_to_le16(data
);
552 data
= cpu_to_le32(data
);
555 data
= cpu_to_le64(data
);
558 kvm_mmio_write_buf(buf
, len
, data
);
562 struct vgic_io_device
*kvm_to_vgic_iodev(const struct kvm_io_device
*dev
)
564 return container_of(dev
, struct vgic_io_device
, dev
);
567 static bool check_region(const struct kvm
*kvm
,
568 const struct vgic_register_region
*region
,
571 int flags
, nr_irqs
= kvm
->arch
.vgic
.nr_spis
+ VGIC_NR_PRIVATE_IRQS
;
575 flags
= VGIC_ACCESS_8bit
;
578 flags
= VGIC_ACCESS_32bit
;
581 flags
= VGIC_ACCESS_64bit
;
587 if ((region
->access_flags
& flags
) && IS_ALIGNED(addr
, len
)) {
588 if (!region
->bits_per_irq
)
591 /* Do we access a non-allocated IRQ? */
592 return VGIC_ADDR_TO_INTID(addr
, region
->bits_per_irq
) < nr_irqs
;
598 const struct vgic_register_region
*
599 vgic_get_mmio_region(struct kvm_vcpu
*vcpu
, struct vgic_io_device
*iodev
,
602 const struct vgic_register_region
*region
;
604 region
= vgic_find_mmio_region(iodev
->regions
, iodev
->nr_regions
,
605 addr
- iodev
->base_addr
);
606 if (!region
|| !check_region(vcpu
->kvm
, region
, addr
, len
))
612 static int vgic_uaccess_read(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*dev
,
613 gpa_t addr
, u32
*val
)
615 struct vgic_io_device
*iodev
= kvm_to_vgic_iodev(dev
);
616 const struct vgic_register_region
*region
;
617 struct kvm_vcpu
*r_vcpu
;
619 region
= vgic_get_mmio_region(vcpu
, iodev
, addr
, sizeof(u32
));
625 r_vcpu
= iodev
->redist_vcpu
? iodev
->redist_vcpu
: vcpu
;
626 if (region
->uaccess_read
)
627 *val
= region
->uaccess_read(r_vcpu
, addr
, sizeof(u32
));
629 *val
= region
->read(r_vcpu
, addr
, sizeof(u32
));
634 static int vgic_uaccess_write(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*dev
,
635 gpa_t addr
, const u32
*val
)
637 struct vgic_io_device
*iodev
= kvm_to_vgic_iodev(dev
);
638 const struct vgic_register_region
*region
;
639 struct kvm_vcpu
*r_vcpu
;
641 region
= vgic_get_mmio_region(vcpu
, iodev
, addr
, sizeof(u32
));
645 r_vcpu
= iodev
->redist_vcpu
? iodev
->redist_vcpu
: vcpu
;
646 if (region
->uaccess_write
)
647 region
->uaccess_write(r_vcpu
, addr
, sizeof(u32
), *val
);
649 region
->write(r_vcpu
, addr
, sizeof(u32
), *val
);
655 * Userland access to VGIC registers.
657 int vgic_uaccess(struct kvm_vcpu
*vcpu
, struct vgic_io_device
*dev
,
658 bool is_write
, int offset
, u32
*val
)
661 return vgic_uaccess_write(vcpu
, &dev
->dev
, offset
, val
);
663 return vgic_uaccess_read(vcpu
, &dev
->dev
, offset
, val
);
666 static int dispatch_mmio_read(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*dev
,
667 gpa_t addr
, int len
, void *val
)
669 struct vgic_io_device
*iodev
= kvm_to_vgic_iodev(dev
);
670 const struct vgic_register_region
*region
;
671 unsigned long data
= 0;
673 region
= vgic_get_mmio_region(vcpu
, iodev
, addr
, len
);
679 switch (iodev
->iodev_type
) {
681 data
= region
->read(vcpu
, addr
, len
);
684 data
= region
->read(vcpu
, addr
, len
);
687 data
= region
->read(iodev
->redist_vcpu
, addr
, len
);
690 data
= region
->its_read(vcpu
->kvm
, iodev
->its
, addr
, len
);
694 vgic_data_host_to_mmio_bus(val
, len
, data
);
698 static int dispatch_mmio_write(struct kvm_vcpu
*vcpu
, struct kvm_io_device
*dev
,
699 gpa_t addr
, int len
, const void *val
)
701 struct vgic_io_device
*iodev
= kvm_to_vgic_iodev(dev
);
702 const struct vgic_register_region
*region
;
703 unsigned long data
= vgic_data_mmio_bus_to_host(val
, len
);
705 region
= vgic_get_mmio_region(vcpu
, iodev
, addr
, len
);
709 switch (iodev
->iodev_type
) {
711 region
->write(vcpu
, addr
, len
, data
);
714 region
->write(vcpu
, addr
, len
, data
);
717 region
->write(iodev
->redist_vcpu
, addr
, len
, data
);
720 region
->its_write(vcpu
->kvm
, iodev
->its
, addr
, len
, data
);
727 struct kvm_io_device_ops kvm_io_gic_ops
= {
728 .read
= dispatch_mmio_read
,
729 .write
= dispatch_mmio_write
,
732 int vgic_register_dist_iodev(struct kvm
*kvm
, gpa_t dist_base_address
,
735 struct vgic_io_device
*io_device
= &kvm
->arch
.vgic
.dist_iodev
;
741 len
= vgic_v2_init_dist_iodev(io_device
);
744 len
= vgic_v3_init_dist_iodev(io_device
);
750 io_device
->base_addr
= dist_base_address
;
751 io_device
->iodev_type
= IODEV_DIST
;
752 io_device
->redist_vcpu
= NULL
;
754 mutex_lock(&kvm
->slots_lock
);
755 ret
= kvm_io_bus_register_dev(kvm
, KVM_MMIO_BUS
, dist_base_address
,
756 len
, &io_device
->dev
);
757 mutex_unlock(&kvm
->slots_lock
);