2 * Copyright (C) 2015, 2016 ARM Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/irqchip/arm-gic.h>
18 #include <linux/kvm.h>
19 #include <linux/kvm_host.h>
20 #include <kvm/arm_vgic.h>
21 #include <asm/kvm_mmu.h>
26 * Call this function to convert a u64 value to an unsigned long * bitmask
27 * in a way that works on both 32-bit and 64-bit LE and BE platforms.
29 * Warning: Calling this function may modify *val.
31 static unsigned long *u64_to_bitmask(u64
*val
)
33 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32
34 *val
= (*val
>> 32) | (*val
<< 32);
36 return (unsigned long *)val
;
39 void vgic_v2_process_maintenance(struct kvm_vcpu
*vcpu
)
41 struct vgic_v2_cpu_if
*cpuif
= &vcpu
->arch
.vgic_cpu
.vgic_v2
;
43 if (cpuif
->vgic_misr
& GICH_MISR_EOI
) {
44 u64 eisr
= cpuif
->vgic_eisr
;
45 unsigned long *eisr_bmap
= u64_to_bitmask(&eisr
);
48 for_each_set_bit(lr
, eisr_bmap
, kvm_vgic_global_state
.nr_lr
) {
49 u32 intid
= cpuif
->vgic_lr
[lr
] & GICH_LR_VIRTUALID
;
51 WARN_ON(cpuif
->vgic_lr
[lr
] & GICH_LR_STATE
);
53 kvm_notify_acked_irq(vcpu
->kvm
, 0,
54 intid
- VGIC_NR_PRIVATE_IRQS
);
58 /* check and disable underflow maintenance IRQ */
59 cpuif
->vgic_hcr
&= ~GICH_HCR_UIE
;
62 * In the next iterations of the vcpu loop, if we sync the
63 * vgic state after flushing it, but before entering the guest
64 * (this happens for pending signals and vmid rollovers), then
65 * make sure we don't pick up any old maintenance interrupts
71 void vgic_v2_set_underflow(struct kvm_vcpu
*vcpu
)
73 struct vgic_v2_cpu_if
*cpuif
= &vcpu
->arch
.vgic_cpu
.vgic_v2
;
75 cpuif
->vgic_hcr
|= GICH_HCR_UIE
;
79 * transfer the content of the LRs back into the corresponding ap_list:
80 * - active bit is transferred as is
82 * - transferred as is in case of edge sensitive IRQs
83 * - set to the line-level (resample time) for level sensitive IRQs
85 void vgic_v2_fold_lr_state(struct kvm_vcpu
*vcpu
)
87 struct vgic_v2_cpu_if
*cpuif
= &vcpu
->arch
.vgic_cpu
.vgic_v2
;
90 for (lr
= 0; lr
< vcpu
->arch
.vgic_cpu
.used_lrs
; lr
++) {
91 u32 val
= cpuif
->vgic_lr
[lr
];
92 u32 intid
= val
& GICH_LR_VIRTUALID
;
95 irq
= vgic_get_irq(vcpu
->kvm
, vcpu
, intid
);
97 spin_lock(&irq
->irq_lock
);
99 /* Always preserve the active bit */
100 irq
->active
= !!(val
& GICH_LR_ACTIVE_BIT
);
102 /* Edge is the only case where we preserve the pending bit */
103 if (irq
->config
== VGIC_CONFIG_EDGE
&&
104 (val
& GICH_LR_PENDING_BIT
)) {
107 if (vgic_irq_is_sgi(intid
)) {
108 u32 cpuid
= val
& GICH_LR_PHYSID_CPUID
;
110 cpuid
>>= GICH_LR_PHYSID_CPUID_SHIFT
;
111 irq
->source
|= (1 << cpuid
);
115 /* Clear soft pending state when level IRQs have been acked */
116 if (irq
->config
== VGIC_CONFIG_LEVEL
&&
117 !(val
& GICH_LR_PENDING_BIT
)) {
118 irq
->soft_pending
= false;
119 irq
->pending
= irq
->line_level
;
122 spin_unlock(&irq
->irq_lock
);
127 * Populates the particular LR with the state of a given IRQ:
128 * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
129 * - for a level sensitive IRQ the pending state value is unchanged;
130 * it is dictated directly by the input level
132 * If @irq describes an SGI with multiple sources, we choose the
133 * lowest-numbered source VCPU and clear that bit in the source bitmap.
135 * The irq_lock must be held by the caller.
137 void vgic_v2_populate_lr(struct kvm_vcpu
*vcpu
, struct vgic_irq
*irq
, int lr
)
139 u32 val
= irq
->intid
;
142 val
|= GICH_LR_PENDING_BIT
;
144 if (irq
->config
== VGIC_CONFIG_EDGE
)
145 irq
->pending
= false;
147 if (vgic_irq_is_sgi(irq
->intid
)) {
148 u32 src
= ffs(irq
->source
);
151 val
|= (src
- 1) << GICH_LR_PHYSID_CPUID_SHIFT
;
152 irq
->source
&= ~(1 << (src
- 1));
159 val
|= GICH_LR_ACTIVE_BIT
;
163 val
|= irq
->hwintid
<< GICH_LR_PHYSID_CPUID_SHIFT
;
165 if (irq
->config
== VGIC_CONFIG_LEVEL
)
169 /* The GICv2 LR only holds five bits of priority. */
170 val
|= (irq
->priority
>> 3) << GICH_LR_PRIORITY_SHIFT
;
172 vcpu
->arch
.vgic_cpu
.vgic_v2
.vgic_lr
[lr
] = val
;
175 void vgic_v2_clear_lr(struct kvm_vcpu
*vcpu
, int lr
)
177 vcpu
->arch
.vgic_cpu
.vgic_v2
.vgic_lr
[lr
] = 0;
180 void vgic_v2_set_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcrp
)
184 vmcr
= (vmcrp
->ctlr
<< GICH_VMCR_CTRL_SHIFT
) & GICH_VMCR_CTRL_MASK
;
185 vmcr
|= (vmcrp
->abpr
<< GICH_VMCR_ALIAS_BINPOINT_SHIFT
) &
186 GICH_VMCR_ALIAS_BINPOINT_MASK
;
187 vmcr
|= (vmcrp
->bpr
<< GICH_VMCR_BINPOINT_SHIFT
) &
188 GICH_VMCR_BINPOINT_MASK
;
189 vmcr
|= (vmcrp
->pmr
<< GICH_VMCR_PRIMASK_SHIFT
) &
190 GICH_VMCR_PRIMASK_MASK
;
192 vcpu
->arch
.vgic_cpu
.vgic_v2
.vgic_vmcr
= vmcr
;
195 void vgic_v2_get_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcrp
)
197 u32 vmcr
= vcpu
->arch
.vgic_cpu
.vgic_v2
.vgic_vmcr
;
199 vmcrp
->ctlr
= (vmcr
& GICH_VMCR_CTRL_MASK
) >>
200 GICH_VMCR_CTRL_SHIFT
;
201 vmcrp
->abpr
= (vmcr
& GICH_VMCR_ALIAS_BINPOINT_MASK
) >>
202 GICH_VMCR_ALIAS_BINPOINT_SHIFT
;
203 vmcrp
->bpr
= (vmcr
& GICH_VMCR_BINPOINT_MASK
) >>
204 GICH_VMCR_BINPOINT_SHIFT
;
205 vmcrp
->pmr
= (vmcr
& GICH_VMCR_PRIMASK_MASK
) >>
206 GICH_VMCR_PRIMASK_SHIFT
;
209 void vgic_v2_enable(struct kvm_vcpu
*vcpu
)
212 * By forcing VMCR to zero, the GIC will restore the binary
213 * points to their reset values. Anything else resets to zero
216 vcpu
->arch
.vgic_cpu
.vgic_v2
.vgic_vmcr
= 0;
217 vcpu
->arch
.vgic_cpu
.vgic_v2
.vgic_elrsr
= ~0;
219 /* Get the show on the road... */
220 vcpu
->arch
.vgic_cpu
.vgic_v2
.vgic_hcr
= GICH_HCR_EN
;
223 /* check for overlapping regions and for regions crossing the end of memory */
224 static bool vgic_v2_check_base(gpa_t dist_base
, gpa_t cpu_base
)
226 if (dist_base
+ KVM_VGIC_V2_DIST_SIZE
< dist_base
)
228 if (cpu_base
+ KVM_VGIC_V2_CPU_SIZE
< cpu_base
)
231 if (dist_base
+ KVM_VGIC_V2_DIST_SIZE
<= cpu_base
)
233 if (cpu_base
+ KVM_VGIC_V2_CPU_SIZE
<= dist_base
)
239 int vgic_v2_map_resources(struct kvm
*kvm
)
241 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
247 if (IS_VGIC_ADDR_UNDEF(dist
->vgic_dist_base
) ||
248 IS_VGIC_ADDR_UNDEF(dist
->vgic_cpu_base
)) {
249 kvm_err("Need to set vgic cpu and dist addresses first\n");
254 if (!vgic_v2_check_base(dist
->vgic_dist_base
, dist
->vgic_cpu_base
)) {
255 kvm_err("VGIC CPU and dist frames overlap\n");
261 * Initialize the vgic if this hasn't already been done on demand by
262 * accessing the vgic state from userspace.
264 ret
= vgic_init(kvm
);
266 kvm_err("Unable to initialize VGIC dynamic data structures\n");
270 ret
= vgic_register_dist_iodev(kvm
, dist
->vgic_dist_base
, VGIC_V2
);
272 kvm_err("Unable to register VGIC MMIO regions\n");
276 ret
= kvm_phys_addr_ioremap(kvm
, dist
->vgic_cpu_base
,
277 kvm_vgic_global_state
.vcpu_base
,
278 KVM_VGIC_V2_CPU_SIZE
, true);
280 kvm_err("Unable to remap VGIC CPU to VCPU\n");
288 kvm_vgic_destroy(kvm
);
293 * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
294 * @node: pointer to the DT node
296 * Returns 0 if a GICv2 has been found, returns an error code otherwise
298 int vgic_v2_probe(const struct gic_kvm_info
*info
)
303 if (!info
->vctrl
.start
) {
304 kvm_err("GICH not present in the firmware table\n");
308 if (!PAGE_ALIGNED(info
->vcpu
.start
)) {
309 kvm_err("GICV physical address 0x%llx not page aligned\n",
310 (unsigned long long)info
->vcpu
.start
);
314 if (!PAGE_ALIGNED(resource_size(&info
->vcpu
))) {
315 kvm_err("GICV size 0x%llx not a multiple of page size 0x%lx\n",
316 (unsigned long long)resource_size(&info
->vcpu
),
321 kvm_vgic_global_state
.vctrl_base
= ioremap(info
->vctrl
.start
,
322 resource_size(&info
->vctrl
));
323 if (!kvm_vgic_global_state
.vctrl_base
) {
324 kvm_err("Cannot ioremap GICH\n");
328 vtr
= readl_relaxed(kvm_vgic_global_state
.vctrl_base
+ GICH_VTR
);
329 kvm_vgic_global_state
.nr_lr
= (vtr
& 0x3f) + 1;
331 ret
= create_hyp_io_mappings(kvm_vgic_global_state
.vctrl_base
,
332 kvm_vgic_global_state
.vctrl_base
+
333 resource_size(&info
->vctrl
),
337 kvm_err("Cannot map VCTRL into hyp\n");
338 iounmap(kvm_vgic_global_state
.vctrl_base
);
342 kvm_vgic_global_state
.can_emulate_gicv2
= true;
343 kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2
);
345 kvm_vgic_global_state
.vcpu_base
= info
->vcpu
.start
;
346 kvm_vgic_global_state
.type
= VGIC_V2
;
347 kvm_vgic_global_state
.max_gic_vcpus
= VGIC_V2_MAX_CPUS
;
349 kvm_info("vgic-v2@%llx\n", info
->vctrl
.start
);