virt/kvm/arm/vgic/vgic-v2.c

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/irqchip/arm-gic.h>
  18 #include <linux/kvm.h>
  19 #include <linux/kvm_host.h>
  20 #include <kvm/arm_vgic.h>
  21 #include <asm/kvm_mmu.h>
  22
  23 #include "vgic.h"
  24
  25 static inline void vgic_v2_write_lr(int lr, u32 val)
  26 {
  27         void __iomem *base = kvm_vgic_global_state.vctrl_base;
  28
  29         writel_relaxed(val, base + GICH_LR0 + (lr * 4));
  30 }
  31
  32 void vgic_v2_init_lrs(void)
  33 {
  34         int i;
  35
  36         for (i = 0; i < kvm_vgic_global_state.nr_lr; i++)
  37                 vgic_v2_write_lr(i, 0);
  38 }
  39
  40 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
  41 {
  42         struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
  43
  44         cpuif->vgic_hcr |= GICH_HCR_UIE;
  45 }
  46
  47 static bool lr_signals_eoi_mi(u32 lr_val)
  48 {
  49         return !(lr_val & GICH_LR_STATE) && (lr_val & GICH_LR_EOI) &&
  50                !(lr_val & GICH_LR_HW);
  51 }
  52
  53 /*
  54  * transfer the content of the LRs back into the corresponding ap_list:
  55  * - active bit is transferred as is
  56  * - pending bit is
  57  *   - transferred as is in case of edge sensitive IRQs
  58  *   - set to the line-level (resample time) for level sensitive IRQs
  59  */
  60 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
  61 {
  62         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
  63         struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
  64         int lr;
  65         unsigned long flags;
  66
  67         cpuif->vgic_hcr &= ~GICH_HCR_UIE;
  68
  69         for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
  70                 u32 val = cpuif->vgic_lr[lr];
  71                 u32 intid = val & GICH_LR_VIRTUALID;
  72                 struct vgic_irq *irq;
  73
  74                 /* Notify fds when the guest EOI'ed a level-triggered SPI */
  75                 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
  76                         kvm_notify_acked_irq(vcpu->kvm, 0,
  77                                              intid - VGIC_NR_PRIVATE_IRQS);
  78
  79                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
  80
  81                 spin_lock_irqsave(&irq->irq_lock, flags);
  82
  83                 /* Always preserve the active bit */
  84                 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
  85
  86                 /* Edge is the only case where we preserve the pending bit */
  87                 if (irq->config == VGIC_CONFIG_EDGE &&
  88                     (val & GICH_LR_PENDING_BIT)) {
  89                         irq->pending_latch = true;
  90
  91                         if (vgic_irq_is_sgi(intid)) {
  92                                 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
  93
  94                                 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
  95                                 irq->source |= (1 << cpuid);
  96                         }
  97                 }
  98
  99                 /*
 100                  * Clear soft pending state when level irqs have been acked.
 101                  * Always regenerate the pending state.
 102                  */
 103                 if (irq->config == VGIC_CONFIG_LEVEL) {
 104                         if (!(val & GICH_LR_PENDING_BIT))
 105                                 irq->pending_latch = false;
 106                 }
 107
 108                 spin_unlock_irqrestore(&irq->irq_lock, flags);
 109                 vgic_put_irq(vcpu->kvm, irq);
 110         }
 111
 112         vgic_cpu->used_lrs = 0;
 113 }
 114
 115 /*
 116  * Populates the particular LR with the state of a given IRQ:
 117  * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq
 118  * - for a level sensitive IRQ the pending state value is unchanged;
 119  *   it is dictated directly by the input level
 120  *
 121  * If @irq describes an SGI with multiple sources, we choose the
 122  * lowest-numbered source VCPU and clear that bit in the source bitmap.
 123  *
 124  * The irq_lock must be held by the caller.
 125  */
 126 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
 127 {
 128         u32 val = irq->intid;
 129
 130         if (irq_is_pending(irq)) {
 131                 val |= GICH_LR_PENDING_BIT;
 132
 133                 if (irq->config == VGIC_CONFIG_EDGE)
 134                         irq->pending_latch = false;
 135
 136                 if (vgic_irq_is_sgi(irq->intid)) {
 137                         u32 src = ffs(irq->source);
 138
 139                         BUG_ON(!src);
 140                         val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 141                         irq->source &= ~(1 << (src - 1));
 142                         if (irq->source)
 143                                 irq->pending_latch = true;
 144                 }
 145         }
 146
 147         if (irq->active)
 148                 val |= GICH_LR_ACTIVE_BIT;
 149
 150         if (irq->hw) {
 151                 val |= GICH_LR_HW;
 152                 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
 153                 /*
 154                  * Never set pending+active on a HW interrupt, as the
 155                  * pending state is kept at the physical distributor
 156                  * level.
 157                  */
 158                 if (irq->active && irq_is_pending(irq))
 159                         val &= ~GICH_LR_PENDING_BIT;
 160         } else {
 161                 if (irq->config == VGIC_CONFIG_LEVEL)
 162                         val |= GICH_LR_EOI;
 163         }
 164
 165         /* The GICv2 LR only holds five bits of priority. */
 166         val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
 167
 168         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
 169 }
 170
 171 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
 172 {
 173         vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
 174 }
 175
 176 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 177 {
 178         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 179         u32 vmcr;
 180
 181         vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) &
 182                 GICH_VMCR_ENABLE_GRP0_MASK;
 183         vmcr |= (vmcrp->grpen1 << GICH_VMCR_ENABLE_GRP1_SHIFT) &
 184                 GICH_VMCR_ENABLE_GRP1_MASK;
 185         vmcr |= (vmcrp->ackctl << GICH_VMCR_ACK_CTL_SHIFT) &
 186                 GICH_VMCR_ACK_CTL_MASK;
 187         vmcr |= (vmcrp->fiqen << GICH_VMCR_FIQ_EN_SHIFT) &
 188                 GICH_VMCR_FIQ_EN_MASK;
 189         vmcr |= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) &
 190                 GICH_VMCR_CBPR_MASK;
 191         vmcr |= (vmcrp->eoim << GICH_VMCR_EOI_MODE_SHIFT) &
 192                 GICH_VMCR_EOI_MODE_MASK;
 193         vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
 194                 GICH_VMCR_ALIAS_BINPOINT_MASK;
 195         vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
 196                 GICH_VMCR_BINPOINT_MASK;
 197         vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) <<
 198                  GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
 199
 200         cpu_if->vgic_vmcr = vmcr;
 201 }
 202
 203 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 204 {
 205         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 206         u32 vmcr;
 207
 208         vmcr = cpu_if->vgic_vmcr;
 209
 210         vmcrp->grpen0 = (vmcr & GICH_VMCR_ENABLE_GRP0_MASK) >>
 211                 GICH_VMCR_ENABLE_GRP0_SHIFT;
 212         vmcrp->grpen1 = (vmcr & GICH_VMCR_ENABLE_GRP1_MASK) >>
 213                 GICH_VMCR_ENABLE_GRP1_SHIFT;
 214         vmcrp->ackctl = (vmcr & GICH_VMCR_ACK_CTL_MASK) >>
 215                 GICH_VMCR_ACK_CTL_SHIFT;
 216         vmcrp->fiqen = (vmcr & GICH_VMCR_FIQ_EN_MASK) >>
 217                 GICH_VMCR_FIQ_EN_SHIFT;
 218         vmcrp->cbpr = (vmcr & GICH_VMCR_CBPR_MASK) >>
 219                 GICH_VMCR_CBPR_SHIFT;
 220         vmcrp->eoim = (vmcr & GICH_VMCR_EOI_MODE_MASK) >>
 221                 GICH_VMCR_EOI_MODE_SHIFT;
 222
 223         vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
 224                         GICH_VMCR_ALIAS_BINPOINT_SHIFT;
 225         vmcrp->bpr  = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
 226                         GICH_VMCR_BINPOINT_SHIFT;
 227         vmcrp->pmr  = ((vmcr & GICH_VMCR_PRIMASK_MASK) >>
 228                         GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT;
 229 }
 230
 231 void vgic_v2_enable(struct kvm_vcpu *vcpu)
 232 {
 233         /*
 234          * By forcing VMCR to zero, the GIC will restore the binary
 235          * points to their reset values. Anything else resets to zero
 236          * anyway.
 237          */
 238         vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
 239         vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;
 240
 241         /* Get the show on the road... */
 242         vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
 243 }
 244
 245 /* check for overlapping regions and for regions crossing the end of memory */
 246 static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
 247 {
 248         if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
 249                 return false;
 250         if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
 251                 return false;
 252
 253         if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
 254                 return true;
 255         if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
 256                 return true;
 257
 258         return false;
 259 }
 260
 261 int vgic_v2_map_resources(struct kvm *kvm)
 262 {
 263         struct vgic_dist *dist = &kvm->arch.vgic;
 264         int ret = 0;
 265
 266         if (vgic_ready(kvm))
 267                 goto out;
 268
 269         if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
 270             IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
 271                 kvm_err("Need to set vgic cpu and dist addresses first\n");
 272                 ret = -ENXIO;
 273                 goto out;
 274         }
 275
 276         if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
 277                 kvm_err("VGIC CPU and dist frames overlap\n");
 278                 ret = -EINVAL;
 279                 goto out;
 280         }
 281
 282         /*
 283          * Initialize the vgic if this hasn't already been done on demand by
 284          * accessing the vgic state from userspace.
 285          */
 286         ret = vgic_init(kvm);
 287         if (ret) {
 288                 kvm_err("Unable to initialize VGIC dynamic data structures\n");
 289                 goto out;
 290         }
 291
 292         ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
 293         if (ret) {
 294                 kvm_err("Unable to register VGIC MMIO regions\n");
 295                 goto out;
 296         }
 297
 298         if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
 299                 ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
 300                                             kvm_vgic_global_state.vcpu_base,
 301                                             KVM_VGIC_V2_CPU_SIZE, true);
 302                 if (ret) {
 303                         kvm_err("Unable to remap VGIC CPU to VCPU\n");
 304                         goto out;
 305                 }
 306         }
 307
 308         dist->ready = true;
 309
 310 out:
 311         return ret;
 312 }
 313
 314 DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);
 315
 316 /**
 317  * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
 318  * @node:       pointer to the DT node
 319  *
 320  * Returns 0 if a GICv2 has been found, returns an error code otherwise
 321  */
 322 int vgic_v2_probe(const struct gic_kvm_info *info)
 323 {
 324         int ret;
 325         u32 vtr;
 326
 327         if (!info->vctrl.start) {
 328                 kvm_err("GICH not present in the firmware table\n");
 329                 return -ENXIO;
 330         }
 331
 332         if (!PAGE_ALIGNED(info->vcpu.start) ||
 333             !PAGE_ALIGNED(resource_size(&info->vcpu))) {
 334                 kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");
 335                 kvm_vgic_global_state.vcpu_base_va = ioremap(info->vcpu.start,
 336                                                              resource_size(&info->vcpu));
 337                 if (!kvm_vgic_global_state.vcpu_base_va) {
 338                         kvm_err("Cannot ioremap GICV\n");
 339                         return -ENOMEM;
 340                 }
 341
 342                 ret = create_hyp_io_mappings(kvm_vgic_global_state.vcpu_base_va,
 343                                              kvm_vgic_global_state.vcpu_base_va + resource_size(&info->vcpu),
 344                                              info->vcpu.start);
 345                 if (ret) {
 346                         kvm_err("Cannot map GICV into hyp\n");
 347                         goto out;
 348                 }
 349
 350                 static_branch_enable(&vgic_v2_cpuif_trap);
 351         }
 352
 353         kvm_vgic_global_state.vctrl_base = ioremap(info->vctrl.start,
 354                                                    resource_size(&info->vctrl));
 355         if (!kvm_vgic_global_state.vctrl_base) {
 356                 kvm_err("Cannot ioremap GICH\n");
 357                 ret = -ENOMEM;
 358                 goto out;
 359         }
 360
 361         vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
 362         kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
 363
 364         ret = create_hyp_io_mappings(kvm_vgic_global_state.vctrl_base,
 365                                      kvm_vgic_global_state.vctrl_base +
 366                                          resource_size(&info->vctrl),
 367                                      info->vctrl.start);
 368         if (ret) {
 369                 kvm_err("Cannot map VCTRL into hyp\n");
 370                 goto out;
 371         }
 372
 373         ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
 374         if (ret) {
 375                 kvm_err("Cannot register GICv2 KVM device\n");
 376                 goto out;
 377         }
 378
 379         kvm_vgic_global_state.can_emulate_gicv2 = true;
 380         kvm_vgic_global_state.vcpu_base = info->vcpu.start;
 381         kvm_vgic_global_state.type = VGIC_V2;
 382         kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
 383
 384         kvm_info("vgic-v2@%llx\n", info->vctrl.start);
 385
 386         return 0;
 387 out:
 388         if (kvm_vgic_global_state.vctrl_base)
 389                 iounmap(kvm_vgic_global_state.vctrl_base);
 390         if (kvm_vgic_global_state.vcpu_base_va)
 391                 iounmap(kvm_vgic_global_state.vcpu_base_va);
 392
 393         return ret;
 394 }
 395
 396 void vgic_v2_load(struct kvm_vcpu *vcpu)
 397 {
 398         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 399         struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
 400
 401         writel_relaxed(cpu_if->vgic_vmcr, vgic->vctrl_base + GICH_VMCR);
 402 }
 403
 404 void vgic_v2_put(struct kvm_vcpu *vcpu)
 405 {
 406         struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
 407         struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
 408
 409         cpu_if->vgic_vmcr = readl_relaxed(vgic->vctrl_base + GICH_VMCR);
 410 }