virt/kvm/arm/vgic/vgic-v3.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program. If not, see <http://www.gnu.org/licenses/>.
  13  */
  14
  15 #include <linux/irqchip/arm-gic-v3.h>
  16 #include <linux/kvm.h>
  17 #include <linux/kvm_host.h>
  18 #include <kvm/arm_vgic.h>
  19 #include <asm/kvm_mmu.h>
  20 #include <asm/kvm_asm.h>
  21
  22 #include "vgic.h"
  23
  24 static bool group0_trap;
  25 static bool group1_trap;
  26 static bool common_trap;
  27 static bool gicv4_enable;
  28
  29 void vgic_v3_set_npie(struct kvm_vcpu *vcpu)
  30 {
  31         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
  32
  33         cpuif->vgic_hcr |= ICH_HCR_NPIE;
  34 }
  35
  36 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
  37 {
  38         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
  39
  40         cpuif->vgic_hcr |= ICH_HCR_UIE;
  41 }
  42
  43 static bool lr_signals_eoi_mi(u64 lr_val)
  44 {
  45         return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) &&
  46                !(lr_val & ICH_LR_HW);
  47 }
  48
  49 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
  50 {
  51         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
  52         struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3;
  53         u32 model = vcpu->kvm->arch.vgic.vgic_model;
  54         int lr;
  55         unsigned long flags;
  56
  57         cpuif->vgic_hcr &= ~(ICH_HCR_UIE | ICH_HCR_NPIE);
  58
  59         for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
  60                 u64 val = cpuif->vgic_lr[lr];
  61                 u32 intid;
  62                 struct vgic_irq *irq;
  63
  64                 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
  65                         intid = val & ICH_LR_VIRTUAL_ID_MASK;
  66                 else
  67                         intid = val & GICH_LR_VIRTUALID;
  68
  69                 /* Notify fds when the guest EOI'ed a level-triggered IRQ */
  70                 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
  71                         kvm_notify_acked_irq(vcpu->kvm, 0,
  72                                              intid - VGIC_NR_PRIVATE_IRQS);
  73
  74                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
  75                 if (!irq)       /* An LPI could have been unmapped. */
  76                         continue;
  77
  78                 spin_lock_irqsave(&irq->irq_lock, flags);
  79
  80                 /* Always preserve the active bit */
  81                 irq->active = !!(val & ICH_LR_ACTIVE_BIT);
  82
  83                 /* Edge is the only case where we preserve the pending bit */
  84                 if (irq->config == VGIC_CONFIG_EDGE &&
  85                     (val & ICH_LR_PENDING_BIT)) {
  86                         irq->pending_latch = true;
  87
  88                         if (vgic_irq_is_sgi(intid) &&
  89                             model == KVM_DEV_TYPE_ARM_VGIC_V2) {
  90                                 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
  91
  92                                 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
  93                                 irq->source |= (1 << cpuid);
  94                         }
  95                 }
  96
  97                 /*
  98                  * Clear soft pending state when level irqs have been acked.
  99                  * Always regenerate the pending state.
 100                  */
 101                 if (irq->config == VGIC_CONFIG_LEVEL) {
 102                         if (!(val & ICH_LR_PENDING_BIT))
 103                                 irq->pending_latch = false;
 104                 }
 105
 106                 spin_unlock_irqrestore(&irq->irq_lock, flags);
 107                 vgic_put_irq(vcpu->kvm, irq);
 108         }
 109
 110         vgic_cpu->used_lrs = 0;
 111 }
 112
 113 /* Requires the irq to be locked already */
 114 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
 115 {
 116         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 117         u64 val = irq->intid;
 118
 119         if (irq_is_pending(irq)) {
 120                 val |= ICH_LR_PENDING_BIT;
 121
 122                 if (irq->config == VGIC_CONFIG_EDGE)
 123                         irq->pending_latch = false;
 124
 125                 if (vgic_irq_is_sgi(irq->intid) &&
 126                     model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 127                         u32 src = ffs(irq->source);
 128
 129                         if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n",
 130                                            irq->intid))
 131                                 return;
 132
 133                         val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 134                         irq->source &= ~(1 << (src - 1));
 135                         if (irq->source)
 136                                 irq->pending_latch = true;
 137                 }
 138         }
 139
 140         if (irq->active)
 141                 val |= ICH_LR_ACTIVE_BIT;
 142
 143         if (irq->hw) {
 144                 val |= ICH_LR_HW;
 145                 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
 146                 /*
 147                  * Never set pending+active on a HW interrupt, as the
 148                  * pending state is kept at the physical distributor
 149                  * level.
 150                  */
 151                 if (irq->active && irq_is_pending(irq))
 152                         val &= ~ICH_LR_PENDING_BIT;
 153         } else {
 154                 if (irq->config == VGIC_CONFIG_LEVEL)
 155                         val |= ICH_LR_EOI;
 156         }
 157
 158         /*
 159          * We currently only support Group1 interrupts, which is a
 160          * known defect. This needs to be addressed at some point.
 161          */
 162         if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
 163                 val |= ICH_LR_GROUP;
 164
 165         val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
 166
 167         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
 168 }
 169
 170 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
 171 {
 172         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
 173 }
 174
 175 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 176 {
 177         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 178         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 179         u32 vmcr;
 180
 181         if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 182                 vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) &
 183                         ICH_VMCR_ACK_CTL_MASK;
 184                 vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) &
 185                         ICH_VMCR_FIQ_EN_MASK;
 186         } else {
 187                 /*
 188                  * When emulating GICv3 on GICv3 with SRE=1 on the
 189                  * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
 190                  */
 191                 vmcr = ICH_VMCR_FIQ_EN_MASK;
 192         }
 193
 194         vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
 195         vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
 196         vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
 197         vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
 198         vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
 199         vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
 200         vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
 201
 202         cpu_if->vgic_vmcr = vmcr;
 203 }
 204
 205 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 206 {
 207         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 208         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 209         u32 vmcr;
 210
 211         vmcr = cpu_if->vgic_vmcr;
 212
 213         if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 214                 vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >>
 215                         ICH_VMCR_ACK_CTL_SHIFT;
 216                 vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >>
 217                         ICH_VMCR_FIQ_EN_SHIFT;
 218         } else {
 219                 /*
 220                  * When emulating GICv3 on GICv3 with SRE=1 on the
 221                  * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
 222                  */
 223                 vmcrp->fiqen = 1;
 224                 vmcrp->ackctl = 0;
 225         }
 226
 227         vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
 228         vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT;
 229         vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
 230         vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
 231         vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
 232         vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
 233         vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
 234 }
 235
 236 #define INITIAL_PENDBASER_VALUE                                           \
 237         (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb)            | \
 238         GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner)      | \
 239         GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
 240
 241 void vgic_v3_enable(struct kvm_vcpu *vcpu)
 242 {
 243         struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
 244
 245         /*
 246          * By forcing VMCR to zero, the GIC will restore the binary
 247          * points to their reset values. Anything else resets to zero
 248          * anyway.
 249          */
 250         vgic_v3->vgic_vmcr = 0;
 251         vgic_v3->vgic_elrsr = ~0;
 252
 253         /*
 254          * If we are emulating a GICv3, we do it in an non-GICv2-compatible
 255          * way, so we force SRE to 1 to demonstrate this to the guest.
 256          * Also, we don't support any form of IRQ/FIQ bypass.
 257          * This goes with the spec allowing the value to be RAO/WI.
 258          */
 259         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
 260                 vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
 261                                      ICC_SRE_EL1_DFB |
 262                                      ICC_SRE_EL1_SRE);
 263                 vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
 264         } else {
 265                 vgic_v3->vgic_sre = 0;
 266         }
 267
 268         vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
 269                                            ICH_VTR_ID_BITS_MASK) >>
 270                                            ICH_VTR_ID_BITS_SHIFT;
 271         vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
 272                                             ICH_VTR_PRI_BITS_MASK) >>
 273                                             ICH_VTR_PRI_BITS_SHIFT) + 1;
 274
 275         /* Get the show on the road... */
 276         vgic_v3->vgic_hcr = ICH_HCR_EN;
 277         if (group0_trap)
 278                 vgic_v3->vgic_hcr |= ICH_HCR_TALL0;
 279         if (group1_trap)
 280                 vgic_v3->vgic_hcr |= ICH_HCR_TALL1;
 281         if (common_trap)
 282                 vgic_v3->vgic_hcr |= ICH_HCR_TC;
 283 }
 284
 285 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
 286 {
 287         struct kvm_vcpu *vcpu;
 288         int byte_offset, bit_nr;
 289         gpa_t pendbase, ptr;
 290         bool status;
 291         u8 val;
 292         int ret;
 293         unsigned long flags;
 294
 295 retry:
 296         vcpu = irq->target_vcpu;
 297         if (!vcpu)
 298                 return 0;
 299
 300         pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
 301
 302         byte_offset = irq->intid / BITS_PER_BYTE;
 303         bit_nr = irq->intid % BITS_PER_BYTE;
 304         ptr = pendbase + byte_offset;
 305
 306         ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
 307         if (ret)
 308                 return ret;
 309
 310         status = val & (1 << bit_nr);
 311
 312         spin_lock_irqsave(&irq->irq_lock, flags);
 313         if (irq->target_vcpu != vcpu) {
 314                 spin_unlock_irqrestore(&irq->irq_lock, flags);
 315                 goto retry;
 316         }
 317         irq->pending_latch = status;
 318         vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 319
 320         if (status) {
 321                 /* clear consumed data */
 322                 val &= ~(1 << bit_nr);
 323                 ret = kvm_write_guest_lock(kvm, ptr, &val, 1);
 324                 if (ret)
 325                         return ret;
 326         }
 327         return 0;
 328 }
 329
 330 /**
 331  * vgic_its_save_pending_tables - Save the pending tables into guest RAM
 332  * kvm lock and all vcpu lock must be held
 333  */
 334 int vgic_v3_save_pending_tables(struct kvm *kvm)
 335 {
 336         struct vgic_dist *dist = &kvm->arch.vgic;
 337         struct vgic_irq *irq;
 338         gpa_t last_ptr = ~(gpa_t)0;
 339         int ret;
 340         u8 val;
 341
 342         list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
 343                 int byte_offset, bit_nr;
 344                 struct kvm_vcpu *vcpu;
 345                 gpa_t pendbase, ptr;
 346                 bool stored;
 347
 348                 vcpu = irq->target_vcpu;
 349                 if (!vcpu)
 350                         continue;
 351
 352                 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
 353
 354                 byte_offset = irq->intid / BITS_PER_BYTE;
 355                 bit_nr = irq->intid % BITS_PER_BYTE;
 356                 ptr = pendbase + byte_offset;
 357
 358                 if (ptr != last_ptr) {
 359                         ret = kvm_read_guest_lock(kvm, ptr, &val, 1);
 360                         if (ret)
 361                                 return ret;
 362                         last_ptr = ptr;
 363                 }
 364
 365                 stored = val & (1U << bit_nr);
 366                 if (stored == irq->pending_latch)
 367                         continue;
 368
 369                 if (irq->pending_latch)
 370                         val |= 1 << bit_nr;
 371                 else
 372                         val &= ~(1 << bit_nr);
 373
 374                 ret = kvm_write_guest_lock(kvm, ptr, &val, 1);
 375                 if (ret)
 376                         return ret;
 377         }
 378         return 0;
 379 }
 380
 381 /*
 382  * Check for overlapping regions and for regions crossing the end of memory
 383  * for base addresses which have already been set.
 384  */
 385 bool vgic_v3_check_base(struct kvm *kvm)
 386 {
 387         struct vgic_dist *d = &kvm->arch.vgic;
 388         gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;
 389
 390         redist_size *= atomic_read(&kvm->online_vcpus);
 391
 392         if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
 393             d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
 394                 return false;
 395
 396         if (!IS_VGIC_ADDR_UNDEF(d->vgic_redist_base) &&
 397             d->vgic_redist_base + redist_size < d->vgic_redist_base)
 398                 return false;
 399
 400         /* Both base addresses must be set to check if they overlap */
 401         if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) ||
 402             IS_VGIC_ADDR_UNDEF(d->vgic_redist_base))
 403                 return true;
 404
 405         if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
 406                 return true;
 407         if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
 408                 return true;
 409
 410         return false;
 411 }
 412
 413 int vgic_v3_map_resources(struct kvm *kvm)
 414 {
 415         int ret = 0;
 416         struct vgic_dist *dist = &kvm->arch.vgic;
 417
 418         if (vgic_ready(kvm))
 419                 goto out;
 420
 421         if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
 422             IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
 423                 kvm_err("Need to set vgic distributor addresses first\n");
 424                 ret = -ENXIO;
 425                 goto out;
 426         }
 427
 428         if (!vgic_v3_check_base(kvm)) {
 429                 kvm_err("VGIC redist and dist frames overlap\n");
 430                 ret = -EINVAL;
 431                 goto out;
 432         }
 433
 434         /*
 435          * For a VGICv3 we require the userland to explicitly initialize
 436          * the VGIC before we need to use it.
 437          */
 438         if (!vgic_initialized(kvm)) {
 439                 ret = -EBUSY;
 440                 goto out;
 441         }
 442
 443         ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
 444         if (ret) {
 445                 kvm_err("Unable to register VGICv3 dist MMIO regions\n");
 446                 goto out;
 447         }
 448
 449         dist->ready = true;
 450
 451 out:
 452         return ret;
 453 }
 454
 455 DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap);
 456
 457 static int __init early_group0_trap_cfg(char *buf)
 458 {
 459         return strtobool(buf, &group0_trap);
 460 }
 461 early_param("kvm-arm.vgic_v3_group0_trap", early_group0_trap_cfg);
 462
 463 static int __init early_group1_trap_cfg(char *buf)
 464 {
 465         return strtobool(buf, &group1_trap);
 466 }
 467 early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg);
 468
 469 static int __init early_common_trap_cfg(char *buf)
 470 {
 471         return strtobool(buf, &common_trap);
 472 }
 473 early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg);
 474
 475 static int __init early_gicv4_enable(char *buf)
 476 {
 477         return strtobool(buf, &gicv4_enable);
 478 }
 479 early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable);
 480
 481 /**
 482  * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
 483  * @node:       pointer to the DT node
 484  *
 485  * Returns 0 if a GICv3 has been found, returns an error code otherwise
 486  */
 487 int vgic_v3_probe(const struct gic_kvm_info *info)
 488 {
 489         u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
 490         int ret;
 491
 492         /*
 493          * The ListRegs field is 5 bits, but there is a architectural
 494          * maximum of 16 list registers. Just ignore bit 4...
 495          */
 496         kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
 497         kvm_vgic_global_state.can_emulate_gicv2 = false;
 498         kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
 499
 500         /* GICv4 support? */
 501         if (info->has_v4) {
 502                 kvm_vgic_global_state.has_gicv4 = gicv4_enable;
 503                 kvm_info("GICv4 support %sabled\n",
 504                          gicv4_enable ? "en" : "dis");
 505         }
 506
 507         if (!info->vcpu.start) {
 508                 kvm_info("GICv3: no GICV resource entry\n");
 509                 kvm_vgic_global_state.vcpu_base = 0;
 510         } else if (!PAGE_ALIGNED(info->vcpu.start)) {
 511                 pr_warn("GICV physical address 0x%llx not page aligned\n",
 512                         (unsigned long long)info->vcpu.start);
 513                 kvm_vgic_global_state.vcpu_base = 0;
 514         } else {
 515                 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
 516                 kvm_vgic_global_state.can_emulate_gicv2 = true;
 517                 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
 518                 if (ret) {
 519                         kvm_err("Cannot register GICv2 KVM device.\n");
 520                         return ret;
 521                 }
 522                 kvm_info("vgic-v2@%llx\n", info->vcpu.start);
 523         }
 524         ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
 525         if (ret) {
 526                 kvm_err("Cannot register GICv3 KVM device.\n");
 527                 kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
 528                 return ret;
 529         }
 530
 531         if (kvm_vgic_global_state.vcpu_base == 0)
 532                 kvm_info("disabling GICv2 emulation\n");
 533
 534 #ifdef CONFIG_ARM64
 535         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_30115)) {
 536                 group0_trap = true;
 537                 group1_trap = true;
 538         }
 539 #endif
 540
 541         if (group0_trap || group1_trap || common_trap) {
 542                 kvm_info("GICv3 sysreg trapping enabled ([%s%s%s], reduced performance)\n",
 543                          group0_trap ? "G0" : "",
 544                          group1_trap ? "G1" : "",
 545                          common_trap ? "C"  : "");
 546                 static_branch_enable(&vgic_v3_cpuif_trap);
 547         }
 548
 549         kvm_vgic_global_state.vctrl_base = NULL;
 550         kvm_vgic_global_state.type = VGIC_V3;
 551         kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
 552
 553         return 0;
 554 }
 555
 556 void vgic_v3_load(struct kvm_vcpu *vcpu)
 557 {
 558         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 559
 560         /*
 561          * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen
 562          * is dependent on ICC_SRE_EL1.SRE, and we have to perform the
 563          * VMCR_EL2 save/restore in the world switch.
 564          */
 565         if (likely(cpu_if->vgic_sre))
 566                 kvm_call_hyp(__vgic_v3_write_vmcr, cpu_if->vgic_vmcr);
 567 }
 568
 569 void vgic_v3_vmcr_sync(struct kvm_vcpu *vcpu)
 570 {
 571         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 572
 573         if (likely(cpu_if->vgic_sre))
 574                 cpu_if->vgic_vmcr = kvm_call_hyp(__vgic_v3_read_vmcr);
 575 }
 576
 577 void vgic_v3_put(struct kvm_vcpu *vcpu)
 578 {
 579         vgic_v3_vmcr_sync(vcpu);
 580 }