virt/kvm/arm/vgic/vgic-v3.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program. If not, see <http://www.gnu.org/licenses/>.
  13  */
  14
  15 #include <linux/irqchip/arm-gic-v3.h>
  16 #include <linux/kvm.h>
  17 #include <linux/kvm_host.h>
  18 #include <kvm/arm_vgic.h>
  19 #include <asm/kvm_mmu.h>
  20 #include <asm/kvm_asm.h>
  21
  22 #include "vgic.h"
  23
  24 static bool group0_trap;
  25 static bool group1_trap;
  26 static bool common_trap;
  27
  28 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
  29 {
  30         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
  31
  32         cpuif->vgic_hcr |= ICH_HCR_UIE;
  33 }
  34
  35 static bool lr_signals_eoi_mi(u64 lr_val)
  36 {
  37         return !(lr_val & ICH_LR_STATE) && (lr_val & ICH_LR_EOI) &&
  38                !(lr_val & ICH_LR_HW);
  39 }
  40
  41 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
  42 {
  43         struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
  44         struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3;
  45         u32 model = vcpu->kvm->arch.vgic.vgic_model;
  46         int lr;
  47         unsigned long flags;
  48
  49         cpuif->vgic_hcr &= ~ICH_HCR_UIE;
  50
  51         for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
  52                 u64 val = cpuif->vgic_lr[lr];
  53                 u32 intid;
  54                 struct vgic_irq *irq;
  55
  56                 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
  57                         intid = val & ICH_LR_VIRTUAL_ID_MASK;
  58                 else
  59                         intid = val & GICH_LR_VIRTUALID;
  60
  61                 /* Notify fds when the guest EOI'ed a level-triggered IRQ */
  62                 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
  63                         kvm_notify_acked_irq(vcpu->kvm, 0,
  64                                              intid - VGIC_NR_PRIVATE_IRQS);
  65
  66                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
  67                 if (!irq)       /* An LPI could have been unmapped. */
  68                         continue;
  69
  70                 spin_lock_irqsave(&irq->irq_lock, flags);
  71
  72                 /* Always preserve the active bit */
  73                 irq->active = !!(val & ICH_LR_ACTIVE_BIT);
  74
  75                 /* Edge is the only case where we preserve the pending bit */
  76                 if (irq->config == VGIC_CONFIG_EDGE &&
  77                     (val & ICH_LR_PENDING_BIT)) {
  78                         irq->pending_latch = true;
  79
  80                         if (vgic_irq_is_sgi(intid) &&
  81                             model == KVM_DEV_TYPE_ARM_VGIC_V2) {
  82                                 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
  83
  84                                 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
  85                                 irq->source |= (1 << cpuid);
  86                         }
  87                 }
  88
  89                 /*
  90                  * Clear soft pending state when level irqs have been acked.
  91                  * Always regenerate the pending state.
  92                  */
  93                 if (irq->config == VGIC_CONFIG_LEVEL) {
  94                         if (!(val & ICH_LR_PENDING_BIT))
  95                                 irq->pending_latch = false;
  96                 }
  97
  98                 spin_unlock_irqrestore(&irq->irq_lock, flags);
  99                 vgic_put_irq(vcpu->kvm, irq);
 100         }
 101
 102         vgic_cpu->used_lrs = 0;
 103 }
 104
 105 /* Requires the irq to be locked already */
 106 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
 107 {
 108         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 109         u64 val = irq->intid;
 110
 111         if (irq_is_pending(irq)) {
 112                 val |= ICH_LR_PENDING_BIT;
 113
 114                 if (irq->config == VGIC_CONFIG_EDGE)
 115                         irq->pending_latch = false;
 116
 117                 if (vgic_irq_is_sgi(irq->intid) &&
 118                     model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 119                         u32 src = ffs(irq->source);
 120
 121                         BUG_ON(!src);
 122                         val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 123                         irq->source &= ~(1 << (src - 1));
 124                         if (irq->source)
 125                                 irq->pending_latch = true;
 126                 }
 127         }
 128
 129         if (irq->active)
 130                 val |= ICH_LR_ACTIVE_BIT;
 131
 132         if (irq->hw) {
 133                 val |= ICH_LR_HW;
 134                 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
 135                 /*
 136                  * Never set pending+active on a HW interrupt, as the
 137                  * pending state is kept at the physical distributor
 138                  * level.
 139                  */
 140                 if (irq->active && irq_is_pending(irq))
 141                         val &= ~ICH_LR_PENDING_BIT;
 142         } else {
 143                 if (irq->config == VGIC_CONFIG_LEVEL)
 144                         val |= ICH_LR_EOI;
 145         }
 146
 147         /*
 148          * We currently only support Group1 interrupts, which is a
 149          * known defect. This needs to be addressed at some point.
 150          */
 151         if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
 152                 val |= ICH_LR_GROUP;
 153
 154         val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
 155
 156         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
 157 }
 158
 159 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
 160 {
 161         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
 162 }
 163
 164 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 165 {
 166         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 167         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 168         u32 vmcr;
 169
 170         if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 171                 vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) &
 172                         ICH_VMCR_ACK_CTL_MASK;
 173                 vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) &
 174                         ICH_VMCR_FIQ_EN_MASK;
 175         } else {
 176                 /*
 177                  * When emulating GICv3 on GICv3 with SRE=1 on the
 178                  * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
 179                  */
 180                 vmcr = ICH_VMCR_FIQ_EN_MASK;
 181         }
 182
 183         vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
 184         vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
 185         vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
 186         vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
 187         vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
 188         vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
 189         vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
 190
 191         cpu_if->vgic_vmcr = vmcr;
 192 }
 193
 194 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 195 {
 196         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 197         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 198         u32 vmcr;
 199
 200         vmcr = cpu_if->vgic_vmcr;
 201
 202         if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 203                 vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >>
 204                         ICH_VMCR_ACK_CTL_SHIFT;
 205                 vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >>
 206                         ICH_VMCR_FIQ_EN_SHIFT;
 207         } else {
 208                 /*
 209                  * When emulating GICv3 on GICv3 with SRE=1 on the
 210                  * VFIQEn bit is RES1 and the VAckCtl bit is RES0.
 211                  */
 212                 vmcrp->fiqen = 1;
 213                 vmcrp->ackctl = 0;
 214         }
 215
 216         vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
 217         vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT;
 218         vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
 219         vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
 220         vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
 221         vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
 222         vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
 223 }
 224
 225 #define INITIAL_PENDBASER_VALUE                                           \
 226         (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb)            | \
 227         GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner)      | \
 228         GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
 229
 230 void vgic_v3_enable(struct kvm_vcpu *vcpu)
 231 {
 232         struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
 233
 234         /*
 235          * By forcing VMCR to zero, the GIC will restore the binary
 236          * points to their reset values. Anything else resets to zero
 237          * anyway.
 238          */
 239         vgic_v3->vgic_vmcr = 0;
 240         vgic_v3->vgic_elrsr = ~0;
 241
 242         /*
 243          * If we are emulating a GICv3, we do it in an non-GICv2-compatible
 244          * way, so we force SRE to 1 to demonstrate this to the guest.
 245          * Also, we don't support any form of IRQ/FIQ bypass.
 246          * This goes with the spec allowing the value to be RAO/WI.
 247          */
 248         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
 249                 vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB |
 250                                      ICC_SRE_EL1_DFB |
 251                                      ICC_SRE_EL1_SRE);
 252                 vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
 253         } else {
 254                 vgic_v3->vgic_sre = 0;
 255         }
 256
 257         vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
 258                                            ICH_VTR_ID_BITS_MASK) >>
 259                                            ICH_VTR_ID_BITS_SHIFT;
 260         vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
 261                                             ICH_VTR_PRI_BITS_MASK) >>
 262                                             ICH_VTR_PRI_BITS_SHIFT) + 1;
 263
 264         /* Get the show on the road... */
 265         vgic_v3->vgic_hcr = ICH_HCR_EN;
 266         if (group0_trap)
 267                 vgic_v3->vgic_hcr |= ICH_HCR_TALL0;
 268         if (group1_trap)
 269                 vgic_v3->vgic_hcr |= ICH_HCR_TALL1;
 270         if (common_trap)
 271                 vgic_v3->vgic_hcr |= ICH_HCR_TC;
 272 }
 273
 274 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)
 275 {
 276         struct kvm_vcpu *vcpu;
 277         int byte_offset, bit_nr;
 278         gpa_t pendbase, ptr;
 279         bool status;
 280         u8 val;
 281         int ret;
 282         unsigned long flags;
 283
 284 retry:
 285         vcpu = irq->target_vcpu;
 286         if (!vcpu)
 287                 return 0;
 288
 289         pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
 290
 291         byte_offset = irq->intid / BITS_PER_BYTE;
 292         bit_nr = irq->intid % BITS_PER_BYTE;
 293         ptr = pendbase + byte_offset;
 294
 295         ret = kvm_read_guest(kvm, ptr, &val, 1);
 296         if (ret)
 297                 return ret;
 298
 299         status = val & (1 << bit_nr);
 300
 301         spin_lock_irqsave(&irq->irq_lock, flags);
 302         if (irq->target_vcpu != vcpu) {
 303                 spin_unlock_irqrestore(&irq->irq_lock, flags);
 304                 goto retry;
 305         }
 306         irq->pending_latch = status;
 307         vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 308
 309         if (status) {
 310                 /* clear consumed data */
 311                 val &= ~(1 << bit_nr);
 312                 ret = kvm_write_guest(kvm, ptr, &val, 1);
 313                 if (ret)
 314                         return ret;
 315         }
 316         return 0;
 317 }
 318
 319 /**
 320  * vgic_its_save_pending_tables - Save the pending tables into guest RAM
 321  * kvm lock and all vcpu lock must be held
 322  */
 323 int vgic_v3_save_pending_tables(struct kvm *kvm)
 324 {
 325         struct vgic_dist *dist = &kvm->arch.vgic;
 326         int last_byte_offset = -1;
 327         struct vgic_irq *irq;
 328         int ret;
 329
 330         list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
 331                 int byte_offset, bit_nr;
 332                 struct kvm_vcpu *vcpu;
 333                 gpa_t pendbase, ptr;
 334                 bool stored;
 335                 u8 val;
 336
 337                 vcpu = irq->target_vcpu;
 338                 if (!vcpu)
 339                         continue;
 340
 341                 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser);
 342
 343                 byte_offset = irq->intid / BITS_PER_BYTE;
 344                 bit_nr = irq->intid % BITS_PER_BYTE;
 345                 ptr = pendbase + byte_offset;
 346
 347                 if (byte_offset != last_byte_offset) {
 348                         ret = kvm_read_guest(kvm, ptr, &val, 1);
 349                         if (ret)
 350                                 return ret;
 351                         last_byte_offset = byte_offset;
 352                 }
 353
 354                 stored = val & (1U << bit_nr);
 355                 if (stored == irq->pending_latch)
 356                         continue;
 357
 358                 if (irq->pending_latch)
 359                         val |= 1 << bit_nr;
 360                 else
 361                         val &= ~(1 << bit_nr);
 362
 363                 ret = kvm_write_guest(kvm, ptr, &val, 1);
 364                 if (ret)
 365                         return ret;
 366         }
 367         return 0;
 368 }
 369
 370 /*
 371  * Check for overlapping regions and for regions crossing the end of memory
 372  * for base addresses which have already been set.
 373  */
 374 bool vgic_v3_check_base(struct kvm *kvm)
 375 {
 376         struct vgic_dist *d = &kvm->arch.vgic;
 377         gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;
 378
 379         redist_size *= atomic_read(&kvm->online_vcpus);
 380
 381         if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) &&
 382             d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
 383                 return false;
 384
 385         if (!IS_VGIC_ADDR_UNDEF(d->vgic_redist_base) &&
 386             d->vgic_redist_base + redist_size < d->vgic_redist_base)
 387                 return false;
 388
 389         /* Both base addresses must be set to check if they overlap */
 390         if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) ||
 391             IS_VGIC_ADDR_UNDEF(d->vgic_redist_base))
 392                 return true;
 393
 394         if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
 395                 return true;
 396         if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
 397                 return true;
 398
 399         return false;
 400 }
 401
 402 int vgic_v3_map_resources(struct kvm *kvm)
 403 {
 404         int ret = 0;
 405         struct vgic_dist *dist = &kvm->arch.vgic;
 406
 407         if (vgic_ready(kvm))
 408                 goto out;
 409
 410         if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
 411             IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
 412                 kvm_err("Need to set vgic distributor addresses first\n");
 413                 ret = -ENXIO;
 414                 goto out;
 415         }
 416
 417         if (!vgic_v3_check_base(kvm)) {
 418                 kvm_err("VGIC redist and dist frames overlap\n");
 419                 ret = -EINVAL;
 420                 goto out;
 421         }
 422
 423         /*
 424          * For a VGICv3 we require the userland to explicitly initialize
 425          * the VGIC before we need to use it.
 426          */
 427         if (!vgic_initialized(kvm)) {
 428                 ret = -EBUSY;
 429                 goto out;
 430         }
 431
 432         ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
 433         if (ret) {
 434                 kvm_err("Unable to register VGICv3 dist MMIO regions\n");
 435                 goto out;
 436         }
 437
 438         dist->ready = true;
 439
 440 out:
 441         return ret;
 442 }
 443
 444 DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap);
 445
 446 static int __init early_group0_trap_cfg(char *buf)
 447 {
 448         return strtobool(buf, &group0_trap);
 449 }
 450 early_param("kvm-arm.vgic_v3_group0_trap", early_group0_trap_cfg);
 451
 452 static int __init early_group1_trap_cfg(char *buf)
 453 {
 454         return strtobool(buf, &group1_trap);
 455 }
 456 early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg);
 457
 458 static int __init early_common_trap_cfg(char *buf)
 459 {
 460         return strtobool(buf, &common_trap);
 461 }
 462 early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg);
 463
 464 /**
 465  * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
 466  * @node:       pointer to the DT node
 467  *
 468  * Returns 0 if a GICv3 has been found, returns an error code otherwise
 469  */
 470 int vgic_v3_probe(const struct gic_kvm_info *info)
 471 {
 472         u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
 473         int ret;
 474
 475         /*
 476          * The ListRegs field is 5 bits, but there is a architectural
 477          * maximum of 16 list registers. Just ignore bit 4...
 478          */
 479         kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
 480         kvm_vgic_global_state.can_emulate_gicv2 = false;
 481         kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
 482
 483         if (!info->vcpu.start) {
 484                 kvm_info("GICv3: no GICV resource entry\n");
 485                 kvm_vgic_global_state.vcpu_base = 0;
 486         } else if (!PAGE_ALIGNED(info->vcpu.start)) {
 487                 pr_warn("GICV physical address 0x%llx not page aligned\n",
 488                         (unsigned long long)info->vcpu.start);
 489                 kvm_vgic_global_state.vcpu_base = 0;
 490         } else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
 491                 pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
 492                         (unsigned long long)resource_size(&info->vcpu),
 493                         PAGE_SIZE);
 494                 kvm_vgic_global_state.vcpu_base = 0;
 495         } else {
 496                 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
 497                 kvm_vgic_global_state.can_emulate_gicv2 = true;
 498                 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
 499                 if (ret) {
 500                         kvm_err("Cannot register GICv2 KVM device.\n");
 501                         return ret;
 502                 }
 503                 kvm_info("vgic-v2@%llx\n", info->vcpu.start);
 504         }
 505         ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
 506         if (ret) {
 507                 kvm_err("Cannot register GICv3 KVM device.\n");
 508                 kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
 509                 return ret;
 510         }
 511
 512         if (kvm_vgic_global_state.vcpu_base == 0)
 513                 kvm_info("disabling GICv2 emulation\n");
 514
 515 #ifdef CONFIG_ARM64
 516         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_30115)) {
 517                 group0_trap = true;
 518                 group1_trap = true;
 519         }
 520 #endif
 521
 522         if (group0_trap || group1_trap || common_trap) {
 523                 kvm_info("GICv3 sysreg trapping enabled ([%s%s%s], reduced performance)\n",
 524                          group0_trap ? "G0" : "",
 525                          group1_trap ? "G1" : "",
 526                          common_trap ? "C"  : "");
 527                 static_branch_enable(&vgic_v3_cpuif_trap);
 528         }
 529
 530         kvm_vgic_global_state.vctrl_base = NULL;
 531         kvm_vgic_global_state.type = VGIC_V3;
 532         kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
 533
 534         return 0;
 535 }
 536
 537 void vgic_v3_load(struct kvm_vcpu *vcpu)
 538 {
 539         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 540
 541         /*
 542          * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen
 543          * is dependent on ICC_SRE_EL1.SRE, and we have to perform the
 544          * VMCR_EL2 save/restore in the world switch.
 545          */
 546         if (likely(cpu_if->vgic_sre))
 547                 kvm_call_hyp(__vgic_v3_write_vmcr, cpu_if->vgic_vmcr);
 548 }
 549
 550 void vgic_v3_put(struct kvm_vcpu *vcpu)
 551 {
 552         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 553
 554         if (likely(cpu_if->vgic_sre))
 555                 cpu_if->vgic_vmcr = kvm_call_hyp(__vgic_v3_read_vmcr);
 556 }