virt/kvm/arm/vgic/vgic-v3.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program. If not, see <http://www.gnu.org/licenses/>.
  13  */
  14
  15 #include <linux/irqchip/arm-gic-v3.h>
  16 #include <linux/kvm.h>
  17 #include <linux/kvm_host.h>
  18 #include <kvm/arm_vgic.h>
  19 #include <asm/kvm_mmu.h>
  20 #include <asm/kvm_asm.h>
  21
  22 #include "vgic.h"
  23
  24 void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu)
  25 {
  26         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
  27         u32 model = vcpu->kvm->arch.vgic.vgic_model;
  28
  29         if (cpuif->vgic_misr & ICH_MISR_EOI) {
  30                 unsigned long eisr_bmap = cpuif->vgic_eisr;
  31                 int lr;
  32
  33                 for_each_set_bit(lr, &eisr_bmap, kvm_vgic_global_state.nr_lr) {
  34                         u32 intid;
  35                         u64 val = cpuif->vgic_lr[lr];
  36
  37                         if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
  38                                 intid = val & ICH_LR_VIRTUAL_ID_MASK;
  39                         else
  40                                 intid = val & GICH_LR_VIRTUALID;
  41
  42                         WARN_ON(cpuif->vgic_lr[lr] & ICH_LR_STATE);
  43
  44                         /* Only SPIs require notification */
  45                         if (vgic_valid_spi(vcpu->kvm, intid))
  46                                 kvm_notify_acked_irq(vcpu->kvm, 0,
  47                                                      intid - VGIC_NR_PRIVATE_IRQS);
  48                 }
  49
  50                 /*
  51                  * In the next iterations of the vcpu loop, if we sync
  52                  * the vgic state after flushing it, but before
  53                  * entering the guest (this happens for pending
  54                  * signals and vmid rollovers), then make sure we
  55                  * don't pick up any old maintenance interrupts here.
  56                  */
  57                 cpuif->vgic_eisr = 0;
  58         }
  59
  60         cpuif->vgic_hcr &= ~ICH_HCR_UIE;
  61 }
  62
  63 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
  64 {
  65         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
  66
  67         cpuif->vgic_hcr |= ICH_HCR_UIE;
  68 }
  69
  70 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
  71 {
  72         struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
  73         u32 model = vcpu->kvm->arch.vgic.vgic_model;
  74         int lr;
  75
  76         for (lr = 0; lr < vcpu->arch.vgic_cpu.used_lrs; lr++) {
  77                 u64 val = cpuif->vgic_lr[lr];
  78                 u32 intid;
  79                 struct vgic_irq *irq;
  80
  81                 if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
  82                         intid = val & ICH_LR_VIRTUAL_ID_MASK;
  83                 else
  84                         intid = val & GICH_LR_VIRTUALID;
  85                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
  86                 if (!irq)       /* An LPI could have been unmapped. */
  87                         continue;
  88
  89                 spin_lock(&irq->irq_lock);
  90
  91                 /* Always preserve the active bit */
  92                 irq->active = !!(val & ICH_LR_ACTIVE_BIT);
  93
  94                 /* Edge is the only case where we preserve the pending bit */
  95                 if (irq->config == VGIC_CONFIG_EDGE &&
  96                     (val & ICH_LR_PENDING_BIT)) {
  97                         irq->pending_latch = true;
  98
  99                         if (vgic_irq_is_sgi(intid) &&
 100                             model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 101                                 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
 102
 103                                 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
 104                                 irq->source |= (1 << cpuid);
 105                         }
 106                 }
 107
 108                 /*
 109                  * Clear soft pending state when level irqs have been acked.
 110                  * Always regenerate the pending state.
 111                  */
 112                 if (irq->config == VGIC_CONFIG_LEVEL) {
 113                         if (!(val & ICH_LR_PENDING_BIT))
 114                                 irq->pending_latch = false;
 115                 }
 116
 117                 spin_unlock(&irq->irq_lock);
 118                 vgic_put_irq(vcpu->kvm, irq);
 119         }
 120 }
 121
 122 /* Requires the irq to be locked already */
 123 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
 124 {
 125         u32 model = vcpu->kvm->arch.vgic.vgic_model;
 126         u64 val = irq->intid;
 127
 128         if (irq_is_pending(irq)) {
 129                 val |= ICH_LR_PENDING_BIT;
 130
 131                 if (irq->config == VGIC_CONFIG_EDGE)
 132                         irq->pending_latch = false;
 133
 134                 if (vgic_irq_is_sgi(irq->intid) &&
 135                     model == KVM_DEV_TYPE_ARM_VGIC_V2) {
 136                         u32 src = ffs(irq->source);
 137
 138                         BUG_ON(!src);
 139                         val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
 140                         irq->source &= ~(1 << (src - 1));
 141                         if (irq->source)
 142                                 irq->pending_latch = true;
 143                 }
 144         }
 145
 146         if (irq->active)
 147                 val |= ICH_LR_ACTIVE_BIT;
 148
 149         if (irq->hw) {
 150                 val |= ICH_LR_HW;
 151                 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT;
 152         } else {
 153                 if (irq->config == VGIC_CONFIG_LEVEL)
 154                         val |= ICH_LR_EOI;
 155         }
 156
 157         /*
 158          * We currently only support Group1 interrupts, which is a
 159          * known defect. This needs to be addressed at some point.
 160          */
 161         if (model == KVM_DEV_TYPE_ARM_VGIC_V3)
 162                 val |= ICH_LR_GROUP;
 163
 164         val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT;
 165
 166         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val;
 167 }
 168
 169 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
 170 {
 171         vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0;
 172 }
 173
 174 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 175 {
 176         u32 vmcr;
 177
 178         /*
 179          * Ignore the FIQen bit, because GIC emulation always implies
 180          * SRE=1 which means the vFIQEn bit is also RES1.
 181          */
 182         vmcr = ((vmcrp->ctlr >> ICC_CTLR_EL1_EOImode_SHIFT) <<
 183                  ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
 184         vmcr |= (vmcrp->ctlr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
 185         vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
 186         vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
 187         vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
 188         vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
 189         vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK;
 190
 191         vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr = vmcr;
 192 }
 193
 194 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
 195 {
 196         u32 vmcr = vcpu->arch.vgic_cpu.vgic_v3.vgic_vmcr;
 197
 198         /*
 199          * Ignore the FIQen bit, because GIC emulation always implies
 200          * SRE=1 which means the vFIQEn bit is also RES1.
 201          */
 202         vmcrp->ctlr = ((vmcr >> ICH_VMCR_EOIM_SHIFT) <<
 203                         ICC_CTLR_EL1_EOImode_SHIFT) & ICC_CTLR_EL1_EOImode_MASK;
 204         vmcrp->ctlr |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
 205         vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
 206         vmcrp->bpr  = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
 207         vmcrp->pmr  = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
 208         vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
 209         vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT;
 210 }
 211
 212 #define INITIAL_PENDBASER_VALUE                                           \
 213         (GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb)            | \
 214         GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, SameAsInner)      | \
 215         GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable))
 216
 217 void vgic_v3_enable(struct kvm_vcpu *vcpu)
 218 {
 219         struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3;
 220
 221         /*
 222          * By forcing VMCR to zero, the GIC will restore the binary
 223          * points to their reset values. Anything else resets to zero
 224          * anyway.
 225          */
 226         vgic_v3->vgic_vmcr = 0;
 227         vgic_v3->vgic_elrsr = ~0;
 228
 229         /*
 230          * If we are emulating a GICv3, we do it in an non-GICv2-compatible
 231          * way, so we force SRE to 1 to demonstrate this to the guest.
 232          * This goes with the spec allowing the value to be RAO/WI.
 233          */
 234         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
 235                 vgic_v3->vgic_sre = ICC_SRE_EL1_SRE;
 236                 vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE;
 237         } else {
 238                 vgic_v3->vgic_sre = 0;
 239         }
 240
 241         vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
 242                                            ICH_VTR_ID_BITS_MASK) >>
 243                                            ICH_VTR_ID_BITS_SHIFT;
 244         vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
 245                                             ICH_VTR_PRI_BITS_MASK) >>
 246                                             ICH_VTR_PRI_BITS_SHIFT) + 1;
 247
 248         /* Get the show on the road... */
 249         vgic_v3->vgic_hcr = ICH_HCR_EN;
 250 }
 251
 252 /* check for overlapping regions and for regions crossing the end of memory */
 253 static bool vgic_v3_check_base(struct kvm *kvm)
 254 {
 255         struct vgic_dist *d = &kvm->arch.vgic;
 256         gpa_t redist_size = KVM_VGIC_V3_REDIST_SIZE;
 257
 258         redist_size *= atomic_read(&kvm->online_vcpus);
 259
 260         if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base)
 261                 return false;
 262         if (d->vgic_redist_base + redist_size < d->vgic_redist_base)
 263                 return false;
 264
 265         if (d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE <= d->vgic_redist_base)
 266                 return true;
 267         if (d->vgic_redist_base + redist_size <= d->vgic_dist_base)
 268                 return true;
 269
 270         return false;
 271 }
 272
 273 int vgic_v3_map_resources(struct kvm *kvm)
 274 {
 275         int ret = 0;
 276         struct vgic_dist *dist = &kvm->arch.vgic;
 277
 278         if (vgic_ready(kvm))
 279                 goto out;
 280
 281         if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
 282             IS_VGIC_ADDR_UNDEF(dist->vgic_redist_base)) {
 283                 kvm_err("Need to set vgic distributor addresses first\n");
 284                 ret = -ENXIO;
 285                 goto out;
 286         }
 287
 288         if (!vgic_v3_check_base(kvm)) {
 289                 kvm_err("VGIC redist and dist frames overlap\n");
 290                 ret = -EINVAL;
 291                 goto out;
 292         }
 293
 294         /*
 295          * For a VGICv3 we require the userland to explicitly initialize
 296          * the VGIC before we need to use it.
 297          */
 298         if (!vgic_initialized(kvm)) {
 299                 ret = -EBUSY;
 300                 goto out;
 301         }
 302
 303         ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
 304         if (ret) {
 305                 kvm_err("Unable to register VGICv3 dist MMIO regions\n");
 306                 goto out;
 307         }
 308
 309         ret = vgic_register_redist_iodevs(kvm, dist->vgic_redist_base);
 310         if (ret) {
 311                 kvm_err("Unable to register VGICv3 redist MMIO regions\n");
 312                 goto out;
 313         }
 314
 315         if (vgic_has_its(kvm)) {
 316                 ret = vgic_register_its_iodevs(kvm);
 317                 if (ret) {
 318                         kvm_err("Unable to register VGIC ITS MMIO regions\n");
 319                         goto out;
 320                 }
 321         }
 322
 323         dist->ready = true;
 324
 325 out:
 326         return ret;
 327 }
 328
 329 /**
 330  * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
 331  * @node:       pointer to the DT node
 332  *
 333  * Returns 0 if a GICv3 has been found, returns an error code otherwise
 334  */
 335 int vgic_v3_probe(const struct gic_kvm_info *info)
 336 {
 337         u32 ich_vtr_el2 = kvm_call_hyp(__vgic_v3_get_ich_vtr_el2);
 338         int ret;
 339
 340         /*
 341          * The ListRegs field is 5 bits, but there is a architectural
 342          * maximum of 16 list registers. Just ignore bit 4...
 343          */
 344         kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
 345         kvm_vgic_global_state.can_emulate_gicv2 = false;
 346         kvm_vgic_global_state.ich_vtr_el2 = ich_vtr_el2;
 347
 348         if (!info->vcpu.start) {
 349                 kvm_info("GICv3: no GICV resource entry\n");
 350                 kvm_vgic_global_state.vcpu_base = 0;
 351         } else if (!PAGE_ALIGNED(info->vcpu.start)) {
 352                 pr_warn("GICV physical address 0x%llx not page aligned\n",
 353                         (unsigned long long)info->vcpu.start);
 354                 kvm_vgic_global_state.vcpu_base = 0;
 355         } else if (!PAGE_ALIGNED(resource_size(&info->vcpu))) {
 356                 pr_warn("GICV size 0x%llx not a multiple of page size 0x%lx\n",
 357                         (unsigned long long)resource_size(&info->vcpu),
 358                         PAGE_SIZE);
 359                 kvm_vgic_global_state.vcpu_base = 0;
 360         } else {
 361                 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
 362                 kvm_vgic_global_state.can_emulate_gicv2 = true;
 363                 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
 364                 if (ret) {
 365                         kvm_err("Cannot register GICv2 KVM device.\n");
 366                         return ret;
 367                 }
 368                 kvm_info("vgic-v2@%llx\n", info->vcpu.start);
 369         }
 370         ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
 371         if (ret) {
 372                 kvm_err("Cannot register GICv3 KVM device.\n");
 373                 kvm_unregister_device_ops(KVM_DEV_TYPE_ARM_VGIC_V2);
 374                 return ret;
 375         }
 376
 377         if (kvm_vgic_global_state.vcpu_base == 0)
 378                 kvm_info("disabling GICv2 emulation\n");
 379
 380         kvm_vgic_global_state.vctrl_base = NULL;
 381         kvm_vgic_global_state.type = VGIC_V3;
 382         kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
 383
 384         return 0;
 385 }