virt/kvm/arm/vgic/vgic.h

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __KVM_ARM_VGIC_NEW_H__
  17 #define __KVM_ARM_VGIC_NEW_H__
  18
  19 #include <linux/irqchip/arm-gic-common.h>
  20
  21 #define PRODUCT_ID_KVM          0x4b    /* ASCII code K */
  22 #define IMPLEMENTER_ARM         0x43b
  23
  24 #define VGIC_ADDR_UNDEF         (-1)
  25 #define IS_VGIC_ADDR_UNDEF(_x)  ((_x) == VGIC_ADDR_UNDEF)
  26
  27 #define INTERRUPT_ID_BITS_SPIS  10
  28 #define INTERRUPT_ID_BITS_ITS   16
  29 #define VGIC_PRI_BITS           5
  30
  31 #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
  32
  33 #define VGIC_AFFINITY_0_SHIFT 0
  34 #define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
  35 #define VGIC_AFFINITY_1_SHIFT 8
  36 #define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
  37 #define VGIC_AFFINITY_2_SHIFT 16
  38 #define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
  39 #define VGIC_AFFINITY_3_SHIFT 24
  40 #define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)
  41
  42 #define VGIC_AFFINITY_LEVEL(reg, level) \
  43         ((((reg) & VGIC_AFFINITY_## level ##_MASK) \
  44         >> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
  45
  46 /*
  47  * The Userspace encodes the affinity differently from the MPIDR,
  48  * Below macro converts vgic userspace format to MPIDR reg format.
  49  */
  50 #define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \
  51                             VGIC_AFFINITY_LEVEL(val, 1) | \
  52                             VGIC_AFFINITY_LEVEL(val, 2) | \
  53                             VGIC_AFFINITY_LEVEL(val, 3))
  54
  55 static inline bool irq_is_pending(struct vgic_irq *irq)
  56 {
  57         if (irq->config == VGIC_CONFIG_EDGE)
  58                 return irq->pending_latch;
  59         else
  60                 return irq->pending_latch || irq->line_level;
  61 }
  62
  63 struct vgic_vmcr {
  64         u32     ctlr;
  65         u32     abpr;
  66         u32     bpr;
  67         u32     pmr;
  68         /* Below member variable are valid only for GICv3 */
  69         u32     grpen0;
  70         u32     grpen1;
  71 };
  72
  73 struct vgic_reg_attr {
  74         struct kvm_vcpu *vcpu;
  75         gpa_t addr;
  76 };
  77
  78 int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
  79                        struct vgic_reg_attr *reg_attr);
  80 int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
  81                        struct vgic_reg_attr *reg_attr);
  82 const struct vgic_register_region *
  83 vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
  84                      gpa_t addr, int len);
  85 struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
  86                               u32 intid);
  87 void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq);
  88 bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq);
  89 void vgic_kick_vcpus(struct kvm *kvm);
  90
  91 int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr,
  92                       phys_addr_t addr, phys_addr_t alignment);
  93
  94 void vgic_v2_process_maintenance(struct kvm_vcpu *vcpu);
  95 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
  96 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
  97 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
  98 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
  99 int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
 100 int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 101                          int offset, u32 *val);
 102 int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 103                           int offset, u32 *val);
 104 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 105 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 106 void vgic_v2_enable(struct kvm_vcpu *vcpu);
 107 int vgic_v2_probe(const struct gic_kvm_info *info);
 108 int vgic_v2_map_resources(struct kvm *kvm);
 109 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
 110                              enum vgic_type);
 111
 112 static inline void vgic_get_irq_kref(struct vgic_irq *irq)
 113 {
 114         if (irq->intid < VGIC_MIN_LPI)
 115                 return;
 116
 117         kref_get(&irq->refcount);
 118 }
 119
 120 void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu);
 121 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
 122 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
 123 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
 124 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
 125 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 126 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 127 void vgic_v3_enable(struct kvm_vcpu *vcpu);
 128 int vgic_v3_probe(const struct gic_kvm_info *info);
 129 int vgic_v3_map_resources(struct kvm *kvm);
 130 int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t dist_base_address);
 131
 132 int vgic_register_its_iodevs(struct kvm *kvm);
 133 bool vgic_has_its(struct kvm *kvm);
 134 int kvm_vgic_register_its_device(void);
 135 void vgic_enable_lpis(struct kvm_vcpu *vcpu);
 136 int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
 137 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
 138 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 139                          int offset, u32 *val);
 140 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 141                          int offset, u32 *val);
 142 int kvm_register_vgic_device(unsigned long type);
 143 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 144 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 145 int vgic_lazy_init(struct kvm *kvm);
 146 int vgic_init(struct kvm *kvm);
 147
 148 int vgic_debug_init(struct kvm *kvm);
 149 int vgic_debug_destroy(struct kvm *kvm);
 150
 151 #endif