2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/cpu.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_host.h>
22 #include <linux/interrupt.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/uaccess.h>
29 #include <linux/irqchip/arm-gic.h>
31 #include <asm/kvm_emulate.h>
32 #include <asm/kvm_arm.h>
33 #include <asm/kvm_mmu.h>
36 * How the whole thing works (courtesy of Christoffer Dall):
38 * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
39 * something is pending
40 * - VGIC pending interrupts are stored on the vgic.irq_state vgic
41 * bitmap (this bitmap is updated by both user land ioctls and guest
42 * mmio ops, and other in-kernel peripherals such as the
43 * arch. timers) and indicate the 'wire' state.
44 * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
46 * - To calculate the oracle, we need info for each cpu from
47 * compute_pending_for_cpu, which considers:
48 * - PPI: dist->irq_state & dist->irq_enable
49 * - SPI: dist->irq_state & dist->irq_enable & dist->irq_spi_target
50 * - irq_spi_target is a 'formatted' version of the GICD_ICFGR
51 * registers, stored on each vcpu. We only keep one bit of
52 * information per interrupt, making sure that only one vcpu can
53 * accept the interrupt.
54 * - The same is true when injecting an interrupt, except that we only
55 * consider a single interrupt at a time. The irq_spi_cpu array
56 * contains the target CPU for each SPI.
58 * The handling of level interrupts adds some extra complexity. We
59 * need to track when the interrupt has been EOIed, so we can sample
60 * the 'line' again. This is achieved as such:
62 * - When a level interrupt is moved onto a vcpu, the corresponding
63 * bit in irq_active is set. As long as this bit is set, the line
64 * will be ignored for further interrupts. The interrupt is injected
65 * into the vcpu with the GICH_LR_EOI bit set (generate a
66 * maintenance interrupt on EOI).
67 * - When the interrupt is EOIed, the maintenance interrupt fires,
68 * and clears the corresponding bit in irq_active. This allow the
69 * interrupt line to be sampled again.
72 #define VGIC_ADDR_UNDEF (-1)
73 #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
75 #define PRODUCT_ID_KVM 0x4b /* ASCII code K */
76 #define IMPLEMENTER_ARM 0x43b
77 #define GICC_ARCH_VERSION_V2 0x2
79 /* Physical address of vgic virtual cpu interface */
80 static phys_addr_t vgic_vcpu_base
;
82 /* Virtual control interface base address */
83 static void __iomem
*vgic_vctrl_base
;
85 static struct device_node
*vgic_node
;
87 #define ACCESS_READ_VALUE (1 << 0)
88 #define ACCESS_READ_RAZ (0 << 0)
89 #define ACCESS_READ_MASK(x) ((x) & (1 << 0))
90 #define ACCESS_WRITE_IGNORED (0 << 1)
91 #define ACCESS_WRITE_SETBIT (1 << 1)
92 #define ACCESS_WRITE_CLEARBIT (2 << 1)
93 #define ACCESS_WRITE_VALUE (3 << 1)
94 #define ACCESS_WRITE_MASK(x) ((x) & (3 << 1))
96 static void vgic_retire_disabled_irqs(struct kvm_vcpu
*vcpu
);
97 static void vgic_retire_lr(int lr_nr
, int irq
, struct kvm_vcpu
*vcpu
);
98 static void vgic_update_state(struct kvm
*kvm
);
99 static void vgic_kick_vcpus(struct kvm
*kvm
);
100 static void vgic_dispatch_sgi(struct kvm_vcpu
*vcpu
, u32 reg
);
101 static struct vgic_lr
vgic_get_lr(const struct kvm_vcpu
*vcpu
, int lr
);
102 static void vgic_set_lr(struct kvm_vcpu
*vcpu
, int lr
, struct vgic_lr lr_desc
);
103 static u32 vgic_nr_lr
;
105 static unsigned int vgic_maint_irq
;
107 static u32
*vgic_bitmap_get_reg(struct vgic_bitmap
*x
,
108 int cpuid
, u32 offset
)
112 return x
->percpu
[cpuid
].reg
;
114 return x
->shared
.reg
+ offset
- 1;
117 static int vgic_bitmap_get_irq_val(struct vgic_bitmap
*x
,
120 if (irq
< VGIC_NR_PRIVATE_IRQS
)
121 return test_bit(irq
, x
->percpu
[cpuid
].reg_ul
);
123 return test_bit(irq
- VGIC_NR_PRIVATE_IRQS
, x
->shared
.reg_ul
);
126 static void vgic_bitmap_set_irq_val(struct vgic_bitmap
*x
, int cpuid
,
131 if (irq
< VGIC_NR_PRIVATE_IRQS
) {
132 reg
= x
->percpu
[cpuid
].reg_ul
;
134 reg
= x
->shared
.reg_ul
;
135 irq
-= VGIC_NR_PRIVATE_IRQS
;
144 static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap
*x
, int cpuid
)
146 if (unlikely(cpuid
>= VGIC_MAX_CPUS
))
148 return x
->percpu
[cpuid
].reg_ul
;
151 static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap
*x
)
153 return x
->shared
.reg_ul
;
156 static u32
*vgic_bytemap_get_reg(struct vgic_bytemap
*x
, int cpuid
, u32 offset
)
159 BUG_ON(offset
> (VGIC_NR_IRQS
/ 4));
161 return x
->percpu
[cpuid
] + offset
;
163 return x
->shared
+ offset
- 8;
166 #define VGIC_CFG_LEVEL 0
167 #define VGIC_CFG_EDGE 1
169 static bool vgic_irq_is_edge(struct kvm_vcpu
*vcpu
, int irq
)
171 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
174 irq_val
= vgic_bitmap_get_irq_val(&dist
->irq_cfg
, vcpu
->vcpu_id
, irq
);
175 return irq_val
== VGIC_CFG_EDGE
;
178 static int vgic_irq_is_enabled(struct kvm_vcpu
*vcpu
, int irq
)
180 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
182 return vgic_bitmap_get_irq_val(&dist
->irq_enabled
, vcpu
->vcpu_id
, irq
);
185 static int vgic_irq_is_active(struct kvm_vcpu
*vcpu
, int irq
)
187 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
189 return vgic_bitmap_get_irq_val(&dist
->irq_active
, vcpu
->vcpu_id
, irq
);
192 static void vgic_irq_set_active(struct kvm_vcpu
*vcpu
, int irq
)
194 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
196 vgic_bitmap_set_irq_val(&dist
->irq_active
, vcpu
->vcpu_id
, irq
, 1);
199 static void vgic_irq_clear_active(struct kvm_vcpu
*vcpu
, int irq
)
201 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
203 vgic_bitmap_set_irq_val(&dist
->irq_active
, vcpu
->vcpu_id
, irq
, 0);
206 static int vgic_dist_irq_is_pending(struct kvm_vcpu
*vcpu
, int irq
)
208 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
210 return vgic_bitmap_get_irq_val(&dist
->irq_state
, vcpu
->vcpu_id
, irq
);
213 static void vgic_dist_irq_set(struct kvm_vcpu
*vcpu
, int irq
)
215 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
217 vgic_bitmap_set_irq_val(&dist
->irq_state
, vcpu
->vcpu_id
, irq
, 1);
220 static void vgic_dist_irq_clear(struct kvm_vcpu
*vcpu
, int irq
)
222 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
224 vgic_bitmap_set_irq_val(&dist
->irq_state
, vcpu
->vcpu_id
, irq
, 0);
227 static void vgic_cpu_irq_set(struct kvm_vcpu
*vcpu
, int irq
)
229 if (irq
< VGIC_NR_PRIVATE_IRQS
)
230 set_bit(irq
, vcpu
->arch
.vgic_cpu
.pending_percpu
);
232 set_bit(irq
- VGIC_NR_PRIVATE_IRQS
,
233 vcpu
->arch
.vgic_cpu
.pending_shared
);
236 static void vgic_cpu_irq_clear(struct kvm_vcpu
*vcpu
, int irq
)
238 if (irq
< VGIC_NR_PRIVATE_IRQS
)
239 clear_bit(irq
, vcpu
->arch
.vgic_cpu
.pending_percpu
);
241 clear_bit(irq
- VGIC_NR_PRIVATE_IRQS
,
242 vcpu
->arch
.vgic_cpu
.pending_shared
);
245 static u32
mmio_data_read(struct kvm_exit_mmio
*mmio
, u32 mask
)
247 return *((u32
*)mmio
->data
) & mask
;
250 static void mmio_data_write(struct kvm_exit_mmio
*mmio
, u32 mask
, u32 value
)
252 *((u32
*)mmio
->data
) = value
& mask
;
256 * vgic_reg_access - access vgic register
257 * @mmio: pointer to the data describing the mmio access
258 * @reg: pointer to the virtual backing of vgic distributor data
259 * @offset: least significant 2 bits used for word offset
260 * @mode: ACCESS_ mode (see defines above)
262 * Helper to make vgic register access easier using one of the access
263 * modes defined for vgic register access
264 * (read,raz,write-ignored,setbit,clearbit,write)
266 static void vgic_reg_access(struct kvm_exit_mmio
*mmio
, u32
*reg
,
267 phys_addr_t offset
, int mode
)
269 int word_offset
= (offset
& 3) * 8;
270 u32 mask
= (1UL << (mmio
->len
* 8)) - 1;
274 * Any alignment fault should have been delivered to the guest
275 * directly (ARM ARM B3.12.7 "Prioritization of aborts").
281 BUG_ON(mode
!= (ACCESS_READ_RAZ
| ACCESS_WRITE_IGNORED
));
285 if (mmio
->is_write
) {
286 u32 data
= mmio_data_read(mmio
, mask
) << word_offset
;
287 switch (ACCESS_WRITE_MASK(mode
)) {
288 case ACCESS_WRITE_IGNORED
:
291 case ACCESS_WRITE_SETBIT
:
295 case ACCESS_WRITE_CLEARBIT
:
299 case ACCESS_WRITE_VALUE
:
300 regval
= (regval
& ~(mask
<< word_offset
)) | data
;
305 switch (ACCESS_READ_MASK(mode
)) {
306 case ACCESS_READ_RAZ
:
310 case ACCESS_READ_VALUE
:
311 mmio_data_write(mmio
, mask
, regval
>> word_offset
);
316 static bool handle_mmio_misc(struct kvm_vcpu
*vcpu
,
317 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
320 u32 word_offset
= offset
& 3;
322 switch (offset
& ~3) {
323 case 0: /* GICD_CTLR */
324 reg
= vcpu
->kvm
->arch
.vgic
.enabled
;
325 vgic_reg_access(mmio
, ®
, word_offset
,
326 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
327 if (mmio
->is_write
) {
328 vcpu
->kvm
->arch
.vgic
.enabled
= reg
& 1;
329 vgic_update_state(vcpu
->kvm
);
334 case 4: /* GICD_TYPER */
335 reg
= (atomic_read(&vcpu
->kvm
->online_vcpus
) - 1) << 5;
336 reg
|= (VGIC_NR_IRQS
>> 5) - 1;
337 vgic_reg_access(mmio
, ®
, word_offset
,
338 ACCESS_READ_VALUE
| ACCESS_WRITE_IGNORED
);
341 case 8: /* GICD_IIDR */
342 reg
= (PRODUCT_ID_KVM
<< 24) | (IMPLEMENTER_ARM
<< 0);
343 vgic_reg_access(mmio
, ®
, word_offset
,
344 ACCESS_READ_VALUE
| ACCESS_WRITE_IGNORED
);
351 static bool handle_mmio_raz_wi(struct kvm_vcpu
*vcpu
,
352 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
354 vgic_reg_access(mmio
, NULL
, offset
,
355 ACCESS_READ_RAZ
| ACCESS_WRITE_IGNORED
);
359 static bool handle_mmio_set_enable_reg(struct kvm_vcpu
*vcpu
,
360 struct kvm_exit_mmio
*mmio
,
363 u32
*reg
= vgic_bitmap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_enabled
,
364 vcpu
->vcpu_id
, offset
);
365 vgic_reg_access(mmio
, reg
, offset
,
366 ACCESS_READ_VALUE
| ACCESS_WRITE_SETBIT
);
367 if (mmio
->is_write
) {
368 vgic_update_state(vcpu
->kvm
);
375 static bool handle_mmio_clear_enable_reg(struct kvm_vcpu
*vcpu
,
376 struct kvm_exit_mmio
*mmio
,
379 u32
*reg
= vgic_bitmap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_enabled
,
380 vcpu
->vcpu_id
, offset
);
381 vgic_reg_access(mmio
, reg
, offset
,
382 ACCESS_READ_VALUE
| ACCESS_WRITE_CLEARBIT
);
383 if (mmio
->is_write
) {
384 if (offset
< 4) /* Force SGI enabled */
386 vgic_retire_disabled_irqs(vcpu
);
387 vgic_update_state(vcpu
->kvm
);
394 static bool handle_mmio_set_pending_reg(struct kvm_vcpu
*vcpu
,
395 struct kvm_exit_mmio
*mmio
,
398 u32
*reg
= vgic_bitmap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_state
,
399 vcpu
->vcpu_id
, offset
);
400 vgic_reg_access(mmio
, reg
, offset
,
401 ACCESS_READ_VALUE
| ACCESS_WRITE_SETBIT
);
402 if (mmio
->is_write
) {
403 vgic_update_state(vcpu
->kvm
);
410 static bool handle_mmio_clear_pending_reg(struct kvm_vcpu
*vcpu
,
411 struct kvm_exit_mmio
*mmio
,
414 u32
*reg
= vgic_bitmap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_state
,
415 vcpu
->vcpu_id
, offset
);
416 vgic_reg_access(mmio
, reg
, offset
,
417 ACCESS_READ_VALUE
| ACCESS_WRITE_CLEARBIT
);
418 if (mmio
->is_write
) {
419 vgic_update_state(vcpu
->kvm
);
426 static bool handle_mmio_priority_reg(struct kvm_vcpu
*vcpu
,
427 struct kvm_exit_mmio
*mmio
,
430 u32
*reg
= vgic_bytemap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_priority
,
431 vcpu
->vcpu_id
, offset
);
432 vgic_reg_access(mmio
, reg
, offset
,
433 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
437 #define GICD_ITARGETSR_SIZE 32
438 #define GICD_CPUTARGETS_BITS 8
439 #define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS)
440 static u32
vgic_get_target_reg(struct kvm
*kvm
, int irq
)
442 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
446 irq
-= VGIC_NR_PRIVATE_IRQS
;
448 for (i
= 0; i
< GICD_IRQS_PER_ITARGETSR
; i
++)
449 val
|= 1 << (dist
->irq_spi_cpu
[irq
+ i
] + i
* 8);
454 static void vgic_set_target_reg(struct kvm
*kvm
, u32 val
, int irq
)
456 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
457 struct kvm_vcpu
*vcpu
;
462 irq
-= VGIC_NR_PRIVATE_IRQS
;
465 * Pick the LSB in each byte. This ensures we target exactly
466 * one vcpu per IRQ. If the byte is null, assume we target
469 for (i
= 0; i
< GICD_IRQS_PER_ITARGETSR
; i
++) {
470 int shift
= i
* GICD_CPUTARGETS_BITS
;
471 target
= ffs((val
>> shift
) & 0xffU
);
472 target
= target
? (target
- 1) : 0;
473 dist
->irq_spi_cpu
[irq
+ i
] = target
;
474 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
475 bmap
= vgic_bitmap_get_shared_map(&dist
->irq_spi_target
[c
]);
477 set_bit(irq
+ i
, bmap
);
479 clear_bit(irq
+ i
, bmap
);
484 static bool handle_mmio_target_reg(struct kvm_vcpu
*vcpu
,
485 struct kvm_exit_mmio
*mmio
,
490 /* We treat the banked interrupts targets as read-only */
492 u32 roreg
= 1 << vcpu
->vcpu_id
;
494 roreg
|= roreg
<< 16;
496 vgic_reg_access(mmio
, &roreg
, offset
,
497 ACCESS_READ_VALUE
| ACCESS_WRITE_IGNORED
);
501 reg
= vgic_get_target_reg(vcpu
->kvm
, offset
& ~3U);
502 vgic_reg_access(mmio
, ®
, offset
,
503 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
504 if (mmio
->is_write
) {
505 vgic_set_target_reg(vcpu
->kvm
, reg
, offset
& ~3U);
506 vgic_update_state(vcpu
->kvm
);
513 static u32
vgic_cfg_expand(u16 val
)
519 * Turn a 16bit value like abcd...mnop into a 32bit word
520 * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
522 for (i
= 0; i
< 16; i
++)
523 res
|= ((val
>> i
) & VGIC_CFG_EDGE
) << (2 * i
+ 1);
528 static u16
vgic_cfg_compress(u32 val
)
534 * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
535 * abcd...mnop which is what we really care about.
537 for (i
= 0; i
< 16; i
++)
538 res
|= ((val
>> (i
* 2 + 1)) & VGIC_CFG_EDGE
) << i
;
544 * The distributor uses 2 bits per IRQ for the CFG register, but the
545 * LSB is always 0. As such, we only keep the upper bit, and use the
546 * two above functions to compress/expand the bits
548 static bool handle_mmio_cfg_reg(struct kvm_vcpu
*vcpu
,
549 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
554 reg
= vgic_bitmap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_cfg
,
555 vcpu
->vcpu_id
, offset
>> 1);
562 val
= vgic_cfg_expand(val
);
563 vgic_reg_access(mmio
, &val
, offset
,
564 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
565 if (mmio
->is_write
) {
567 *reg
= ~0U; /* Force PPIs/SGIs to 1 */
571 val
= vgic_cfg_compress(val
);
576 *reg
&= 0xffff << 16;
584 static bool handle_mmio_sgi_reg(struct kvm_vcpu
*vcpu
,
585 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
588 vgic_reg_access(mmio
, ®
, offset
,
589 ACCESS_READ_RAZ
| ACCESS_WRITE_VALUE
);
590 if (mmio
->is_write
) {
591 vgic_dispatch_sgi(vcpu
, reg
);
592 vgic_update_state(vcpu
->kvm
);
600 * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor
601 * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs
603 * Move any pending IRQs that have already been assigned to LRs back to the
604 * emulated distributor state so that the complete emulated state can be read
605 * from the main emulation structures without investigating the LRs.
607 * Note that IRQs in the active state in the LRs get their pending state moved
608 * to the distributor but the active state stays in the LRs, because we don't
609 * track the active state on the distributor side.
611 static void vgic_unqueue_irqs(struct kvm_vcpu
*vcpu
)
613 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
614 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
615 int vcpu_id
= vcpu
->vcpu_id
;
618 for_each_set_bit(i
, vgic_cpu
->lr_used
, vgic_cpu
->nr_lr
) {
619 struct vgic_lr lr
= vgic_get_lr(vcpu
, i
);
622 * There are three options for the state bits:
626 * 11: pending and active
628 * If the LR holds only an active interrupt (not pending) then
629 * just leave it alone.
631 if ((lr
.state
& LR_STATE_MASK
) == LR_STATE_ACTIVE
)
635 * Reestablish the pending state on the distributor and the
636 * CPU interface. It may have already been pending, but that
637 * is fine, then we are only setting a few bits that were
640 vgic_dist_irq_set(vcpu
, lr
.irq
);
641 if (lr
.irq
< VGIC_NR_SGIS
)
642 dist
->irq_sgi_sources
[vcpu_id
][lr
.irq
] |= 1 << lr
.source
;
643 lr
.state
&= ~LR_STATE_PENDING
;
644 vgic_set_lr(vcpu
, i
, lr
);
647 * If there's no state left on the LR (it could still be
648 * active), then the LR does not hold any useful info and can
649 * be marked as free for other use.
651 if (!(lr
.state
& LR_STATE_MASK
))
652 vgic_retire_lr(i
, lr
.irq
, vcpu
);
654 /* Finally update the VGIC state. */
655 vgic_update_state(vcpu
->kvm
);
659 /* Handle reads of GICD_CPENDSGIRn and GICD_SPENDSGIRn */
660 static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu
*vcpu
,
661 struct kvm_exit_mmio
*mmio
,
664 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
666 int min_sgi
= (offset
& ~0x3) * 4;
667 int max_sgi
= min_sgi
+ 3;
668 int vcpu_id
= vcpu
->vcpu_id
;
671 /* Copy source SGIs from distributor side */
672 for (sgi
= min_sgi
; sgi
<= max_sgi
; sgi
++) {
673 int shift
= 8 * (sgi
- min_sgi
);
674 reg
|= (u32
)dist
->irq_sgi_sources
[vcpu_id
][sgi
] << shift
;
677 mmio_data_write(mmio
, ~0, reg
);
681 static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu
*vcpu
,
682 struct kvm_exit_mmio
*mmio
,
683 phys_addr_t offset
, bool set
)
685 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
687 int min_sgi
= (offset
& ~0x3) * 4;
688 int max_sgi
= min_sgi
+ 3;
689 int vcpu_id
= vcpu
->vcpu_id
;
691 bool updated
= false;
693 reg
= mmio_data_read(mmio
, ~0);
695 /* Clear pending SGIs on the distributor */
696 for (sgi
= min_sgi
; sgi
<= max_sgi
; sgi
++) {
697 u8 mask
= reg
>> (8 * (sgi
- min_sgi
));
699 if ((dist
->irq_sgi_sources
[vcpu_id
][sgi
] & mask
) != mask
)
701 dist
->irq_sgi_sources
[vcpu_id
][sgi
] |= mask
;
703 if (dist
->irq_sgi_sources
[vcpu_id
][sgi
] & mask
)
705 dist
->irq_sgi_sources
[vcpu_id
][sgi
] &= ~mask
;
710 vgic_update_state(vcpu
->kvm
);
715 static bool handle_mmio_sgi_set(struct kvm_vcpu
*vcpu
,
716 struct kvm_exit_mmio
*mmio
,
720 return read_set_clear_sgi_pend_reg(vcpu
, mmio
, offset
);
722 return write_set_clear_sgi_pend_reg(vcpu
, mmio
, offset
, true);
725 static bool handle_mmio_sgi_clear(struct kvm_vcpu
*vcpu
,
726 struct kvm_exit_mmio
*mmio
,
730 return read_set_clear_sgi_pend_reg(vcpu
, mmio
, offset
);
732 return write_set_clear_sgi_pend_reg(vcpu
, mmio
, offset
, false);
736 * I would have liked to use the kvm_bus_io_*() API instead, but it
737 * cannot cope with banked registers (only the VM pointer is passed
738 * around, and we need the vcpu). One of these days, someone please
744 bool (*handle_mmio
)(struct kvm_vcpu
*vcpu
, struct kvm_exit_mmio
*mmio
,
748 static const struct mmio_range vgic_dist_ranges
[] = {
750 .base
= GIC_DIST_CTRL
,
752 .handle_mmio
= handle_mmio_misc
,
755 .base
= GIC_DIST_IGROUP
,
756 .len
= VGIC_NR_IRQS
/ 8,
757 .handle_mmio
= handle_mmio_raz_wi
,
760 .base
= GIC_DIST_ENABLE_SET
,
761 .len
= VGIC_NR_IRQS
/ 8,
762 .handle_mmio
= handle_mmio_set_enable_reg
,
765 .base
= GIC_DIST_ENABLE_CLEAR
,
766 .len
= VGIC_NR_IRQS
/ 8,
767 .handle_mmio
= handle_mmio_clear_enable_reg
,
770 .base
= GIC_DIST_PENDING_SET
,
771 .len
= VGIC_NR_IRQS
/ 8,
772 .handle_mmio
= handle_mmio_set_pending_reg
,
775 .base
= GIC_DIST_PENDING_CLEAR
,
776 .len
= VGIC_NR_IRQS
/ 8,
777 .handle_mmio
= handle_mmio_clear_pending_reg
,
780 .base
= GIC_DIST_ACTIVE_SET
,
781 .len
= VGIC_NR_IRQS
/ 8,
782 .handle_mmio
= handle_mmio_raz_wi
,
785 .base
= GIC_DIST_ACTIVE_CLEAR
,
786 .len
= VGIC_NR_IRQS
/ 8,
787 .handle_mmio
= handle_mmio_raz_wi
,
790 .base
= GIC_DIST_PRI
,
792 .handle_mmio
= handle_mmio_priority_reg
,
795 .base
= GIC_DIST_TARGET
,
797 .handle_mmio
= handle_mmio_target_reg
,
800 .base
= GIC_DIST_CONFIG
,
801 .len
= VGIC_NR_IRQS
/ 4,
802 .handle_mmio
= handle_mmio_cfg_reg
,
805 .base
= GIC_DIST_SOFTINT
,
807 .handle_mmio
= handle_mmio_sgi_reg
,
810 .base
= GIC_DIST_SGI_PENDING_CLEAR
,
812 .handle_mmio
= handle_mmio_sgi_clear
,
815 .base
= GIC_DIST_SGI_PENDING_SET
,
817 .handle_mmio
= handle_mmio_sgi_set
,
823 struct mmio_range
*find_matching_range(const struct mmio_range
*ranges
,
824 struct kvm_exit_mmio
*mmio
,
827 const struct mmio_range
*r
= ranges
;
830 if (offset
>= r
->base
&&
831 (offset
+ mmio
->len
) <= (r
->base
+ r
->len
))
840 * vgic_handle_mmio - handle an in-kernel MMIO access
841 * @vcpu: pointer to the vcpu performing the access
842 * @run: pointer to the kvm_run structure
843 * @mmio: pointer to the data describing the access
845 * returns true if the MMIO access has been performed in kernel space,
846 * and false if it needs to be emulated in user space.
848 bool vgic_handle_mmio(struct kvm_vcpu
*vcpu
, struct kvm_run
*run
,
849 struct kvm_exit_mmio
*mmio
)
851 const struct mmio_range
*range
;
852 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
853 unsigned long base
= dist
->vgic_dist_base
;
855 unsigned long offset
;
857 if (!irqchip_in_kernel(vcpu
->kvm
) ||
858 mmio
->phys_addr
< base
||
859 (mmio
->phys_addr
+ mmio
->len
) > (base
+ KVM_VGIC_V2_DIST_SIZE
))
862 /* We don't support ldrd / strd or ldm / stm to the emulated vgic */
864 kvm_inject_dabt(vcpu
, mmio
->phys_addr
);
868 offset
= mmio
->phys_addr
- base
;
869 range
= find_matching_range(vgic_dist_ranges
, mmio
, offset
);
870 if (unlikely(!range
|| !range
->handle_mmio
)) {
871 pr_warn("Unhandled access %d %08llx %d\n",
872 mmio
->is_write
, mmio
->phys_addr
, mmio
->len
);
876 spin_lock(&vcpu
->kvm
->arch
.vgic
.lock
);
877 offset
= mmio
->phys_addr
- range
->base
- base
;
878 updated_state
= range
->handle_mmio(vcpu
, mmio
, offset
);
879 spin_unlock(&vcpu
->kvm
->arch
.vgic
.lock
);
880 kvm_prepare_mmio(run
, mmio
);
881 kvm_handle_mmio_return(vcpu
, run
);
884 vgic_kick_vcpus(vcpu
->kvm
);
889 static void vgic_dispatch_sgi(struct kvm_vcpu
*vcpu
, u32 reg
)
891 struct kvm
*kvm
= vcpu
->kvm
;
892 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
893 int nrcpus
= atomic_read(&kvm
->online_vcpus
);
895 int sgi
, mode
, c
, vcpu_id
;
897 vcpu_id
= vcpu
->vcpu_id
;
900 target_cpus
= (reg
>> 16) & 0xff;
901 mode
= (reg
>> 24) & 3;
910 target_cpus
= ((1 << nrcpus
) - 1) & ~(1 << vcpu_id
) & 0xff;
914 target_cpus
= 1 << vcpu_id
;
918 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
919 if (target_cpus
& 1) {
920 /* Flag the SGI as pending */
921 vgic_dist_irq_set(vcpu
, sgi
);
922 dist
->irq_sgi_sources
[c
][sgi
] |= 1 << vcpu_id
;
923 kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi
, vcpu_id
, c
);
930 static int compute_pending_for_cpu(struct kvm_vcpu
*vcpu
)
932 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
933 unsigned long *pending
, *enabled
, *pend_percpu
, *pend_shared
;
934 unsigned long pending_private
, pending_shared
;
937 vcpu_id
= vcpu
->vcpu_id
;
938 pend_percpu
= vcpu
->arch
.vgic_cpu
.pending_percpu
;
939 pend_shared
= vcpu
->arch
.vgic_cpu
.pending_shared
;
941 pending
= vgic_bitmap_get_cpu_map(&dist
->irq_state
, vcpu_id
);
942 enabled
= vgic_bitmap_get_cpu_map(&dist
->irq_enabled
, vcpu_id
);
943 bitmap_and(pend_percpu
, pending
, enabled
, VGIC_NR_PRIVATE_IRQS
);
945 pending
= vgic_bitmap_get_shared_map(&dist
->irq_state
);
946 enabled
= vgic_bitmap_get_shared_map(&dist
->irq_enabled
);
947 bitmap_and(pend_shared
, pending
, enabled
, VGIC_NR_SHARED_IRQS
);
948 bitmap_and(pend_shared
, pend_shared
,
949 vgic_bitmap_get_shared_map(&dist
->irq_spi_target
[vcpu_id
]),
950 VGIC_NR_SHARED_IRQS
);
952 pending_private
= find_first_bit(pend_percpu
, VGIC_NR_PRIVATE_IRQS
);
953 pending_shared
= find_first_bit(pend_shared
, VGIC_NR_SHARED_IRQS
);
954 return (pending_private
< VGIC_NR_PRIVATE_IRQS
||
955 pending_shared
< VGIC_NR_SHARED_IRQS
);
959 * Update the interrupt state and determine which CPUs have pending
960 * interrupts. Must be called with distributor lock held.
962 static void vgic_update_state(struct kvm
*kvm
)
964 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
965 struct kvm_vcpu
*vcpu
;
968 if (!dist
->enabled
) {
969 set_bit(0, &dist
->irq_pending_on_cpu
);
973 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
974 if (compute_pending_for_cpu(vcpu
)) {
975 pr_debug("CPU%d has pending interrupts\n", c
);
976 set_bit(c
, &dist
->irq_pending_on_cpu
);
981 static struct vgic_lr
vgic_v2_get_lr(const struct kvm_vcpu
*vcpu
, int lr
)
983 struct vgic_lr lr_desc
;
984 u32 val
= vcpu
->arch
.vgic_cpu
.vgic_v2
.vgic_lr
[lr
];
986 lr_desc
.irq
= val
& GICH_LR_VIRTUALID
;
987 if (lr_desc
.irq
<= 15)
988 lr_desc
.source
= (val
>> GICH_LR_PHYSID_CPUID_SHIFT
) & 0x7;
993 if (val
& GICH_LR_PENDING_BIT
)
994 lr_desc
.state
|= LR_STATE_PENDING
;
995 if (val
& GICH_LR_ACTIVE_BIT
)
996 lr_desc
.state
|= LR_STATE_ACTIVE
;
997 if (val
& GICH_LR_EOI
)
998 lr_desc
.state
|= LR_EOI_INT
;
1003 static void vgic_v2_set_lr(struct kvm_vcpu
*vcpu
, int lr
,
1004 struct vgic_lr lr_desc
)
1006 u32 lr_val
= (lr_desc
.source
<< GICH_LR_PHYSID_CPUID_SHIFT
) | lr_desc
.irq
;
1008 if (lr_desc
.state
& LR_STATE_PENDING
)
1009 lr_val
|= GICH_LR_PENDING_BIT
;
1010 if (lr_desc
.state
& LR_STATE_ACTIVE
)
1011 lr_val
|= GICH_LR_ACTIVE_BIT
;
1012 if (lr_desc
.state
& LR_EOI_INT
)
1013 lr_val
|= GICH_LR_EOI
;
1015 vcpu
->arch
.vgic_cpu
.vgic_v2
.vgic_lr
[lr
] = lr_val
;
1018 static const struct vgic_ops vgic_ops
= {
1019 .get_lr
= vgic_v2_get_lr
,
1020 .set_lr
= vgic_v2_set_lr
,
1023 static struct vgic_lr
vgic_get_lr(const struct kvm_vcpu
*vcpu
, int lr
)
1025 return vgic_ops
.get_lr(vcpu
, lr
);
1028 static void vgic_set_lr(struct kvm_vcpu
*vcpu
, int lr
,
1031 vgic_ops
.set_lr(vcpu
, lr
, vlr
);
1034 static void vgic_retire_lr(int lr_nr
, int irq
, struct kvm_vcpu
*vcpu
)
1036 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1037 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr_nr
);
1040 vgic_set_lr(vcpu
, lr_nr
, vlr
);
1041 clear_bit(lr_nr
, vgic_cpu
->lr_used
);
1042 vgic_cpu
->vgic_irq_lr_map
[irq
] = LR_EMPTY
;
1046 * An interrupt may have been disabled after being made pending on the
1047 * CPU interface (the classic case is a timer running while we're
1048 * rebooting the guest - the interrupt would kick as soon as the CPU
1049 * interface gets enabled, with deadly consequences).
1051 * The solution is to examine already active LRs, and check the
1052 * interrupt is still enabled. If not, just retire it.
1054 static void vgic_retire_disabled_irqs(struct kvm_vcpu
*vcpu
)
1056 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1059 for_each_set_bit(lr
, vgic_cpu
->lr_used
, vgic_cpu
->nr_lr
) {
1060 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr
);
1062 if (!vgic_irq_is_enabled(vcpu
, vlr
.irq
)) {
1063 vgic_retire_lr(lr
, vlr
.irq
, vcpu
);
1064 if (vgic_irq_is_active(vcpu
, vlr
.irq
))
1065 vgic_irq_clear_active(vcpu
, vlr
.irq
);
1071 * Queue an interrupt to a CPU virtual interface. Return true on success,
1072 * or false if it wasn't possible to queue it.
1074 static bool vgic_queue_irq(struct kvm_vcpu
*vcpu
, u8 sgi_source_id
, int irq
)
1076 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1080 /* Sanitize the input... */
1081 BUG_ON(sgi_source_id
& ~7);
1082 BUG_ON(sgi_source_id
&& irq
>= VGIC_NR_SGIS
);
1083 BUG_ON(irq
>= VGIC_NR_IRQS
);
1085 kvm_debug("Queue IRQ%d\n", irq
);
1087 lr
= vgic_cpu
->vgic_irq_lr_map
[irq
];
1089 /* Do we have an active interrupt for the same CPUID? */
1090 if (lr
!= LR_EMPTY
) {
1091 vlr
= vgic_get_lr(vcpu
, lr
);
1092 if (vlr
.source
== sgi_source_id
) {
1093 kvm_debug("LR%d piggyback for IRQ%d\n", lr
, vlr
.irq
);
1094 BUG_ON(!test_bit(lr
, vgic_cpu
->lr_used
));
1095 vlr
.state
|= LR_STATE_PENDING
;
1096 vgic_set_lr(vcpu
, lr
, vlr
);
1101 /* Try to use another LR for this interrupt */
1102 lr
= find_first_zero_bit((unsigned long *)vgic_cpu
->lr_used
,
1104 if (lr
>= vgic_cpu
->nr_lr
)
1107 kvm_debug("LR%d allocated for IRQ%d %x\n", lr
, irq
, sgi_source_id
);
1108 vgic_cpu
->vgic_irq_lr_map
[irq
] = lr
;
1109 set_bit(lr
, vgic_cpu
->lr_used
);
1112 vlr
.source
= sgi_source_id
;
1113 vlr
.state
= LR_STATE_PENDING
;
1114 if (!vgic_irq_is_edge(vcpu
, irq
))
1115 vlr
.state
|= LR_EOI_INT
;
1117 vgic_set_lr(vcpu
, lr
, vlr
);
1122 static bool vgic_queue_sgi(struct kvm_vcpu
*vcpu
, int irq
)
1124 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1125 unsigned long sources
;
1126 int vcpu_id
= vcpu
->vcpu_id
;
1129 sources
= dist
->irq_sgi_sources
[vcpu_id
][irq
];
1131 for_each_set_bit(c
, &sources
, VGIC_MAX_CPUS
) {
1132 if (vgic_queue_irq(vcpu
, c
, irq
))
1133 clear_bit(c
, &sources
);
1136 dist
->irq_sgi_sources
[vcpu_id
][irq
] = sources
;
1139 * If the sources bitmap has been cleared it means that we
1140 * could queue all the SGIs onto link registers (see the
1141 * clear_bit above), and therefore we are done with them in
1142 * our emulated gic and can get rid of them.
1145 vgic_dist_irq_clear(vcpu
, irq
);
1146 vgic_cpu_irq_clear(vcpu
, irq
);
1153 static bool vgic_queue_hwirq(struct kvm_vcpu
*vcpu
, int irq
)
1155 if (vgic_irq_is_active(vcpu
, irq
))
1156 return true; /* level interrupt, already queued */
1158 if (vgic_queue_irq(vcpu
, 0, irq
)) {
1159 if (vgic_irq_is_edge(vcpu
, irq
)) {
1160 vgic_dist_irq_clear(vcpu
, irq
);
1161 vgic_cpu_irq_clear(vcpu
, irq
);
1163 vgic_irq_set_active(vcpu
, irq
);
1173 * Fill the list registers with pending interrupts before running the
1176 static void __kvm_vgic_flush_hwstate(struct kvm_vcpu
*vcpu
)
1178 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1179 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1183 vcpu_id
= vcpu
->vcpu_id
;
1186 * We may not have any pending interrupt, or the interrupts
1187 * may have been serviced from another vcpu. In all cases,
1190 if (!kvm_vgic_vcpu_pending_irq(vcpu
)) {
1191 pr_debug("CPU%d has no pending interrupt\n", vcpu_id
);
1196 for_each_set_bit(i
, vgic_cpu
->pending_percpu
, VGIC_NR_SGIS
) {
1197 if (!vgic_queue_sgi(vcpu
, i
))
1202 for_each_set_bit_from(i
, vgic_cpu
->pending_percpu
, VGIC_NR_PRIVATE_IRQS
) {
1203 if (!vgic_queue_hwirq(vcpu
, i
))
1208 for_each_set_bit(i
, vgic_cpu
->pending_shared
, VGIC_NR_SHARED_IRQS
) {
1209 if (!vgic_queue_hwirq(vcpu
, i
+ VGIC_NR_PRIVATE_IRQS
))
1215 vgic_cpu
->vgic_v2
.vgic_hcr
|= GICH_HCR_UIE
;
1217 vgic_cpu
->vgic_v2
.vgic_hcr
&= ~GICH_HCR_UIE
;
1219 * We're about to run this VCPU, and we've consumed
1220 * everything the distributor had in store for
1221 * us. Claim we don't have anything pending. We'll
1222 * adjust that if needed while exiting.
1224 clear_bit(vcpu_id
, &dist
->irq_pending_on_cpu
);
1228 static bool vgic_process_maintenance(struct kvm_vcpu
*vcpu
)
1230 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1231 bool level_pending
= false;
1233 kvm_debug("MISR = %08x\n", vgic_cpu
->vgic_v2
.vgic_misr
);
1235 if (vgic_cpu
->vgic_v2
.vgic_misr
& GICH_MISR_EOI
) {
1237 * Some level interrupts have been EOIed. Clear their
1242 for_each_set_bit(lr
, (unsigned long *)vgic_cpu
->vgic_v2
.vgic_eisr
,
1244 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr
);
1246 vgic_irq_clear_active(vcpu
, vlr
.irq
);
1247 WARN_ON(vlr
.state
& LR_STATE_MASK
);
1249 vgic_set_lr(vcpu
, lr
, vlr
);
1251 /* Any additional pending interrupt? */
1252 if (vgic_dist_irq_is_pending(vcpu
, vlr
.irq
)) {
1253 vgic_cpu_irq_set(vcpu
, vlr
.irq
);
1254 level_pending
= true;
1256 vgic_cpu_irq_clear(vcpu
, vlr
.irq
);
1260 * Despite being EOIed, the LR may not have
1261 * been marked as empty.
1263 set_bit(lr
, (unsigned long *)vgic_cpu
->vgic_v2
.vgic_elrsr
);
1267 if (vgic_cpu
->vgic_v2
.vgic_misr
& GICH_MISR_U
)
1268 vgic_cpu
->vgic_v2
.vgic_hcr
&= ~GICH_HCR_UIE
;
1270 return level_pending
;
1274 * Sync back the VGIC state after a guest run. The distributor lock is
1275 * needed so we don't get preempted in the middle of the state processing.
1277 static void __kvm_vgic_sync_hwstate(struct kvm_vcpu
*vcpu
)
1279 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1280 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1284 level_pending
= vgic_process_maintenance(vcpu
);
1286 /* Clear mappings for empty LRs */
1287 for_each_set_bit(lr
, (unsigned long *)vgic_cpu
->vgic_v2
.vgic_elrsr
,
1291 if (!test_and_clear_bit(lr
, vgic_cpu
->lr_used
))
1294 vlr
= vgic_get_lr(vcpu
, lr
);
1296 BUG_ON(vlr
.irq
>= VGIC_NR_IRQS
);
1297 vgic_cpu
->vgic_irq_lr_map
[vlr
.irq
] = LR_EMPTY
;
1300 /* Check if we still have something up our sleeve... */
1301 pending
= find_first_zero_bit((unsigned long *)vgic_cpu
->vgic_v2
.vgic_elrsr
,
1303 if (level_pending
|| pending
< vgic_cpu
->nr_lr
)
1304 set_bit(vcpu
->vcpu_id
, &dist
->irq_pending_on_cpu
);
1307 void kvm_vgic_flush_hwstate(struct kvm_vcpu
*vcpu
)
1309 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1311 if (!irqchip_in_kernel(vcpu
->kvm
))
1314 spin_lock(&dist
->lock
);
1315 __kvm_vgic_flush_hwstate(vcpu
);
1316 spin_unlock(&dist
->lock
);
1319 void kvm_vgic_sync_hwstate(struct kvm_vcpu
*vcpu
)
1321 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1323 if (!irqchip_in_kernel(vcpu
->kvm
))
1326 spin_lock(&dist
->lock
);
1327 __kvm_vgic_sync_hwstate(vcpu
);
1328 spin_unlock(&dist
->lock
);
1331 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu
*vcpu
)
1333 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1335 if (!irqchip_in_kernel(vcpu
->kvm
))
1338 return test_bit(vcpu
->vcpu_id
, &dist
->irq_pending_on_cpu
);
1341 static void vgic_kick_vcpus(struct kvm
*kvm
)
1343 struct kvm_vcpu
*vcpu
;
1347 * We've injected an interrupt, time to find out who deserves
1350 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
1351 if (kvm_vgic_vcpu_pending_irq(vcpu
))
1352 kvm_vcpu_kick(vcpu
);
1356 static int vgic_validate_injection(struct kvm_vcpu
*vcpu
, int irq
, int level
)
1358 int is_edge
= vgic_irq_is_edge(vcpu
, irq
);
1359 int state
= vgic_dist_irq_is_pending(vcpu
, irq
);
1362 * Only inject an interrupt if:
1363 * - edge triggered and we have a rising edge
1364 * - level triggered and we change level
1367 return level
> state
;
1369 return level
!= state
;
1372 static bool vgic_update_irq_state(struct kvm
*kvm
, int cpuid
,
1373 unsigned int irq_num
, bool level
)
1375 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1376 struct kvm_vcpu
*vcpu
;
1377 int is_edge
, is_level
;
1381 spin_lock(&dist
->lock
);
1383 vcpu
= kvm_get_vcpu(kvm
, cpuid
);
1384 is_edge
= vgic_irq_is_edge(vcpu
, irq_num
);
1385 is_level
= !is_edge
;
1387 if (!vgic_validate_injection(vcpu
, irq_num
, level
)) {
1392 if (irq_num
>= VGIC_NR_PRIVATE_IRQS
) {
1393 cpuid
= dist
->irq_spi_cpu
[irq_num
- VGIC_NR_PRIVATE_IRQS
];
1394 vcpu
= kvm_get_vcpu(kvm
, cpuid
);
1397 kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num
, level
, cpuid
);
1400 vgic_dist_irq_set(vcpu
, irq_num
);
1402 vgic_dist_irq_clear(vcpu
, irq_num
);
1404 enabled
= vgic_irq_is_enabled(vcpu
, irq_num
);
1411 if (is_level
&& vgic_irq_is_active(vcpu
, irq_num
)) {
1413 * Level interrupt in progress, will be picked up
1421 vgic_cpu_irq_set(vcpu
, irq_num
);
1422 set_bit(cpuid
, &dist
->irq_pending_on_cpu
);
1426 spin_unlock(&dist
->lock
);
1432 * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
1433 * @kvm: The VM structure pointer
1434 * @cpuid: The CPU for PPIs
1435 * @irq_num: The IRQ number that is assigned to the device
1436 * @level: Edge-triggered: true: to trigger the interrupt
1437 * false: to ignore the call
1438 * Level-sensitive true: activates an interrupt
1439 * false: deactivates an interrupt
1441 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1442 * level-sensitive interrupts. You can think of the level parameter as 1
1443 * being HIGH and 0 being LOW and all devices being active-HIGH.
1445 int kvm_vgic_inject_irq(struct kvm
*kvm
, int cpuid
, unsigned int irq_num
,
1448 if (vgic_update_irq_state(kvm
, cpuid
, irq_num
, level
))
1449 vgic_kick_vcpus(kvm
);
1454 static irqreturn_t
vgic_maintenance_handler(int irq
, void *data
)
1457 * We cannot rely on the vgic maintenance interrupt to be
1458 * delivered synchronously. This means we can only use it to
1459 * exit the VM, and we perform the handling of EOIed
1460 * interrupts on the exit path (see vgic_process_maintenance).
1466 * kvm_vgic_vcpu_init - Initialize per-vcpu VGIC state
1467 * @vcpu: pointer to the vcpu struct
1469 * Initialize the vgic_cpu struct and vgic_dist struct fields pertaining to
1470 * this vcpu and enable the VGIC for this VCPU
1472 int kvm_vgic_vcpu_init(struct kvm_vcpu
*vcpu
)
1474 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1475 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1478 if (vcpu
->vcpu_id
>= VGIC_MAX_CPUS
)
1481 for (i
= 0; i
< VGIC_NR_IRQS
; i
++) {
1482 if (i
< VGIC_NR_PPIS
)
1483 vgic_bitmap_set_irq_val(&dist
->irq_enabled
,
1484 vcpu
->vcpu_id
, i
, 1);
1485 if (i
< VGIC_NR_PRIVATE_IRQS
)
1486 vgic_bitmap_set_irq_val(&dist
->irq_cfg
,
1487 vcpu
->vcpu_id
, i
, VGIC_CFG_EDGE
);
1489 vgic_cpu
->vgic_irq_lr_map
[i
] = LR_EMPTY
;
1493 * By forcing VMCR to zero, the GIC will restore the binary
1494 * points to their reset values. Anything else resets to zero
1497 vgic_cpu
->vgic_v2
.vgic_vmcr
= 0;
1499 vgic_cpu
->nr_lr
= vgic_nr_lr
;
1500 vgic_cpu
->vgic_v2
.vgic_hcr
= GICH_HCR_EN
; /* Get the show on the road... */
1505 static void vgic_init_maintenance_interrupt(void *info
)
1507 enable_percpu_irq(vgic_maint_irq
, 0);
1510 static int vgic_cpu_notify(struct notifier_block
*self
,
1511 unsigned long action
, void *cpu
)
1515 case CPU_STARTING_FROZEN
:
1516 vgic_init_maintenance_interrupt(NULL
);
1519 case CPU_DYING_FROZEN
:
1520 disable_percpu_irq(vgic_maint_irq
);
1527 static struct notifier_block vgic_cpu_nb
= {
1528 .notifier_call
= vgic_cpu_notify
,
1531 int kvm_vgic_hyp_init(void)
1534 struct resource vctrl_res
;
1535 struct resource vcpu_res
;
1537 vgic_node
= of_find_compatible_node(NULL
, NULL
, "arm,cortex-a15-gic");
1539 kvm_err("error: no compatible vgic node in DT\n");
1543 vgic_maint_irq
= irq_of_parse_and_map(vgic_node
, 0);
1544 if (!vgic_maint_irq
) {
1545 kvm_err("error getting vgic maintenance irq from DT\n");
1550 ret
= request_percpu_irq(vgic_maint_irq
, vgic_maintenance_handler
,
1551 "vgic", kvm_get_running_vcpus());
1553 kvm_err("Cannot register interrupt %d\n", vgic_maint_irq
);
1557 ret
= __register_cpu_notifier(&vgic_cpu_nb
);
1559 kvm_err("Cannot register vgic CPU notifier\n");
1563 ret
= of_address_to_resource(vgic_node
, 2, &vctrl_res
);
1565 kvm_err("Cannot obtain VCTRL resource\n");
1569 vgic_vctrl_base
= of_iomap(vgic_node
, 2);
1570 if (!vgic_vctrl_base
) {
1571 kvm_err("Cannot ioremap VCTRL\n");
1576 vgic_nr_lr
= readl_relaxed(vgic_vctrl_base
+ GICH_VTR
);
1577 vgic_nr_lr
= (vgic_nr_lr
& 0x3f) + 1;
1579 ret
= create_hyp_io_mappings(vgic_vctrl_base
,
1580 vgic_vctrl_base
+ resource_size(&vctrl_res
),
1583 kvm_err("Cannot map VCTRL into hyp\n");
1587 kvm_info("%s@%llx IRQ%d\n", vgic_node
->name
,
1588 vctrl_res
.start
, vgic_maint_irq
);
1589 on_each_cpu(vgic_init_maintenance_interrupt
, NULL
, 1);
1591 if (of_address_to_resource(vgic_node
, 3, &vcpu_res
)) {
1592 kvm_err("Cannot obtain VCPU resource\n");
1596 vgic_vcpu_base
= vcpu_res
.start
;
1601 iounmap(vgic_vctrl_base
);
1603 free_percpu_irq(vgic_maint_irq
, kvm_get_running_vcpus());
1605 of_node_put(vgic_node
);
1610 * kvm_vgic_init - Initialize global VGIC state before running any VCPUs
1611 * @kvm: pointer to the kvm struct
1613 * Map the virtual CPU interface into the VM before running any VCPUs. We
1614 * can't do this at creation time, because user space must first set the
1615 * virtual CPU interface address in the guest physical address space. Also
1616 * initialize the ITARGETSRn regs to 0 on the emulated distributor.
1618 int kvm_vgic_init(struct kvm
*kvm
)
1622 if (!irqchip_in_kernel(kvm
))
1625 mutex_lock(&kvm
->lock
);
1627 if (vgic_initialized(kvm
))
1630 if (IS_VGIC_ADDR_UNDEF(kvm
->arch
.vgic
.vgic_dist_base
) ||
1631 IS_VGIC_ADDR_UNDEF(kvm
->arch
.vgic
.vgic_cpu_base
)) {
1632 kvm_err("Need to set vgic cpu and dist addresses first\n");
1637 ret
= kvm_phys_addr_ioremap(kvm
, kvm
->arch
.vgic
.vgic_cpu_base
,
1638 vgic_vcpu_base
, KVM_VGIC_V2_CPU_SIZE
);
1640 kvm_err("Unable to remap VGIC CPU to VCPU\n");
1644 for (i
= VGIC_NR_PRIVATE_IRQS
; i
< VGIC_NR_IRQS
; i
+= 4)
1645 vgic_set_target_reg(kvm
, 0, i
);
1647 kvm
->arch
.vgic
.ready
= true;
1649 mutex_unlock(&kvm
->lock
);
1653 int kvm_vgic_create(struct kvm
*kvm
)
1655 int i
, vcpu_lock_idx
= -1, ret
= 0;
1656 struct kvm_vcpu
*vcpu
;
1658 mutex_lock(&kvm
->lock
);
1660 if (kvm
->arch
.vgic
.vctrl_base
) {
1666 * Any time a vcpu is run, vcpu_load is called which tries to grab the
1667 * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure
1668 * that no other VCPUs are run while we create the vgic.
1670 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
1671 if (!mutex_trylock(&vcpu
->mutex
))
1676 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
1677 if (vcpu
->arch
.has_run_once
) {
1683 spin_lock_init(&kvm
->arch
.vgic
.lock
);
1684 kvm
->arch
.vgic
.vctrl_base
= vgic_vctrl_base
;
1685 kvm
->arch
.vgic
.vgic_dist_base
= VGIC_ADDR_UNDEF
;
1686 kvm
->arch
.vgic
.vgic_cpu_base
= VGIC_ADDR_UNDEF
;
1689 for (; vcpu_lock_idx
>= 0; vcpu_lock_idx
--) {
1690 vcpu
= kvm_get_vcpu(kvm
, vcpu_lock_idx
);
1691 mutex_unlock(&vcpu
->mutex
);
1695 mutex_unlock(&kvm
->lock
);
1699 static bool vgic_ioaddr_overlap(struct kvm
*kvm
)
1701 phys_addr_t dist
= kvm
->arch
.vgic
.vgic_dist_base
;
1702 phys_addr_t cpu
= kvm
->arch
.vgic
.vgic_cpu_base
;
1704 if (IS_VGIC_ADDR_UNDEF(dist
) || IS_VGIC_ADDR_UNDEF(cpu
))
1706 if ((dist
<= cpu
&& dist
+ KVM_VGIC_V2_DIST_SIZE
> cpu
) ||
1707 (cpu
<= dist
&& cpu
+ KVM_VGIC_V2_CPU_SIZE
> dist
))
1712 static int vgic_ioaddr_assign(struct kvm
*kvm
, phys_addr_t
*ioaddr
,
1713 phys_addr_t addr
, phys_addr_t size
)
1717 if (addr
& ~KVM_PHYS_MASK
)
1720 if (addr
& (SZ_4K
- 1))
1723 if (!IS_VGIC_ADDR_UNDEF(*ioaddr
))
1725 if (addr
+ size
< addr
)
1729 ret
= vgic_ioaddr_overlap(kvm
);
1731 *ioaddr
= VGIC_ADDR_UNDEF
;
1737 * kvm_vgic_addr - set or get vgic VM base addresses
1738 * @kvm: pointer to the vm struct
1739 * @type: the VGIC addr type, one of KVM_VGIC_V2_ADDR_TYPE_XXX
1740 * @addr: pointer to address value
1741 * @write: if true set the address in the VM address space, if false read the
1744 * Set or get the vgic base addresses for the distributor and the virtual CPU
1745 * interface in the VM physical address space. These addresses are properties
1746 * of the emulated core/SoC and therefore user space initially knows this
1749 int kvm_vgic_addr(struct kvm
*kvm
, unsigned long type
, u64
*addr
, bool write
)
1752 struct vgic_dist
*vgic
= &kvm
->arch
.vgic
;
1754 mutex_lock(&kvm
->lock
);
1756 case KVM_VGIC_V2_ADDR_TYPE_DIST
:
1758 r
= vgic_ioaddr_assign(kvm
, &vgic
->vgic_dist_base
,
1759 *addr
, KVM_VGIC_V2_DIST_SIZE
);
1761 *addr
= vgic
->vgic_dist_base
;
1764 case KVM_VGIC_V2_ADDR_TYPE_CPU
:
1766 r
= vgic_ioaddr_assign(kvm
, &vgic
->vgic_cpu_base
,
1767 *addr
, KVM_VGIC_V2_CPU_SIZE
);
1769 *addr
= vgic
->vgic_cpu_base
;
1776 mutex_unlock(&kvm
->lock
);
1780 static bool handle_cpu_mmio_misc(struct kvm_vcpu
*vcpu
,
1781 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
1783 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1784 u32 reg
, mask
= 0, shift
= 0;
1785 bool updated
= false;
1787 switch (offset
& ~0x3) {
1789 mask
= GICH_VMCR_CTRL_MASK
;
1790 shift
= GICH_VMCR_CTRL_SHIFT
;
1792 case GIC_CPU_PRIMASK
:
1793 mask
= GICH_VMCR_PRIMASK_MASK
;
1794 shift
= GICH_VMCR_PRIMASK_SHIFT
;
1796 case GIC_CPU_BINPOINT
:
1797 mask
= GICH_VMCR_BINPOINT_MASK
;
1798 shift
= GICH_VMCR_BINPOINT_SHIFT
;
1800 case GIC_CPU_ALIAS_BINPOINT
:
1801 mask
= GICH_VMCR_ALIAS_BINPOINT_MASK
;
1802 shift
= GICH_VMCR_ALIAS_BINPOINT_SHIFT
;
1806 if (!mmio
->is_write
) {
1807 reg
= (vgic_cpu
->vgic_v2
.vgic_vmcr
& mask
) >> shift
;
1808 mmio_data_write(mmio
, ~0, reg
);
1810 reg
= mmio_data_read(mmio
, ~0);
1811 reg
= (reg
<< shift
) & mask
;
1812 if (reg
!= (vgic_cpu
->vgic_v2
.vgic_vmcr
& mask
))
1814 vgic_cpu
->vgic_v2
.vgic_vmcr
&= ~mask
;
1815 vgic_cpu
->vgic_v2
.vgic_vmcr
|= reg
;
1820 static bool handle_mmio_abpr(struct kvm_vcpu
*vcpu
,
1821 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
1823 return handle_cpu_mmio_misc(vcpu
, mmio
, GIC_CPU_ALIAS_BINPOINT
);
1826 static bool handle_cpu_mmio_ident(struct kvm_vcpu
*vcpu
,
1827 struct kvm_exit_mmio
*mmio
,
1836 reg
= (PRODUCT_ID_KVM
<< 20) |
1837 (GICC_ARCH_VERSION_V2
<< 16) |
1838 (IMPLEMENTER_ARM
<< 0);
1839 mmio_data_write(mmio
, ~0, reg
);
1844 * CPU Interface Register accesses - these are not accessed by the VM, but by
1845 * user space for saving and restoring VGIC state.
1847 static const struct mmio_range vgic_cpu_ranges
[] = {
1849 .base
= GIC_CPU_CTRL
,
1851 .handle_mmio
= handle_cpu_mmio_misc
,
1854 .base
= GIC_CPU_ALIAS_BINPOINT
,
1856 .handle_mmio
= handle_mmio_abpr
,
1859 .base
= GIC_CPU_ACTIVEPRIO
,
1861 .handle_mmio
= handle_mmio_raz_wi
,
1864 .base
= GIC_CPU_IDENT
,
1866 .handle_mmio
= handle_cpu_mmio_ident
,
1870 static int vgic_attr_regs_access(struct kvm_device
*dev
,
1871 struct kvm_device_attr
*attr
,
1872 u32
*reg
, bool is_write
)
1874 const struct mmio_range
*r
= NULL
, *ranges
;
1877 struct kvm_vcpu
*vcpu
, *tmp_vcpu
;
1878 struct vgic_dist
*vgic
;
1879 struct kvm_exit_mmio mmio
;
1881 offset
= attr
->attr
& KVM_DEV_ARM_VGIC_OFFSET_MASK
;
1882 cpuid
= (attr
->attr
& KVM_DEV_ARM_VGIC_CPUID_MASK
) >>
1883 KVM_DEV_ARM_VGIC_CPUID_SHIFT
;
1885 mutex_lock(&dev
->kvm
->lock
);
1887 if (cpuid
>= atomic_read(&dev
->kvm
->online_vcpus
)) {
1892 vcpu
= kvm_get_vcpu(dev
->kvm
, cpuid
);
1893 vgic
= &dev
->kvm
->arch
.vgic
;
1896 mmio
.is_write
= is_write
;
1898 mmio_data_write(&mmio
, ~0, *reg
);
1899 switch (attr
->group
) {
1900 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS
:
1901 mmio
.phys_addr
= vgic
->vgic_dist_base
+ offset
;
1902 ranges
= vgic_dist_ranges
;
1904 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS
:
1905 mmio
.phys_addr
= vgic
->vgic_cpu_base
+ offset
;
1906 ranges
= vgic_cpu_ranges
;
1911 r
= find_matching_range(ranges
, &mmio
, offset
);
1913 if (unlikely(!r
|| !r
->handle_mmio
)) {
1919 spin_lock(&vgic
->lock
);
1922 * Ensure that no other VCPU is running by checking the vcpu->cpu
1923 * field. If no other VPCUs are running we can safely access the VGIC
1924 * state, because even if another VPU is run after this point, that
1925 * VCPU will not touch the vgic state, because it will block on
1926 * getting the vgic->lock in kvm_vgic_sync_hwstate().
1928 kvm_for_each_vcpu(c
, tmp_vcpu
, dev
->kvm
) {
1929 if (unlikely(tmp_vcpu
->cpu
!= -1)) {
1931 goto out_vgic_unlock
;
1936 * Move all pending IRQs from the LRs on all VCPUs so the pending
1937 * state can be properly represented in the register state accessible
1940 kvm_for_each_vcpu(c
, tmp_vcpu
, dev
->kvm
)
1941 vgic_unqueue_irqs(tmp_vcpu
);
1944 r
->handle_mmio(vcpu
, &mmio
, offset
);
1947 *reg
= mmio_data_read(&mmio
, ~0);
1951 spin_unlock(&vgic
->lock
);
1953 mutex_unlock(&dev
->kvm
->lock
);
1957 static int vgic_set_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
1961 switch (attr
->group
) {
1962 case KVM_DEV_ARM_VGIC_GRP_ADDR
: {
1963 u64 __user
*uaddr
= (u64 __user
*)(long)attr
->addr
;
1965 unsigned long type
= (unsigned long)attr
->attr
;
1967 if (copy_from_user(&addr
, uaddr
, sizeof(addr
)))
1970 r
= kvm_vgic_addr(dev
->kvm
, type
, &addr
, true);
1971 return (r
== -ENODEV
) ? -ENXIO
: r
;
1974 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS
:
1975 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS
: {
1976 u32 __user
*uaddr
= (u32 __user
*)(long)attr
->addr
;
1979 if (get_user(reg
, uaddr
))
1982 return vgic_attr_regs_access(dev
, attr
, ®
, true);
1990 static int vgic_get_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
1994 switch (attr
->group
) {
1995 case KVM_DEV_ARM_VGIC_GRP_ADDR
: {
1996 u64 __user
*uaddr
= (u64 __user
*)(long)attr
->addr
;
1998 unsigned long type
= (unsigned long)attr
->attr
;
2000 r
= kvm_vgic_addr(dev
->kvm
, type
, &addr
, false);
2002 return (r
== -ENODEV
) ? -ENXIO
: r
;
2004 if (copy_to_user(uaddr
, &addr
, sizeof(addr
)))
2009 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS
:
2010 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS
: {
2011 u32 __user
*uaddr
= (u32 __user
*)(long)attr
->addr
;
2014 r
= vgic_attr_regs_access(dev
, attr
, ®
, false);
2017 r
= put_user(reg
, uaddr
);
2026 static int vgic_has_attr_regs(const struct mmio_range
*ranges
,
2029 struct kvm_exit_mmio dev_attr_mmio
;
2031 dev_attr_mmio
.len
= 4;
2032 if (find_matching_range(ranges
, &dev_attr_mmio
, offset
))
2038 static int vgic_has_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
2042 switch (attr
->group
) {
2043 case KVM_DEV_ARM_VGIC_GRP_ADDR
:
2044 switch (attr
->attr
) {
2045 case KVM_VGIC_V2_ADDR_TYPE_DIST
:
2046 case KVM_VGIC_V2_ADDR_TYPE_CPU
:
2050 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS
:
2051 offset
= attr
->attr
& KVM_DEV_ARM_VGIC_OFFSET_MASK
;
2052 return vgic_has_attr_regs(vgic_dist_ranges
, offset
);
2053 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS
:
2054 offset
= attr
->attr
& KVM_DEV_ARM_VGIC_OFFSET_MASK
;
2055 return vgic_has_attr_regs(vgic_cpu_ranges
, offset
);
2060 static void vgic_destroy(struct kvm_device
*dev
)
2065 static int vgic_create(struct kvm_device
*dev
, u32 type
)
2067 return kvm_vgic_create(dev
->kvm
);
2070 struct kvm_device_ops kvm_arm_vgic_v2_ops
= {
2071 .name
= "kvm-arm-vgic",
2072 .create
= vgic_create
,
2073 .destroy
= vgic_destroy
,
2074 .set_attr
= vgic_set_attr
,
2075 .get_attr
= vgic_get_attr
,
2076 .has_attr
= vgic_has_attr
,