2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/cpu.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_host.h>
22 #include <linux/interrupt.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/rculist.h>
28 #include <linux/uaccess.h>
30 #include <asm/kvm_emulate.h>
31 #include <asm/kvm_arm.h>
32 #include <asm/kvm_mmu.h>
33 #include <trace/events/kvm.h>
35 #include <kvm/iodev.h>
37 #define CREATE_TRACE_POINTS
41 * How the whole thing works (courtesy of Christoffer Dall):
43 * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
44 * something is pending on the CPU interface.
45 * - Interrupts that are pending on the distributor are stored on the
46 * vgic.irq_pending vgic bitmap (this bitmap is updated by both user land
47 * ioctls and guest mmio ops, and other in-kernel peripherals such as the
49 * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
51 * - To calculate the oracle, we need info for each cpu from
52 * compute_pending_for_cpu, which considers:
53 * - PPI: dist->irq_pending & dist->irq_enable
54 * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target
55 * - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn
56 * registers, stored on each vcpu. We only keep one bit of
57 * information per interrupt, making sure that only one vcpu can
58 * accept the interrupt.
59 * - If any of the above state changes, we must recalculate the oracle.
60 * - The same is true when injecting an interrupt, except that we only
61 * consider a single interrupt at a time. The irq_spi_cpu array
62 * contains the target CPU for each SPI.
64 * The handling of level interrupts adds some extra complexity. We
65 * need to track when the interrupt has been EOIed, so we can sample
66 * the 'line' again. This is achieved as such:
68 * - When a level interrupt is moved onto a vcpu, the corresponding
69 * bit in irq_queued is set. As long as this bit is set, the line
70 * will be ignored for further interrupts. The interrupt is injected
71 * into the vcpu with the GICH_LR_EOI bit set (generate a
72 * maintenance interrupt on EOI).
73 * - When the interrupt is EOIed, the maintenance interrupt fires,
74 * and clears the corresponding bit in irq_queued. This allows the
75 * interrupt line to be sampled again.
76 * - Note that level-triggered interrupts can also be set to pending from
77 * writes to GICD_ISPENDRn and lowering the external input line does not
78 * cause the interrupt to become inactive in such a situation.
79 * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become
80 * inactive as long as the external input line is held high.
83 * Initialization rules: there are multiple stages to the vgic
84 * initialization, both for the distributor and the CPU interfaces.
88 * - kvm_vgic_early_init(): initialization of static data that doesn't
89 * depend on any sizing information or emulation type. No allocation
92 * - vgic_init(): allocation and initialization of the generic data
93 * structures that depend on sizing information (number of CPUs,
94 * number of interrupts). Also initializes the vcpu specific data
95 * structures. Can be executed lazily for GICv2.
96 * [to be renamed to kvm_vgic_init??]
100 * - kvm_vgic_cpu_early_init(): initialization of static data that
101 * doesn't depend on any sizing information or emulation type. No
102 * allocation is allowed there.
107 static void vgic_retire_disabled_irqs(struct kvm_vcpu
*vcpu
);
108 static void vgic_retire_lr(int lr_nr
, struct kvm_vcpu
*vcpu
);
109 static struct vgic_lr
vgic_get_lr(const struct kvm_vcpu
*vcpu
, int lr
);
110 static void vgic_set_lr(struct kvm_vcpu
*vcpu
, int lr
, struct vgic_lr lr_desc
);
111 static u64
vgic_get_elrsr(struct kvm_vcpu
*vcpu
);
112 static struct irq_phys_map
*vgic_irq_map_search(struct kvm_vcpu
*vcpu
,
114 static int compute_pending_for_cpu(struct kvm_vcpu
*vcpu
);
116 static const struct vgic_ops
*vgic_ops
;
117 static const struct vgic_params
*vgic
;
119 static void add_sgi_source(struct kvm_vcpu
*vcpu
, int irq
, int source
)
121 vcpu
->kvm
->arch
.vgic
.vm_ops
.add_sgi_source(vcpu
, irq
, source
);
124 static bool queue_sgi(struct kvm_vcpu
*vcpu
, int irq
)
126 return vcpu
->kvm
->arch
.vgic
.vm_ops
.queue_sgi(vcpu
, irq
);
129 int kvm_vgic_map_resources(struct kvm
*kvm
)
131 return kvm
->arch
.vgic
.vm_ops
.map_resources(kvm
, vgic
);
135 * struct vgic_bitmap contains a bitmap made of unsigned longs, but
136 * extracts u32s out of them.
138 * This does not work on 64-bit BE systems, because the bitmap access
139 * will store two consecutive 32-bit words with the higher-addressed
140 * register's bits at the lower index and the lower-addressed register's
141 * bits at the higher index.
143 * Therefore, swizzle the register index when accessing the 32-bit word
144 * registers to access the right register's value.
146 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64
147 #define REG_OFFSET_SWIZZLE 1
149 #define REG_OFFSET_SWIZZLE 0
152 static int vgic_init_bitmap(struct vgic_bitmap
*b
, int nr_cpus
, int nr_irqs
)
156 nr_longs
= nr_cpus
+ BITS_TO_LONGS(nr_irqs
- VGIC_NR_PRIVATE_IRQS
);
158 b
->private = kzalloc(sizeof(unsigned long) * nr_longs
, GFP_KERNEL
);
162 b
->shared
= b
->private + nr_cpus
;
167 static void vgic_free_bitmap(struct vgic_bitmap
*b
)
175 * Call this function to convert a u64 value to an unsigned long * bitmask
176 * in a way that works on both 32-bit and 64-bit LE and BE platforms.
178 * Warning: Calling this function may modify *val.
180 static unsigned long *u64_to_bitmask(u64
*val
)
182 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32
183 *val
= (*val
>> 32) | (*val
<< 32);
185 return (unsigned long *)val
;
188 u32
*vgic_bitmap_get_reg(struct vgic_bitmap
*x
, int cpuid
, u32 offset
)
192 return (u32
*)(x
->private + cpuid
) + REG_OFFSET_SWIZZLE
;
194 return (u32
*)(x
->shared
) + ((offset
- 1) ^ REG_OFFSET_SWIZZLE
);
197 static int vgic_bitmap_get_irq_val(struct vgic_bitmap
*x
,
200 if (irq
< VGIC_NR_PRIVATE_IRQS
)
201 return test_bit(irq
, x
->private + cpuid
);
203 return test_bit(irq
- VGIC_NR_PRIVATE_IRQS
, x
->shared
);
206 void vgic_bitmap_set_irq_val(struct vgic_bitmap
*x
, int cpuid
,
211 if (irq
< VGIC_NR_PRIVATE_IRQS
) {
212 reg
= x
->private + cpuid
;
215 irq
-= VGIC_NR_PRIVATE_IRQS
;
224 static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap
*x
, int cpuid
)
226 return x
->private + cpuid
;
229 unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap
*x
)
234 static int vgic_init_bytemap(struct vgic_bytemap
*x
, int nr_cpus
, int nr_irqs
)
238 size
= nr_cpus
* VGIC_NR_PRIVATE_IRQS
;
239 size
+= nr_irqs
- VGIC_NR_PRIVATE_IRQS
;
241 x
->private = kzalloc(size
, GFP_KERNEL
);
245 x
->shared
= x
->private + nr_cpus
* VGIC_NR_PRIVATE_IRQS
/ sizeof(u32
);
249 static void vgic_free_bytemap(struct vgic_bytemap
*b
)
256 u32
*vgic_bytemap_get_reg(struct vgic_bytemap
*x
, int cpuid
, u32 offset
)
260 if (offset
< VGIC_NR_PRIVATE_IRQS
) {
262 offset
+= cpuid
* VGIC_NR_PRIVATE_IRQS
;
265 offset
-= VGIC_NR_PRIVATE_IRQS
;
268 return reg
+ (offset
/ sizeof(u32
));
271 #define VGIC_CFG_LEVEL 0
272 #define VGIC_CFG_EDGE 1
274 static bool vgic_irq_is_edge(struct kvm_vcpu
*vcpu
, int irq
)
276 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
279 irq_val
= vgic_bitmap_get_irq_val(&dist
->irq_cfg
, vcpu
->vcpu_id
, irq
);
280 return irq_val
== VGIC_CFG_EDGE
;
283 static int vgic_irq_is_enabled(struct kvm_vcpu
*vcpu
, int irq
)
285 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
287 return vgic_bitmap_get_irq_val(&dist
->irq_enabled
, vcpu
->vcpu_id
, irq
);
290 static int vgic_irq_is_queued(struct kvm_vcpu
*vcpu
, int irq
)
292 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
294 return vgic_bitmap_get_irq_val(&dist
->irq_queued
, vcpu
->vcpu_id
, irq
);
297 static int vgic_irq_is_active(struct kvm_vcpu
*vcpu
, int irq
)
299 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
301 return vgic_bitmap_get_irq_val(&dist
->irq_active
, vcpu
->vcpu_id
, irq
);
304 static void vgic_irq_set_queued(struct kvm_vcpu
*vcpu
, int irq
)
306 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
308 vgic_bitmap_set_irq_val(&dist
->irq_queued
, vcpu
->vcpu_id
, irq
, 1);
311 static void vgic_irq_clear_queued(struct kvm_vcpu
*vcpu
, int irq
)
313 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
315 vgic_bitmap_set_irq_val(&dist
->irq_queued
, vcpu
->vcpu_id
, irq
, 0);
318 static void vgic_irq_set_active(struct kvm_vcpu
*vcpu
, int irq
)
320 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
322 vgic_bitmap_set_irq_val(&dist
->irq_active
, vcpu
->vcpu_id
, irq
, 1);
325 static void vgic_irq_clear_active(struct kvm_vcpu
*vcpu
, int irq
)
327 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
329 vgic_bitmap_set_irq_val(&dist
->irq_active
, vcpu
->vcpu_id
, irq
, 0);
332 static int vgic_dist_irq_get_level(struct kvm_vcpu
*vcpu
, int irq
)
334 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
336 return vgic_bitmap_get_irq_val(&dist
->irq_level
, vcpu
->vcpu_id
, irq
);
339 static void vgic_dist_irq_set_level(struct kvm_vcpu
*vcpu
, int irq
)
341 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
343 vgic_bitmap_set_irq_val(&dist
->irq_level
, vcpu
->vcpu_id
, irq
, 1);
346 static void vgic_dist_irq_clear_level(struct kvm_vcpu
*vcpu
, int irq
)
348 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
350 vgic_bitmap_set_irq_val(&dist
->irq_level
, vcpu
->vcpu_id
, irq
, 0);
353 static int vgic_dist_irq_soft_pend(struct kvm_vcpu
*vcpu
, int irq
)
355 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
357 return vgic_bitmap_get_irq_val(&dist
->irq_soft_pend
, vcpu
->vcpu_id
, irq
);
360 static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu
*vcpu
, int irq
)
362 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
364 vgic_bitmap_set_irq_val(&dist
->irq_soft_pend
, vcpu
->vcpu_id
, irq
, 0);
365 if (!vgic_dist_irq_get_level(vcpu
, irq
)) {
366 vgic_dist_irq_clear_pending(vcpu
, irq
);
367 if (!compute_pending_for_cpu(vcpu
))
368 clear_bit(vcpu
->vcpu_id
, dist
->irq_pending_on_cpu
);
372 static int vgic_dist_irq_is_pending(struct kvm_vcpu
*vcpu
, int irq
)
374 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
376 return vgic_bitmap_get_irq_val(&dist
->irq_pending
, vcpu
->vcpu_id
, irq
);
379 void vgic_dist_irq_set_pending(struct kvm_vcpu
*vcpu
, int irq
)
381 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
383 vgic_bitmap_set_irq_val(&dist
->irq_pending
, vcpu
->vcpu_id
, irq
, 1);
386 void vgic_dist_irq_clear_pending(struct kvm_vcpu
*vcpu
, int irq
)
388 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
390 vgic_bitmap_set_irq_val(&dist
->irq_pending
, vcpu
->vcpu_id
, irq
, 0);
393 static void vgic_cpu_irq_set(struct kvm_vcpu
*vcpu
, int irq
)
395 if (irq
< VGIC_NR_PRIVATE_IRQS
)
396 set_bit(irq
, vcpu
->arch
.vgic_cpu
.pending_percpu
);
398 set_bit(irq
- VGIC_NR_PRIVATE_IRQS
,
399 vcpu
->arch
.vgic_cpu
.pending_shared
);
402 void vgic_cpu_irq_clear(struct kvm_vcpu
*vcpu
, int irq
)
404 if (irq
< VGIC_NR_PRIVATE_IRQS
)
405 clear_bit(irq
, vcpu
->arch
.vgic_cpu
.pending_percpu
);
407 clear_bit(irq
- VGIC_NR_PRIVATE_IRQS
,
408 vcpu
->arch
.vgic_cpu
.pending_shared
);
411 static bool vgic_can_sample_irq(struct kvm_vcpu
*vcpu
, int irq
)
413 return !vgic_irq_is_queued(vcpu
, irq
);
417 * vgic_reg_access - access vgic register
418 * @mmio: pointer to the data describing the mmio access
419 * @reg: pointer to the virtual backing of vgic distributor data
420 * @offset: least significant 2 bits used for word offset
421 * @mode: ACCESS_ mode (see defines above)
423 * Helper to make vgic register access easier using one of the access
424 * modes defined for vgic register access
425 * (read,raz,write-ignored,setbit,clearbit,write)
427 void vgic_reg_access(struct kvm_exit_mmio
*mmio
, u32
*reg
,
428 phys_addr_t offset
, int mode
)
430 int word_offset
= (offset
& 3) * 8;
431 u32 mask
= (1UL << (mmio
->len
* 8)) - 1;
435 * Any alignment fault should have been delivered to the guest
436 * directly (ARM ARM B3.12.7 "Prioritization of aborts").
442 BUG_ON(mode
!= (ACCESS_READ_RAZ
| ACCESS_WRITE_IGNORED
));
446 if (mmio
->is_write
) {
447 u32 data
= mmio_data_read(mmio
, mask
) << word_offset
;
448 switch (ACCESS_WRITE_MASK(mode
)) {
449 case ACCESS_WRITE_IGNORED
:
452 case ACCESS_WRITE_SETBIT
:
456 case ACCESS_WRITE_CLEARBIT
:
460 case ACCESS_WRITE_VALUE
:
461 regval
= (regval
& ~(mask
<< word_offset
)) | data
;
466 switch (ACCESS_READ_MASK(mode
)) {
467 case ACCESS_READ_RAZ
:
471 case ACCESS_READ_VALUE
:
472 mmio_data_write(mmio
, mask
, regval
>> word_offset
);
477 bool handle_mmio_raz_wi(struct kvm_vcpu
*vcpu
, struct kvm_exit_mmio
*mmio
,
480 vgic_reg_access(mmio
, NULL
, offset
,
481 ACCESS_READ_RAZ
| ACCESS_WRITE_IGNORED
);
485 bool vgic_handle_enable_reg(struct kvm
*kvm
, struct kvm_exit_mmio
*mmio
,
486 phys_addr_t offset
, int vcpu_id
, int access
)
489 int mode
= ACCESS_READ_VALUE
| access
;
490 struct kvm_vcpu
*target_vcpu
= kvm_get_vcpu(kvm
, vcpu_id
);
492 reg
= vgic_bitmap_get_reg(&kvm
->arch
.vgic
.irq_enabled
, vcpu_id
, offset
);
493 vgic_reg_access(mmio
, reg
, offset
, mode
);
494 if (mmio
->is_write
) {
495 if (access
& ACCESS_WRITE_CLEARBIT
) {
496 if (offset
< 4) /* Force SGI enabled */
498 vgic_retire_disabled_irqs(target_vcpu
);
500 vgic_update_state(kvm
);
507 bool vgic_handle_set_pending_reg(struct kvm
*kvm
,
508 struct kvm_exit_mmio
*mmio
,
509 phys_addr_t offset
, int vcpu_id
)
513 int mode
= ACCESS_READ_VALUE
| ACCESS_WRITE_SETBIT
;
514 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
516 reg
= vgic_bitmap_get_reg(&dist
->irq_cfg
, vcpu_id
, offset
);
517 level_mask
= (~(*reg
));
519 /* Mark both level and edge triggered irqs as pending */
520 reg
= vgic_bitmap_get_reg(&dist
->irq_pending
, vcpu_id
, offset
);
522 vgic_reg_access(mmio
, reg
, offset
, mode
);
524 if (mmio
->is_write
) {
525 /* Set the soft-pending flag only for level-triggered irqs */
526 reg
= vgic_bitmap_get_reg(&dist
->irq_soft_pend
,
528 vgic_reg_access(mmio
, reg
, offset
, mode
);
531 /* Ignore writes to SGIs */
534 *reg
|= orig
& 0xffff;
537 vgic_update_state(kvm
);
544 bool vgic_handle_clear_pending_reg(struct kvm
*kvm
,
545 struct kvm_exit_mmio
*mmio
,
546 phys_addr_t offset
, int vcpu_id
)
550 int mode
= ACCESS_READ_VALUE
| ACCESS_WRITE_CLEARBIT
;
551 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
553 reg
= vgic_bitmap_get_reg(&dist
->irq_pending
, vcpu_id
, offset
);
555 vgic_reg_access(mmio
, reg
, offset
, mode
);
556 if (mmio
->is_write
) {
557 /* Re-set level triggered level-active interrupts */
558 level_active
= vgic_bitmap_get_reg(&dist
->irq_level
,
560 reg
= vgic_bitmap_get_reg(&dist
->irq_pending
, vcpu_id
, offset
);
561 *reg
|= *level_active
;
563 /* Ignore writes to SGIs */
566 *reg
|= orig
& 0xffff;
569 /* Clear soft-pending flags */
570 reg
= vgic_bitmap_get_reg(&dist
->irq_soft_pend
,
572 vgic_reg_access(mmio
, reg
, offset
, mode
);
574 vgic_update_state(kvm
);
580 bool vgic_handle_set_active_reg(struct kvm
*kvm
,
581 struct kvm_exit_mmio
*mmio
,
582 phys_addr_t offset
, int vcpu_id
)
585 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
587 reg
= vgic_bitmap_get_reg(&dist
->irq_active
, vcpu_id
, offset
);
588 vgic_reg_access(mmio
, reg
, offset
,
589 ACCESS_READ_VALUE
| ACCESS_WRITE_SETBIT
);
591 if (mmio
->is_write
) {
592 vgic_update_state(kvm
);
599 bool vgic_handle_clear_active_reg(struct kvm
*kvm
,
600 struct kvm_exit_mmio
*mmio
,
601 phys_addr_t offset
, int vcpu_id
)
604 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
606 reg
= vgic_bitmap_get_reg(&dist
->irq_active
, vcpu_id
, offset
);
607 vgic_reg_access(mmio
, reg
, offset
,
608 ACCESS_READ_VALUE
| ACCESS_WRITE_CLEARBIT
);
610 if (mmio
->is_write
) {
611 vgic_update_state(kvm
);
618 static u32
vgic_cfg_expand(u16 val
)
624 * Turn a 16bit value like abcd...mnop into a 32bit word
625 * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
627 for (i
= 0; i
< 16; i
++)
628 res
|= ((val
>> i
) & VGIC_CFG_EDGE
) << (2 * i
+ 1);
633 static u16
vgic_cfg_compress(u32 val
)
639 * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
640 * abcd...mnop which is what we really care about.
642 for (i
= 0; i
< 16; i
++)
643 res
|= ((val
>> (i
* 2 + 1)) & VGIC_CFG_EDGE
) << i
;
649 * The distributor uses 2 bits per IRQ for the CFG register, but the
650 * LSB is always 0. As such, we only keep the upper bit, and use the
651 * two above functions to compress/expand the bits
653 bool vgic_handle_cfg_reg(u32
*reg
, struct kvm_exit_mmio
*mmio
,
663 val
= vgic_cfg_expand(val
);
664 vgic_reg_access(mmio
, &val
, offset
,
665 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
666 if (mmio
->is_write
) {
667 /* Ignore writes to read-only SGI and PPI bits */
671 val
= vgic_cfg_compress(val
);
676 *reg
&= 0xffff << 16;
685 * vgic_unqueue_irqs - move pending/active IRQs from LRs to the distributor
686 * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs
688 * Move any IRQs that have already been assigned to LRs back to the
689 * emulated distributor state so that the complete emulated state can be read
690 * from the main emulation structures without investigating the LRs.
692 void vgic_unqueue_irqs(struct kvm_vcpu
*vcpu
)
694 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
695 u64 elrsr
= vgic_get_elrsr(vcpu
);
696 unsigned long *elrsr_ptr
= u64_to_bitmask(&elrsr
);
699 for_each_clear_bit(i
, elrsr_ptr
, vgic_cpu
->nr_lr
) {
700 struct vgic_lr lr
= vgic_get_lr(vcpu
, i
);
703 * There are three options for the state bits:
707 * 11: pending and active
709 BUG_ON(!(lr
.state
& LR_STATE_MASK
));
711 /* Reestablish SGI source for pending and active IRQs */
712 if (lr
.irq
< VGIC_NR_SGIS
)
713 add_sgi_source(vcpu
, lr
.irq
, lr
.source
);
716 * If the LR holds an active (10) or a pending and active (11)
717 * interrupt then move the active state to the
718 * distributor tracking bit.
720 if (lr
.state
& LR_STATE_ACTIVE
)
721 vgic_irq_set_active(vcpu
, lr
.irq
);
724 * Reestablish the pending state on the distributor and the
725 * CPU interface and mark the LR as free for other use.
727 vgic_retire_lr(i
, vcpu
);
729 /* Finally update the VGIC state. */
730 vgic_update_state(vcpu
->kvm
);
735 struct vgic_io_range
*vgic_find_range(const struct vgic_io_range
*ranges
,
736 int len
, gpa_t offset
)
738 while (ranges
->len
) {
739 if (offset
>= ranges
->base
&&
740 (offset
+ len
) <= (ranges
->base
+ ranges
->len
))
748 static bool vgic_validate_access(const struct vgic_dist
*dist
,
749 const struct vgic_io_range
*range
,
750 unsigned long offset
)
754 if (!range
->bits_per_irq
)
755 return true; /* Not an irq-based access */
757 irq
= offset
* 8 / range
->bits_per_irq
;
758 if (irq
>= dist
->nr_irqs
)
765 * Call the respective handler function for the given range.
766 * We split up any 64 bit accesses into two consecutive 32 bit
767 * handler calls and merge the result afterwards.
768 * We do this in a little endian fashion regardless of the host's
769 * or guest's endianness, because the GIC is always LE and the rest of
770 * the code (vgic_reg_access) also puts it in a LE fashion already.
771 * At this point we have already identified the handle function, so
772 * range points to that one entry and offset is relative to this.
774 static bool call_range_handler(struct kvm_vcpu
*vcpu
,
775 struct kvm_exit_mmio
*mmio
,
776 unsigned long offset
,
777 const struct vgic_io_range
*range
)
779 struct kvm_exit_mmio mmio32
;
782 if (likely(mmio
->len
<= 4))
783 return range
->handle_mmio(vcpu
, mmio
, offset
);
786 * Any access bigger than 4 bytes (that we currently handle in KVM)
787 * is actually 8 bytes long, caused by a 64-bit access
791 mmio32
.is_write
= mmio
->is_write
;
792 mmio32
.private = mmio
->private;
794 mmio32
.phys_addr
= mmio
->phys_addr
+ 4;
795 mmio32
.data
= &((u32
*)mmio
->data
)[1];
796 ret
= range
->handle_mmio(vcpu
, &mmio32
, offset
+ 4);
798 mmio32
.phys_addr
= mmio
->phys_addr
;
799 mmio32
.data
= &((u32
*)mmio
->data
)[0];
800 ret
|= range
->handle_mmio(vcpu
, &mmio32
, offset
);
806 * vgic_handle_mmio_access - handle an in-kernel MMIO access
807 * This is called by the read/write KVM IO device wrappers below.
808 * @vcpu: pointer to the vcpu performing the access
809 * @this: pointer to the KVM IO device in charge
810 * @addr: guest physical address of the access
811 * @len: size of the access
812 * @val: pointer to the data region
813 * @is_write: read or write access
815 * returns true if the MMIO access could be performed
817 static int vgic_handle_mmio_access(struct kvm_vcpu
*vcpu
,
818 struct kvm_io_device
*this, gpa_t addr
,
819 int len
, void *val
, bool is_write
)
821 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
822 struct vgic_io_device
*iodev
= container_of(this,
823 struct vgic_io_device
, dev
);
824 struct kvm_run
*run
= vcpu
->run
;
825 const struct vgic_io_range
*range
;
826 struct kvm_exit_mmio mmio
;
830 offset
= addr
- iodev
->addr
;
831 range
= vgic_find_range(iodev
->reg_ranges
, len
, offset
);
832 if (unlikely(!range
|| !range
->handle_mmio
)) {
833 pr_warn("Unhandled access %d %08llx %d\n", is_write
, addr
, len
);
837 mmio
.phys_addr
= addr
;
839 mmio
.is_write
= is_write
;
841 mmio
.private = iodev
->redist_vcpu
;
843 spin_lock(&dist
->lock
);
844 offset
-= range
->base
;
845 if (vgic_validate_access(dist
, range
, offset
)) {
846 updated_state
= call_range_handler(vcpu
, &mmio
, offset
, range
);
850 updated_state
= false;
852 spin_unlock(&dist
->lock
);
853 run
->mmio
.is_write
= is_write
;
855 run
->mmio
.phys_addr
= addr
;
856 memcpy(run
->mmio
.data
, val
, len
);
858 kvm_handle_mmio_return(vcpu
, run
);
861 vgic_kick_vcpus(vcpu
->kvm
);
866 static int vgic_handle_mmio_read(struct kvm_vcpu
*vcpu
,
867 struct kvm_io_device
*this,
868 gpa_t addr
, int len
, void *val
)
870 return vgic_handle_mmio_access(vcpu
, this, addr
, len
, val
, false);
873 static int vgic_handle_mmio_write(struct kvm_vcpu
*vcpu
,
874 struct kvm_io_device
*this,
875 gpa_t addr
, int len
, const void *val
)
877 return vgic_handle_mmio_access(vcpu
, this, addr
, len
, (void *)val
,
881 struct kvm_io_device_ops vgic_io_ops
= {
882 .read
= vgic_handle_mmio_read
,
883 .write
= vgic_handle_mmio_write
,
887 * vgic_register_kvm_io_dev - register VGIC register frame on the KVM I/O bus
888 * @kvm: The VM structure pointer
889 * @base: The (guest) base address for the register frame
890 * @len: Length of the register frame window
891 * @ranges: Describing the handler functions for each register
892 * @redist_vcpu_id: The VCPU ID to pass on to the handlers on call
893 * @iodev: Points to memory to be passed on to the handler
895 * @iodev stores the parameters of this function to be usable by the handler
896 * respectively the dispatcher function (since the KVM I/O bus framework lacks
897 * an opaque parameter). Initialization is done in this function, but the
898 * reference should be valid and unique for the whole VGIC lifetime.
899 * If the register frame is not mapped for a specific VCPU, pass -1 to
902 int vgic_register_kvm_io_dev(struct kvm
*kvm
, gpa_t base
, int len
,
903 const struct vgic_io_range
*ranges
,
905 struct vgic_io_device
*iodev
)
907 struct kvm_vcpu
*vcpu
= NULL
;
910 if (redist_vcpu_id
>= 0)
911 vcpu
= kvm_get_vcpu(kvm
, redist_vcpu_id
);
915 iodev
->reg_ranges
= ranges
;
916 iodev
->redist_vcpu
= vcpu
;
918 kvm_iodevice_init(&iodev
->dev
, &vgic_io_ops
);
920 mutex_lock(&kvm
->slots_lock
);
922 ret
= kvm_io_bus_register_dev(kvm
, KVM_MMIO_BUS
, base
, len
,
924 mutex_unlock(&kvm
->slots_lock
);
926 /* Mark the iodev as invalid if registration fails. */
928 iodev
->dev
.ops
= NULL
;
933 static int vgic_nr_shared_irqs(struct vgic_dist
*dist
)
935 return dist
->nr_irqs
- VGIC_NR_PRIVATE_IRQS
;
938 static int compute_active_for_cpu(struct kvm_vcpu
*vcpu
)
940 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
941 unsigned long *active
, *enabled
, *act_percpu
, *act_shared
;
942 unsigned long active_private
, active_shared
;
943 int nr_shared
= vgic_nr_shared_irqs(dist
);
946 vcpu_id
= vcpu
->vcpu_id
;
947 act_percpu
= vcpu
->arch
.vgic_cpu
.active_percpu
;
948 act_shared
= vcpu
->arch
.vgic_cpu
.active_shared
;
950 active
= vgic_bitmap_get_cpu_map(&dist
->irq_active
, vcpu_id
);
951 enabled
= vgic_bitmap_get_cpu_map(&dist
->irq_enabled
, vcpu_id
);
952 bitmap_and(act_percpu
, active
, enabled
, VGIC_NR_PRIVATE_IRQS
);
954 active
= vgic_bitmap_get_shared_map(&dist
->irq_active
);
955 enabled
= vgic_bitmap_get_shared_map(&dist
->irq_enabled
);
956 bitmap_and(act_shared
, active
, enabled
, nr_shared
);
957 bitmap_and(act_shared
, act_shared
,
958 vgic_bitmap_get_shared_map(&dist
->irq_spi_target
[vcpu_id
]),
961 active_private
= find_first_bit(act_percpu
, VGIC_NR_PRIVATE_IRQS
);
962 active_shared
= find_first_bit(act_shared
, nr_shared
);
964 return (active_private
< VGIC_NR_PRIVATE_IRQS
||
965 active_shared
< nr_shared
);
968 static int compute_pending_for_cpu(struct kvm_vcpu
*vcpu
)
970 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
971 unsigned long *pending
, *enabled
, *pend_percpu
, *pend_shared
;
972 unsigned long pending_private
, pending_shared
;
973 int nr_shared
= vgic_nr_shared_irqs(dist
);
976 vcpu_id
= vcpu
->vcpu_id
;
977 pend_percpu
= vcpu
->arch
.vgic_cpu
.pending_percpu
;
978 pend_shared
= vcpu
->arch
.vgic_cpu
.pending_shared
;
980 if (!dist
->enabled
) {
981 bitmap_zero(pend_percpu
, VGIC_NR_PRIVATE_IRQS
);
982 bitmap_zero(pend_shared
, nr_shared
);
986 pending
= vgic_bitmap_get_cpu_map(&dist
->irq_pending
, vcpu_id
);
987 enabled
= vgic_bitmap_get_cpu_map(&dist
->irq_enabled
, vcpu_id
);
988 bitmap_and(pend_percpu
, pending
, enabled
, VGIC_NR_PRIVATE_IRQS
);
990 pending
= vgic_bitmap_get_shared_map(&dist
->irq_pending
);
991 enabled
= vgic_bitmap_get_shared_map(&dist
->irq_enabled
);
992 bitmap_and(pend_shared
, pending
, enabled
, nr_shared
);
993 bitmap_and(pend_shared
, pend_shared
,
994 vgic_bitmap_get_shared_map(&dist
->irq_spi_target
[vcpu_id
]),
997 pending_private
= find_first_bit(pend_percpu
, VGIC_NR_PRIVATE_IRQS
);
998 pending_shared
= find_first_bit(pend_shared
, nr_shared
);
999 return (pending_private
< VGIC_NR_PRIVATE_IRQS
||
1000 pending_shared
< vgic_nr_shared_irqs(dist
));
1004 * Update the interrupt state and determine which CPUs have pending
1005 * or active interrupts. Must be called with distributor lock held.
1007 void vgic_update_state(struct kvm
*kvm
)
1009 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1010 struct kvm_vcpu
*vcpu
;
1013 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
1014 if (compute_pending_for_cpu(vcpu
))
1015 set_bit(c
, dist
->irq_pending_on_cpu
);
1017 if (compute_active_for_cpu(vcpu
))
1018 set_bit(c
, dist
->irq_active_on_cpu
);
1020 clear_bit(c
, dist
->irq_active_on_cpu
);
1024 static struct vgic_lr
vgic_get_lr(const struct kvm_vcpu
*vcpu
, int lr
)
1026 return vgic_ops
->get_lr(vcpu
, lr
);
1029 static void vgic_set_lr(struct kvm_vcpu
*vcpu
, int lr
,
1032 vgic_ops
->set_lr(vcpu
, lr
, vlr
);
1035 static inline u64
vgic_get_elrsr(struct kvm_vcpu
*vcpu
)
1037 return vgic_ops
->get_elrsr(vcpu
);
1040 static inline u64
vgic_get_eisr(struct kvm_vcpu
*vcpu
)
1042 return vgic_ops
->get_eisr(vcpu
);
1045 static inline void vgic_clear_eisr(struct kvm_vcpu
*vcpu
)
1047 vgic_ops
->clear_eisr(vcpu
);
1050 static inline u32
vgic_get_interrupt_status(struct kvm_vcpu
*vcpu
)
1052 return vgic_ops
->get_interrupt_status(vcpu
);
1055 static inline void vgic_enable_underflow(struct kvm_vcpu
*vcpu
)
1057 vgic_ops
->enable_underflow(vcpu
);
1060 static inline void vgic_disable_underflow(struct kvm_vcpu
*vcpu
)
1062 vgic_ops
->disable_underflow(vcpu
);
1065 void vgic_get_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
)
1067 vgic_ops
->get_vmcr(vcpu
, vmcr
);
1070 void vgic_set_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
)
1072 vgic_ops
->set_vmcr(vcpu
, vmcr
);
1075 static inline void vgic_enable(struct kvm_vcpu
*vcpu
)
1077 vgic_ops
->enable(vcpu
);
1080 static void vgic_retire_lr(int lr_nr
, struct kvm_vcpu
*vcpu
)
1082 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr_nr
);
1084 vgic_irq_clear_queued(vcpu
, vlr
.irq
);
1087 * We must transfer the pending state back to the distributor before
1088 * retiring the LR, otherwise we may loose edge-triggered interrupts.
1090 if (vlr
.state
& LR_STATE_PENDING
) {
1091 vgic_dist_irq_set_pending(vcpu
, vlr
.irq
);
1096 vgic_set_lr(vcpu
, lr_nr
, vlr
);
1100 * An interrupt may have been disabled after being made pending on the
1101 * CPU interface (the classic case is a timer running while we're
1102 * rebooting the guest - the interrupt would kick as soon as the CPU
1103 * interface gets enabled, with deadly consequences).
1105 * The solution is to examine already active LRs, and check the
1106 * interrupt is still enabled. If not, just retire it.
1108 static void vgic_retire_disabled_irqs(struct kvm_vcpu
*vcpu
)
1110 u64 elrsr
= vgic_get_elrsr(vcpu
);
1111 unsigned long *elrsr_ptr
= u64_to_bitmask(&elrsr
);
1114 for_each_clear_bit(lr
, elrsr_ptr
, vgic
->nr_lr
) {
1115 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr
);
1117 if (!vgic_irq_is_enabled(vcpu
, vlr
.irq
))
1118 vgic_retire_lr(lr
, vcpu
);
1122 static void vgic_queue_irq_to_lr(struct kvm_vcpu
*vcpu
, int irq
,
1123 int lr_nr
, struct vgic_lr vlr
)
1125 if (vgic_irq_is_active(vcpu
, irq
)) {
1126 vlr
.state
|= LR_STATE_ACTIVE
;
1127 kvm_debug("Set active, clear distributor: 0x%x\n", vlr
.state
);
1128 vgic_irq_clear_active(vcpu
, irq
);
1129 vgic_update_state(vcpu
->kvm
);
1131 WARN_ON(!vgic_dist_irq_is_pending(vcpu
, irq
));
1132 vlr
.state
|= LR_STATE_PENDING
;
1133 kvm_debug("Set pending: 0x%x\n", vlr
.state
);
1136 if (!vgic_irq_is_edge(vcpu
, irq
))
1137 vlr
.state
|= LR_EOI_INT
;
1139 if (vlr
.irq
>= VGIC_NR_SGIS
) {
1140 struct irq_phys_map
*map
;
1141 map
= vgic_irq_map_search(vcpu
, irq
);
1144 vlr
.hwirq
= map
->phys_irq
;
1146 vlr
.state
&= ~LR_EOI_INT
;
1149 * Make sure we're not going to sample this
1150 * again, as a HW-backed interrupt cannot be
1151 * in the PENDING_ACTIVE stage.
1153 vgic_irq_set_queued(vcpu
, irq
);
1157 vgic_set_lr(vcpu
, lr_nr
, vlr
);
1161 * Queue an interrupt to a CPU virtual interface. Return true on success,
1162 * or false if it wasn't possible to queue it.
1163 * sgi_source must be zero for any non-SGI interrupts.
1165 bool vgic_queue_irq(struct kvm_vcpu
*vcpu
, u8 sgi_source_id
, int irq
)
1167 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1168 u64 elrsr
= vgic_get_elrsr(vcpu
);
1169 unsigned long *elrsr_ptr
= u64_to_bitmask(&elrsr
);
1173 /* Sanitize the input... */
1174 BUG_ON(sgi_source_id
& ~7);
1175 BUG_ON(sgi_source_id
&& irq
>= VGIC_NR_SGIS
);
1176 BUG_ON(irq
>= dist
->nr_irqs
);
1178 kvm_debug("Queue IRQ%d\n", irq
);
1180 /* Do we have an active interrupt for the same CPUID? */
1181 for_each_clear_bit(lr
, elrsr_ptr
, vgic
->nr_lr
) {
1182 vlr
= vgic_get_lr(vcpu
, lr
);
1183 if (vlr
.irq
== irq
&& vlr
.source
== sgi_source_id
) {
1184 kvm_debug("LR%d piggyback for IRQ%d\n", lr
, vlr
.irq
);
1185 vgic_queue_irq_to_lr(vcpu
, irq
, lr
, vlr
);
1190 /* Try to use another LR for this interrupt */
1191 lr
= find_first_bit(elrsr_ptr
, vgic
->nr_lr
);
1192 if (lr
>= vgic
->nr_lr
)
1195 kvm_debug("LR%d allocated for IRQ%d %x\n", lr
, irq
, sgi_source_id
);
1198 vlr
.source
= sgi_source_id
;
1200 vgic_queue_irq_to_lr(vcpu
, irq
, lr
, vlr
);
1205 static bool vgic_queue_hwirq(struct kvm_vcpu
*vcpu
, int irq
)
1207 if (!vgic_can_sample_irq(vcpu
, irq
))
1208 return true; /* level interrupt, already queued */
1210 if (vgic_queue_irq(vcpu
, 0, irq
)) {
1211 if (vgic_irq_is_edge(vcpu
, irq
)) {
1212 vgic_dist_irq_clear_pending(vcpu
, irq
);
1213 vgic_cpu_irq_clear(vcpu
, irq
);
1215 vgic_irq_set_queued(vcpu
, irq
);
1225 * Fill the list registers with pending interrupts before running the
1228 static void __kvm_vgic_flush_hwstate(struct kvm_vcpu
*vcpu
)
1230 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1231 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1232 unsigned long *pa_percpu
, *pa_shared
;
1235 int nr_shared
= vgic_nr_shared_irqs(dist
);
1237 vcpu_id
= vcpu
->vcpu_id
;
1239 pa_percpu
= vcpu
->arch
.vgic_cpu
.pend_act_percpu
;
1240 pa_shared
= vcpu
->arch
.vgic_cpu
.pend_act_shared
;
1242 bitmap_or(pa_percpu
, vgic_cpu
->pending_percpu
, vgic_cpu
->active_percpu
,
1243 VGIC_NR_PRIVATE_IRQS
);
1244 bitmap_or(pa_shared
, vgic_cpu
->pending_shared
, vgic_cpu
->active_shared
,
1247 * We may not have any pending interrupt, or the interrupts
1248 * may have been serviced from another vcpu. In all cases,
1251 if (!kvm_vgic_vcpu_pending_irq(vcpu
) && !kvm_vgic_vcpu_active_irq(vcpu
))
1255 for_each_set_bit(i
, pa_percpu
, VGIC_NR_SGIS
) {
1256 if (!queue_sgi(vcpu
, i
))
1261 for_each_set_bit_from(i
, pa_percpu
, VGIC_NR_PRIVATE_IRQS
) {
1262 if (!vgic_queue_hwirq(vcpu
, i
))
1267 for_each_set_bit(i
, pa_shared
, nr_shared
) {
1268 if (!vgic_queue_hwirq(vcpu
, i
+ VGIC_NR_PRIVATE_IRQS
))
1277 vgic_enable_underflow(vcpu
);
1279 vgic_disable_underflow(vcpu
);
1281 * We're about to run this VCPU, and we've consumed
1282 * everything the distributor had in store for
1283 * us. Claim we don't have anything pending. We'll
1284 * adjust that if needed while exiting.
1286 clear_bit(vcpu_id
, dist
->irq_pending_on_cpu
);
1290 static int process_queued_irq(struct kvm_vcpu
*vcpu
,
1291 int lr
, struct vgic_lr vlr
)
1296 * If the IRQ was EOIed (called from vgic_process_maintenance) or it
1297 * went from active to non-active (called from vgic_sync_hwirq) it was
1298 * also ACKed and we we therefore assume we can clear the soft pending
1299 * state (should it had been set) for this interrupt.
1301 * Note: if the IRQ soft pending state was set after the IRQ was
1302 * acked, it actually shouldn't be cleared, but we have no way of
1303 * knowing that unless we start trapping ACKs when the soft-pending
1306 vgic_dist_irq_clear_soft_pend(vcpu
, vlr
.irq
);
1309 * Tell the gic to start sampling this interrupt again.
1311 vgic_irq_clear_queued(vcpu
, vlr
.irq
);
1313 /* Any additional pending interrupt? */
1314 if (vgic_irq_is_edge(vcpu
, vlr
.irq
)) {
1315 BUG_ON(!(vlr
.state
& LR_HW
));
1316 pending
= vgic_dist_irq_is_pending(vcpu
, vlr
.irq
);
1318 if (vgic_dist_irq_get_level(vcpu
, vlr
.irq
)) {
1319 vgic_cpu_irq_set(vcpu
, vlr
.irq
);
1322 vgic_dist_irq_clear_pending(vcpu
, vlr
.irq
);
1323 vgic_cpu_irq_clear(vcpu
, vlr
.irq
);
1328 * Despite being EOIed, the LR may not have
1329 * been marked as empty.
1333 vgic_set_lr(vcpu
, lr
, vlr
);
1338 static bool vgic_process_maintenance(struct kvm_vcpu
*vcpu
)
1340 u32 status
= vgic_get_interrupt_status(vcpu
);
1341 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1342 struct kvm
*kvm
= vcpu
->kvm
;
1343 int level_pending
= 0;
1345 kvm_debug("STATUS = %08x\n", status
);
1347 if (status
& INT_STATUS_EOI
) {
1349 * Some level interrupts have been EOIed. Clear their
1352 u64 eisr
= vgic_get_eisr(vcpu
);
1353 unsigned long *eisr_ptr
= u64_to_bitmask(&eisr
);
1356 for_each_set_bit(lr
, eisr_ptr
, vgic
->nr_lr
) {
1357 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr
);
1359 WARN_ON(vgic_irq_is_edge(vcpu
, vlr
.irq
));
1360 WARN_ON(vlr
.state
& LR_STATE_MASK
);
1364 * kvm_notify_acked_irq calls kvm_set_irq()
1365 * to reset the IRQ level, which grabs the dist->lock
1366 * so we call this before taking the dist->lock.
1368 kvm_notify_acked_irq(kvm
, 0,
1369 vlr
.irq
- VGIC_NR_PRIVATE_IRQS
);
1371 spin_lock(&dist
->lock
);
1372 level_pending
|= process_queued_irq(vcpu
, lr
, vlr
);
1373 spin_unlock(&dist
->lock
);
1377 if (status
& INT_STATUS_UNDERFLOW
)
1378 vgic_disable_underflow(vcpu
);
1381 * In the next iterations of the vcpu loop, if we sync the vgic state
1382 * after flushing it, but before entering the guest (this happens for
1383 * pending signals and vmid rollovers), then make sure we don't pick
1384 * up any old maintenance interrupts here.
1386 vgic_clear_eisr(vcpu
);
1388 return level_pending
;
1392 * Save the physical active state, and reset it to inactive.
1394 * Return true if there's a pending forwarded interrupt to queue.
1396 static bool vgic_sync_hwirq(struct kvm_vcpu
*vcpu
, int lr
, struct vgic_lr vlr
)
1398 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1399 struct irq_phys_map
*map
;
1404 if (!(vlr
.state
& LR_HW
))
1407 map
= vgic_irq_map_search(vcpu
, vlr
.irq
);
1410 ret
= irq_get_irqchip_state(map
->irq
,
1411 IRQCHIP_STATE_ACTIVE
,
1419 spin_lock(&dist
->lock
);
1420 level_pending
= process_queued_irq(vcpu
, lr
, vlr
);
1421 spin_unlock(&dist
->lock
);
1422 return level_pending
;
1425 /* Sync back the VGIC state after a guest run */
1426 static void __kvm_vgic_sync_hwstate(struct kvm_vcpu
*vcpu
)
1428 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1430 unsigned long *elrsr_ptr
;
1434 level_pending
= vgic_process_maintenance(vcpu
);
1436 /* Deal with HW interrupts, and clear mappings for empty LRs */
1437 for (lr
= 0; lr
< vgic
->nr_lr
; lr
++) {
1438 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr
);
1440 level_pending
|= vgic_sync_hwirq(vcpu
, lr
, vlr
);
1441 BUG_ON(vlr
.irq
>= dist
->nr_irqs
);
1444 /* Check if we still have something up our sleeve... */
1445 elrsr
= vgic_get_elrsr(vcpu
);
1446 elrsr_ptr
= u64_to_bitmask(&elrsr
);
1447 pending
= find_first_zero_bit(elrsr_ptr
, vgic
->nr_lr
);
1448 if (level_pending
|| pending
< vgic
->nr_lr
)
1449 set_bit(vcpu
->vcpu_id
, dist
->irq_pending_on_cpu
);
1452 void kvm_vgic_flush_hwstate(struct kvm_vcpu
*vcpu
)
1454 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1456 if (!irqchip_in_kernel(vcpu
->kvm
))
1459 spin_lock(&dist
->lock
);
1460 __kvm_vgic_flush_hwstate(vcpu
);
1461 spin_unlock(&dist
->lock
);
1464 void kvm_vgic_sync_hwstate(struct kvm_vcpu
*vcpu
)
1466 if (!irqchip_in_kernel(vcpu
->kvm
))
1469 __kvm_vgic_sync_hwstate(vcpu
);
1472 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu
*vcpu
)
1474 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1476 if (!irqchip_in_kernel(vcpu
->kvm
))
1479 return test_bit(vcpu
->vcpu_id
, dist
->irq_pending_on_cpu
);
1482 int kvm_vgic_vcpu_active_irq(struct kvm_vcpu
*vcpu
)
1484 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1486 if (!irqchip_in_kernel(vcpu
->kvm
))
1489 return test_bit(vcpu
->vcpu_id
, dist
->irq_active_on_cpu
);
1493 void vgic_kick_vcpus(struct kvm
*kvm
)
1495 struct kvm_vcpu
*vcpu
;
1499 * We've injected an interrupt, time to find out who deserves
1502 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
1503 if (kvm_vgic_vcpu_pending_irq(vcpu
))
1504 kvm_vcpu_kick(vcpu
);
1508 static int vgic_validate_injection(struct kvm_vcpu
*vcpu
, int irq
, int level
)
1510 int edge_triggered
= vgic_irq_is_edge(vcpu
, irq
);
1513 * Only inject an interrupt if:
1514 * - edge triggered and we have a rising edge
1515 * - level triggered and we change level
1517 if (edge_triggered
) {
1518 int state
= vgic_dist_irq_is_pending(vcpu
, irq
);
1519 return level
> state
;
1521 int state
= vgic_dist_irq_get_level(vcpu
, irq
);
1522 return level
!= state
;
1526 static int vgic_update_irq_pending(struct kvm
*kvm
, int cpuid
,
1527 struct irq_phys_map
*map
,
1528 unsigned int irq_num
, bool level
)
1530 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1531 struct kvm_vcpu
*vcpu
;
1532 int edge_triggered
, level_triggered
;
1534 bool ret
= true, can_inject
= true;
1536 trace_vgic_update_irq_pending(cpuid
, irq_num
, level
);
1538 if (irq_num
>= min(kvm
->arch
.vgic
.nr_irqs
, 1020))
1541 spin_lock(&dist
->lock
);
1543 vcpu
= kvm_get_vcpu(kvm
, cpuid
);
1544 edge_triggered
= vgic_irq_is_edge(vcpu
, irq_num
);
1545 level_triggered
= !edge_triggered
;
1547 if (!vgic_validate_injection(vcpu
, irq_num
, level
)) {
1552 if (irq_num
>= VGIC_NR_PRIVATE_IRQS
) {
1553 cpuid
= dist
->irq_spi_cpu
[irq_num
- VGIC_NR_PRIVATE_IRQS
];
1554 if (cpuid
== VCPU_NOT_ALLOCATED
) {
1555 /* Pretend we use CPU0, and prevent injection */
1559 vcpu
= kvm_get_vcpu(kvm
, cpuid
);
1562 kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num
, level
, cpuid
);
1565 if (level_triggered
)
1566 vgic_dist_irq_set_level(vcpu
, irq_num
);
1567 vgic_dist_irq_set_pending(vcpu
, irq_num
);
1569 if (level_triggered
) {
1570 vgic_dist_irq_clear_level(vcpu
, irq_num
);
1571 if (!vgic_dist_irq_soft_pend(vcpu
, irq_num
)) {
1572 vgic_dist_irq_clear_pending(vcpu
, irq_num
);
1573 vgic_cpu_irq_clear(vcpu
, irq_num
);
1574 if (!compute_pending_for_cpu(vcpu
))
1575 clear_bit(cpuid
, dist
->irq_pending_on_cpu
);
1583 enabled
= vgic_irq_is_enabled(vcpu
, irq_num
);
1585 if (!enabled
|| !can_inject
) {
1590 if (!vgic_can_sample_irq(vcpu
, irq_num
)) {
1592 * Level interrupt in progress, will be picked up
1600 vgic_cpu_irq_set(vcpu
, irq_num
);
1601 set_bit(cpuid
, dist
->irq_pending_on_cpu
);
1605 spin_unlock(&dist
->lock
);
1608 /* kick the specified vcpu */
1609 kvm_vcpu_kick(kvm_get_vcpu(kvm
, cpuid
));
1615 static int vgic_lazy_init(struct kvm
*kvm
)
1619 if (unlikely(!vgic_initialized(kvm
))) {
1621 * We only provide the automatic initialization of the VGIC
1622 * for the legacy case of a GICv2. Any other type must
1623 * be explicitly initialized once setup with the respective
1626 if (kvm
->arch
.vgic
.vgic_model
!= KVM_DEV_TYPE_ARM_VGIC_V2
)
1629 mutex_lock(&kvm
->lock
);
1630 ret
= vgic_init(kvm
);
1631 mutex_unlock(&kvm
->lock
);
1638 * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
1639 * @kvm: The VM structure pointer
1640 * @cpuid: The CPU for PPIs
1641 * @irq_num: The IRQ number that is assigned to the device. This IRQ
1642 * must not be mapped to a HW interrupt.
1643 * @level: Edge-triggered: true: to trigger the interrupt
1644 * false: to ignore the call
1645 * Level-sensitive true: raise the input signal
1646 * false: lower the input signal
1648 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1649 * level-sensitive interrupts. You can think of the level parameter as 1
1650 * being HIGH and 0 being LOW and all devices being active-HIGH.
1652 int kvm_vgic_inject_irq(struct kvm
*kvm
, int cpuid
, unsigned int irq_num
,
1655 struct irq_phys_map
*map
;
1658 ret
= vgic_lazy_init(kvm
);
1662 map
= vgic_irq_map_search(kvm_get_vcpu(kvm
, cpuid
), irq_num
);
1666 return vgic_update_irq_pending(kvm
, cpuid
, NULL
, irq_num
, level
);
1670 * kvm_vgic_inject_mapped_irq - Inject a physically mapped IRQ to the vgic
1671 * @kvm: The VM structure pointer
1672 * @cpuid: The CPU for PPIs
1673 * @map: Pointer to a irq_phys_map structure describing the mapping
1674 * @level: Edge-triggered: true: to trigger the interrupt
1675 * false: to ignore the call
1676 * Level-sensitive true: raise the input signal
1677 * false: lower the input signal
1679 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1680 * level-sensitive interrupts. You can think of the level parameter as 1
1681 * being HIGH and 0 being LOW and all devices being active-HIGH.
1683 int kvm_vgic_inject_mapped_irq(struct kvm
*kvm
, int cpuid
,
1684 struct irq_phys_map
*map
, bool level
)
1688 ret
= vgic_lazy_init(kvm
);
1692 return vgic_update_irq_pending(kvm
, cpuid
, map
, map
->virt_irq
, level
);
1695 static irqreturn_t
vgic_maintenance_handler(int irq
, void *data
)
1698 * We cannot rely on the vgic maintenance interrupt to be
1699 * delivered synchronously. This means we can only use it to
1700 * exit the VM, and we perform the handling of EOIed
1701 * interrupts on the exit path (see vgic_process_maintenance).
1706 static struct list_head
*vgic_get_irq_phys_map_list(struct kvm_vcpu
*vcpu
,
1709 if (virt_irq
< VGIC_NR_PRIVATE_IRQS
)
1710 return &vcpu
->arch
.vgic_cpu
.irq_phys_map_list
;
1712 return &vcpu
->kvm
->arch
.vgic
.irq_phys_map_list
;
1716 * kvm_vgic_map_phys_irq - map a virtual IRQ to a physical IRQ
1717 * @vcpu: The VCPU pointer
1718 * @virt_irq: The virtual irq number
1719 * @irq: The Linux IRQ number
1721 * Establish a mapping between a guest visible irq (@virt_irq) and a
1722 * Linux irq (@irq). On injection, @virt_irq will be associated with
1723 * the physical interrupt represented by @irq. This mapping can be
1724 * established multiple times as long as the parameters are the same.
1726 * Returns a valid pointer on success, and an error pointer otherwise
1728 struct irq_phys_map
*kvm_vgic_map_phys_irq(struct kvm_vcpu
*vcpu
,
1729 int virt_irq
, int irq
)
1731 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1732 struct list_head
*root
= vgic_get_irq_phys_map_list(vcpu
, virt_irq
);
1733 struct irq_phys_map
*map
;
1734 struct irq_phys_map_entry
*entry
;
1735 struct irq_desc
*desc
;
1736 struct irq_data
*data
;
1739 desc
= irq_to_desc(irq
);
1741 kvm_err("%s: no interrupt descriptor\n", __func__
);
1742 return ERR_PTR(-EINVAL
);
1745 data
= irq_desc_get_irq_data(desc
);
1746 while (data
->parent_data
)
1747 data
= data
->parent_data
;
1749 phys_irq
= data
->hwirq
;
1751 /* Create a new mapping */
1752 entry
= kzalloc(sizeof(*entry
), GFP_KERNEL
);
1754 return ERR_PTR(-ENOMEM
);
1756 spin_lock(&dist
->irq_phys_map_lock
);
1758 /* Try to match an existing mapping */
1759 map
= vgic_irq_map_search(vcpu
, virt_irq
);
1761 /* Make sure this mapping matches */
1762 if (map
->phys_irq
!= phys_irq
||
1764 map
= ERR_PTR(-EINVAL
);
1766 /* Found an existing, valid mapping */
1771 map
->virt_irq
= virt_irq
;
1772 map
->phys_irq
= phys_irq
;
1775 list_add_tail_rcu(&entry
->entry
, root
);
1778 spin_unlock(&dist
->irq_phys_map_lock
);
1779 /* If we've found a hit in the existing list, free the useless
1781 if (IS_ERR(map
) || map
!= &entry
->map
)
1786 static struct irq_phys_map
*vgic_irq_map_search(struct kvm_vcpu
*vcpu
,
1789 struct list_head
*root
= vgic_get_irq_phys_map_list(vcpu
, virt_irq
);
1790 struct irq_phys_map_entry
*entry
;
1791 struct irq_phys_map
*map
;
1795 list_for_each_entry_rcu(entry
, root
, entry
) {
1797 if (map
->virt_irq
== virt_irq
) {
1808 static void vgic_free_phys_irq_map_rcu(struct rcu_head
*rcu
)
1810 struct irq_phys_map_entry
*entry
;
1812 entry
= container_of(rcu
, struct irq_phys_map_entry
, rcu
);
1817 * kvm_vgic_unmap_phys_irq - Remove a virtual to physical IRQ mapping
1818 * @vcpu: The VCPU pointer
1819 * @map: The pointer to a mapping obtained through kvm_vgic_map_phys_irq
1821 * Remove an existing mapping between virtual and physical interrupts.
1823 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu
*vcpu
, struct irq_phys_map
*map
)
1825 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1826 struct irq_phys_map_entry
*entry
;
1827 struct list_head
*root
;
1832 root
= vgic_get_irq_phys_map_list(vcpu
, map
->virt_irq
);
1834 spin_lock(&dist
->irq_phys_map_lock
);
1836 list_for_each_entry(entry
, root
, entry
) {
1837 if (&entry
->map
== map
) {
1838 list_del_rcu(&entry
->entry
);
1839 call_rcu(&entry
->rcu
, vgic_free_phys_irq_map_rcu
);
1844 spin_unlock(&dist
->irq_phys_map_lock
);
1849 static void vgic_destroy_irq_phys_map(struct kvm
*kvm
, struct list_head
*root
)
1851 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1852 struct irq_phys_map_entry
*entry
;
1854 spin_lock(&dist
->irq_phys_map_lock
);
1856 list_for_each_entry(entry
, root
, entry
) {
1857 list_del_rcu(&entry
->entry
);
1858 call_rcu(&entry
->rcu
, vgic_free_phys_irq_map_rcu
);
1861 spin_unlock(&dist
->irq_phys_map_lock
);
1864 void kvm_vgic_vcpu_destroy(struct kvm_vcpu
*vcpu
)
1866 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1868 kfree(vgic_cpu
->pending_shared
);
1869 kfree(vgic_cpu
->active_shared
);
1870 kfree(vgic_cpu
->pend_act_shared
);
1871 vgic_destroy_irq_phys_map(vcpu
->kvm
, &vgic_cpu
->irq_phys_map_list
);
1872 vgic_cpu
->pending_shared
= NULL
;
1873 vgic_cpu
->active_shared
= NULL
;
1874 vgic_cpu
->pend_act_shared
= NULL
;
1877 static int vgic_vcpu_init_maps(struct kvm_vcpu
*vcpu
, int nr_irqs
)
1879 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1881 int sz
= (nr_irqs
- VGIC_NR_PRIVATE_IRQS
) / 8;
1882 vgic_cpu
->pending_shared
= kzalloc(sz
, GFP_KERNEL
);
1883 vgic_cpu
->active_shared
= kzalloc(sz
, GFP_KERNEL
);
1884 vgic_cpu
->pend_act_shared
= kzalloc(sz
, GFP_KERNEL
);
1886 if (!vgic_cpu
->pending_shared
1887 || !vgic_cpu
->active_shared
1888 || !vgic_cpu
->pend_act_shared
) {
1889 kvm_vgic_vcpu_destroy(vcpu
);
1894 * Store the number of LRs per vcpu, so we don't have to go
1895 * all the way to the distributor structure to find out. Only
1896 * assembly code should use this one.
1898 vgic_cpu
->nr_lr
= vgic
->nr_lr
;
1904 * kvm_vgic_vcpu_early_init - Earliest possible per-vcpu vgic init stage
1906 * No memory allocation should be performed here, only static init.
1908 void kvm_vgic_vcpu_early_init(struct kvm_vcpu
*vcpu
)
1910 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1911 INIT_LIST_HEAD(&vgic_cpu
->irq_phys_map_list
);
1915 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW
1917 * The host's GIC naturally limits the maximum amount of VCPUs a guest
1920 int kvm_vgic_get_max_vcpus(void)
1922 return vgic
->max_gic_vcpus
;
1925 void kvm_vgic_destroy(struct kvm
*kvm
)
1927 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1928 struct kvm_vcpu
*vcpu
;
1931 kvm_for_each_vcpu(i
, vcpu
, kvm
)
1932 kvm_vgic_vcpu_destroy(vcpu
);
1934 vgic_free_bitmap(&dist
->irq_enabled
);
1935 vgic_free_bitmap(&dist
->irq_level
);
1936 vgic_free_bitmap(&dist
->irq_pending
);
1937 vgic_free_bitmap(&dist
->irq_soft_pend
);
1938 vgic_free_bitmap(&dist
->irq_queued
);
1939 vgic_free_bitmap(&dist
->irq_cfg
);
1940 vgic_free_bytemap(&dist
->irq_priority
);
1941 if (dist
->irq_spi_target
) {
1942 for (i
= 0; i
< dist
->nr_cpus
; i
++)
1943 vgic_free_bitmap(&dist
->irq_spi_target
[i
]);
1945 kfree(dist
->irq_sgi_sources
);
1946 kfree(dist
->irq_spi_cpu
);
1947 kfree(dist
->irq_spi_mpidr
);
1948 kfree(dist
->irq_spi_target
);
1949 kfree(dist
->irq_pending_on_cpu
);
1950 kfree(dist
->irq_active_on_cpu
);
1951 vgic_destroy_irq_phys_map(kvm
, &dist
->irq_phys_map_list
);
1952 dist
->irq_sgi_sources
= NULL
;
1953 dist
->irq_spi_cpu
= NULL
;
1954 dist
->irq_spi_target
= NULL
;
1955 dist
->irq_pending_on_cpu
= NULL
;
1956 dist
->irq_active_on_cpu
= NULL
;
1961 * Allocate and initialize the various data structures. Must be called
1962 * with kvm->lock held!
1964 int vgic_init(struct kvm
*kvm
)
1966 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1967 struct kvm_vcpu
*vcpu
;
1968 int nr_cpus
, nr_irqs
;
1969 int ret
, i
, vcpu_id
;
1971 if (vgic_initialized(kvm
))
1974 nr_cpus
= dist
->nr_cpus
= atomic_read(&kvm
->online_vcpus
);
1975 if (!nr_cpus
) /* No vcpus? Can't be good... */
1979 * If nobody configured the number of interrupts, use the
1983 dist
->nr_irqs
= VGIC_NR_IRQS_LEGACY
;
1985 nr_irqs
= dist
->nr_irqs
;
1987 ret
= vgic_init_bitmap(&dist
->irq_enabled
, nr_cpus
, nr_irqs
);
1988 ret
|= vgic_init_bitmap(&dist
->irq_level
, nr_cpus
, nr_irqs
);
1989 ret
|= vgic_init_bitmap(&dist
->irq_pending
, nr_cpus
, nr_irqs
);
1990 ret
|= vgic_init_bitmap(&dist
->irq_soft_pend
, nr_cpus
, nr_irqs
);
1991 ret
|= vgic_init_bitmap(&dist
->irq_queued
, nr_cpus
, nr_irqs
);
1992 ret
|= vgic_init_bitmap(&dist
->irq_active
, nr_cpus
, nr_irqs
);
1993 ret
|= vgic_init_bitmap(&dist
->irq_cfg
, nr_cpus
, nr_irqs
);
1994 ret
|= vgic_init_bytemap(&dist
->irq_priority
, nr_cpus
, nr_irqs
);
1999 dist
->irq_sgi_sources
= kzalloc(nr_cpus
* VGIC_NR_SGIS
, GFP_KERNEL
);
2000 dist
->irq_spi_cpu
= kzalloc(nr_irqs
- VGIC_NR_PRIVATE_IRQS
, GFP_KERNEL
);
2001 dist
->irq_spi_target
= kzalloc(sizeof(*dist
->irq_spi_target
) * nr_cpus
,
2003 dist
->irq_pending_on_cpu
= kzalloc(BITS_TO_LONGS(nr_cpus
) * sizeof(long),
2005 dist
->irq_active_on_cpu
= kzalloc(BITS_TO_LONGS(nr_cpus
) * sizeof(long),
2007 if (!dist
->irq_sgi_sources
||
2008 !dist
->irq_spi_cpu
||
2009 !dist
->irq_spi_target
||
2010 !dist
->irq_pending_on_cpu
||
2011 !dist
->irq_active_on_cpu
) {
2016 for (i
= 0; i
< nr_cpus
; i
++)
2017 ret
|= vgic_init_bitmap(&dist
->irq_spi_target
[i
],
2023 ret
= kvm
->arch
.vgic
.vm_ops
.init_model(kvm
);
2027 kvm_for_each_vcpu(vcpu_id
, vcpu
, kvm
) {
2028 ret
= vgic_vcpu_init_maps(vcpu
, nr_irqs
);
2030 kvm_err("VGIC: Failed to allocate vcpu memory\n");
2035 * Enable and configure all SGIs to be edge-triggere and
2036 * configure all PPIs as level-triggered.
2038 for (i
= 0; i
< VGIC_NR_PRIVATE_IRQS
; i
++) {
2039 if (i
< VGIC_NR_SGIS
) {
2041 vgic_bitmap_set_irq_val(&dist
->irq_enabled
,
2042 vcpu
->vcpu_id
, i
, 1);
2043 vgic_bitmap_set_irq_val(&dist
->irq_cfg
,
2046 } else if (i
< VGIC_NR_PRIVATE_IRQS
) {
2048 vgic_bitmap_set_irq_val(&dist
->irq_cfg
,
2059 kvm_vgic_destroy(kvm
);
2064 static int init_vgic_model(struct kvm
*kvm
, int type
)
2067 case KVM_DEV_TYPE_ARM_VGIC_V2
:
2068 vgic_v2_init_emulation(kvm
);
2070 #ifdef CONFIG_KVM_ARM_VGIC_V3
2071 case KVM_DEV_TYPE_ARM_VGIC_V3
:
2072 vgic_v3_init_emulation(kvm
);
2079 if (atomic_read(&kvm
->online_vcpus
) > kvm
->arch
.max_vcpus
)
2086 * kvm_vgic_early_init - Earliest possible vgic initialization stage
2088 * No memory allocation should be performed here, only static init.
2090 void kvm_vgic_early_init(struct kvm
*kvm
)
2092 spin_lock_init(&kvm
->arch
.vgic
.lock
);
2093 spin_lock_init(&kvm
->arch
.vgic
.irq_phys_map_lock
);
2094 INIT_LIST_HEAD(&kvm
->arch
.vgic
.irq_phys_map_list
);
2097 int kvm_vgic_create(struct kvm
*kvm
, u32 type
)
2099 int i
, vcpu_lock_idx
= -1, ret
;
2100 struct kvm_vcpu
*vcpu
;
2102 mutex_lock(&kvm
->lock
);
2104 if (irqchip_in_kernel(kvm
)) {
2110 * This function is also called by the KVM_CREATE_IRQCHIP handler,
2111 * which had no chance yet to check the availability of the GICv2
2112 * emulation. So check this here again. KVM_CREATE_DEVICE does
2113 * the proper checks already.
2115 if (type
== KVM_DEV_TYPE_ARM_VGIC_V2
&& !vgic
->can_emulate_gicv2
) {
2121 * Any time a vcpu is run, vcpu_load is called which tries to grab the
2122 * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure
2123 * that no other VCPUs are run while we create the vgic.
2126 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
2127 if (!mutex_trylock(&vcpu
->mutex
))
2132 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
2133 if (vcpu
->arch
.has_run_once
)
2138 ret
= init_vgic_model(kvm
, type
);
2142 kvm
->arch
.vgic
.in_kernel
= true;
2143 kvm
->arch
.vgic
.vgic_model
= type
;
2144 kvm
->arch
.vgic
.vctrl_base
= vgic
->vctrl_base
;
2145 kvm
->arch
.vgic
.vgic_dist_base
= VGIC_ADDR_UNDEF
;
2146 kvm
->arch
.vgic
.vgic_cpu_base
= VGIC_ADDR_UNDEF
;
2147 kvm
->arch
.vgic
.vgic_redist_base
= VGIC_ADDR_UNDEF
;
2150 for (; vcpu_lock_idx
>= 0; vcpu_lock_idx
--) {
2151 vcpu
= kvm_get_vcpu(kvm
, vcpu_lock_idx
);
2152 mutex_unlock(&vcpu
->mutex
);
2156 mutex_unlock(&kvm
->lock
);
2160 static int vgic_ioaddr_overlap(struct kvm
*kvm
)
2162 phys_addr_t dist
= kvm
->arch
.vgic
.vgic_dist_base
;
2163 phys_addr_t cpu
= kvm
->arch
.vgic
.vgic_cpu_base
;
2165 if (IS_VGIC_ADDR_UNDEF(dist
) || IS_VGIC_ADDR_UNDEF(cpu
))
2167 if ((dist
<= cpu
&& dist
+ KVM_VGIC_V2_DIST_SIZE
> cpu
) ||
2168 (cpu
<= dist
&& cpu
+ KVM_VGIC_V2_CPU_SIZE
> dist
))
2173 static int vgic_ioaddr_assign(struct kvm
*kvm
, phys_addr_t
*ioaddr
,
2174 phys_addr_t addr
, phys_addr_t size
)
2178 if (addr
& ~KVM_PHYS_MASK
)
2181 if (addr
& (SZ_4K
- 1))
2184 if (!IS_VGIC_ADDR_UNDEF(*ioaddr
))
2186 if (addr
+ size
< addr
)
2190 ret
= vgic_ioaddr_overlap(kvm
);
2192 *ioaddr
= VGIC_ADDR_UNDEF
;
2198 * kvm_vgic_addr - set or get vgic VM base addresses
2199 * @kvm: pointer to the vm struct
2200 * @type: the VGIC addr type, one of KVM_VGIC_V[23]_ADDR_TYPE_XXX
2201 * @addr: pointer to address value
2202 * @write: if true set the address in the VM address space, if false read the
2205 * Set or get the vgic base addresses for the distributor and the virtual CPU
2206 * interface in the VM physical address space. These addresses are properties
2207 * of the emulated core/SoC and therefore user space initially knows this
2210 int kvm_vgic_addr(struct kvm
*kvm
, unsigned long type
, u64
*addr
, bool write
)
2213 struct vgic_dist
*vgic
= &kvm
->arch
.vgic
;
2215 phys_addr_t
*addr_ptr
, block_size
;
2216 phys_addr_t alignment
;
2218 mutex_lock(&kvm
->lock
);
2220 case KVM_VGIC_V2_ADDR_TYPE_DIST
:
2221 type_needed
= KVM_DEV_TYPE_ARM_VGIC_V2
;
2222 addr_ptr
= &vgic
->vgic_dist_base
;
2223 block_size
= KVM_VGIC_V2_DIST_SIZE
;
2226 case KVM_VGIC_V2_ADDR_TYPE_CPU
:
2227 type_needed
= KVM_DEV_TYPE_ARM_VGIC_V2
;
2228 addr_ptr
= &vgic
->vgic_cpu_base
;
2229 block_size
= KVM_VGIC_V2_CPU_SIZE
;
2232 #ifdef CONFIG_KVM_ARM_VGIC_V3
2233 case KVM_VGIC_V3_ADDR_TYPE_DIST
:
2234 type_needed
= KVM_DEV_TYPE_ARM_VGIC_V3
;
2235 addr_ptr
= &vgic
->vgic_dist_base
;
2236 block_size
= KVM_VGIC_V3_DIST_SIZE
;
2239 case KVM_VGIC_V3_ADDR_TYPE_REDIST
:
2240 type_needed
= KVM_DEV_TYPE_ARM_VGIC_V3
;
2241 addr_ptr
= &vgic
->vgic_redist_base
;
2242 block_size
= KVM_VGIC_V3_REDIST_SIZE
;
2251 if (vgic
->vgic_model
!= type_needed
) {
2257 if (!IS_ALIGNED(*addr
, alignment
))
2260 r
= vgic_ioaddr_assign(kvm
, addr_ptr
, *addr
,
2267 mutex_unlock(&kvm
->lock
);
2271 int vgic_set_common_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
2275 switch (attr
->group
) {
2276 case KVM_DEV_ARM_VGIC_GRP_ADDR
: {
2277 u64 __user
*uaddr
= (u64 __user
*)(long)attr
->addr
;
2279 unsigned long type
= (unsigned long)attr
->attr
;
2281 if (copy_from_user(&addr
, uaddr
, sizeof(addr
)))
2284 r
= kvm_vgic_addr(dev
->kvm
, type
, &addr
, true);
2285 return (r
== -ENODEV
) ? -ENXIO
: r
;
2287 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS
: {
2288 u32 __user
*uaddr
= (u32 __user
*)(long)attr
->addr
;
2292 if (get_user(val
, uaddr
))
2297 * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs
2298 * - at most 1024 interrupts
2299 * - a multiple of 32 interrupts
2301 if (val
< (VGIC_NR_PRIVATE_IRQS
+ 32) ||
2302 val
> VGIC_MAX_IRQS
||
2306 mutex_lock(&dev
->kvm
->lock
);
2308 if (vgic_ready(dev
->kvm
) || dev
->kvm
->arch
.vgic
.nr_irqs
)
2311 dev
->kvm
->arch
.vgic
.nr_irqs
= val
;
2313 mutex_unlock(&dev
->kvm
->lock
);
2317 case KVM_DEV_ARM_VGIC_GRP_CTRL
: {
2318 switch (attr
->attr
) {
2319 case KVM_DEV_ARM_VGIC_CTRL_INIT
:
2320 r
= vgic_init(dev
->kvm
);
2330 int vgic_get_common_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
2334 switch (attr
->group
) {
2335 case KVM_DEV_ARM_VGIC_GRP_ADDR
: {
2336 u64 __user
*uaddr
= (u64 __user
*)(long)attr
->addr
;
2338 unsigned long type
= (unsigned long)attr
->attr
;
2340 r
= kvm_vgic_addr(dev
->kvm
, type
, &addr
, false);
2342 return (r
== -ENODEV
) ? -ENXIO
: r
;
2344 if (copy_to_user(uaddr
, &addr
, sizeof(addr
)))
2348 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS
: {
2349 u32 __user
*uaddr
= (u32 __user
*)(long)attr
->addr
;
2351 r
= put_user(dev
->kvm
->arch
.vgic
.nr_irqs
, uaddr
);
2360 int vgic_has_attr_regs(const struct vgic_io_range
*ranges
, phys_addr_t offset
)
2362 if (vgic_find_range(ranges
, 4, offset
))
2368 static void vgic_init_maintenance_interrupt(void *info
)
2370 enable_percpu_irq(vgic
->maint_irq
, 0);
2373 static int vgic_cpu_notify(struct notifier_block
*self
,
2374 unsigned long action
, void *cpu
)
2378 case CPU_STARTING_FROZEN
:
2379 vgic_init_maintenance_interrupt(NULL
);
2382 case CPU_DYING_FROZEN
:
2383 disable_percpu_irq(vgic
->maint_irq
);
2390 static struct notifier_block vgic_cpu_nb
= {
2391 .notifier_call
= vgic_cpu_notify
,
2394 static const struct of_device_id vgic_ids
[] = {
2395 { .compatible
= "arm,cortex-a15-gic", .data
= vgic_v2_probe
, },
2396 { .compatible
= "arm,cortex-a7-gic", .data
= vgic_v2_probe
, },
2397 { .compatible
= "arm,gic-400", .data
= vgic_v2_probe
, },
2398 { .compatible
= "arm,gic-v3", .data
= vgic_v3_probe
, },
2402 int kvm_vgic_hyp_init(void)
2404 const struct of_device_id
*matched_id
;
2405 const int (*vgic_probe
)(struct device_node
*,const struct vgic_ops
**,
2406 const struct vgic_params
**);
2407 struct device_node
*vgic_node
;
2410 vgic_node
= of_find_matching_node_and_match(NULL
,
2411 vgic_ids
, &matched_id
);
2413 kvm_err("error: no compatible GIC node found\n");
2417 vgic_probe
= matched_id
->data
;
2418 ret
= vgic_probe(vgic_node
, &vgic_ops
, &vgic
);
2422 ret
= request_percpu_irq(vgic
->maint_irq
, vgic_maintenance_handler
,
2423 "vgic", kvm_get_running_vcpus());
2425 kvm_err("Cannot register interrupt %d\n", vgic
->maint_irq
);
2429 ret
= __register_cpu_notifier(&vgic_cpu_nb
);
2431 kvm_err("Cannot register vgic CPU notifier\n");
2435 on_each_cpu(vgic_init_maintenance_interrupt
, NULL
, 1);
2440 free_percpu_irq(vgic
->maint_irq
, kvm_get_running_vcpus());
2444 int kvm_irq_map_gsi(struct kvm
*kvm
,
2445 struct kvm_kernel_irq_routing_entry
*entries
,
2451 int kvm_irq_map_chip_pin(struct kvm
*kvm
, unsigned irqchip
, unsigned pin
)
2456 int kvm_set_irq(struct kvm
*kvm
, int irq_source_id
,
2457 u32 irq
, int level
, bool line_status
)
2459 unsigned int spi
= irq
+ VGIC_NR_PRIVATE_IRQS
;
2461 trace_kvm_set_irq(irq
, level
, irq_source_id
);
2463 BUG_ON(!vgic_initialized(kvm
));
2465 return kvm_vgic_inject_irq(kvm
, 0, spi
, level
);
2468 /* MSI not implemented yet */
2469 int kvm_set_msi(struct kvm_kernel_irq_routing_entry
*e
,
2470 struct kvm
*kvm
, int irq_source_id
,
2471 int level
, bool line_status
)