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1 /*
2 * Copyright (C) 2001 MandrakeSoft S.A.
3 *
4 * MandrakeSoft S.A.
5 * 43, rue d'Aboukir
6 * 75002 Paris - France
7 * http://www.linux-mandrake.com/
8 * http://www.mandrakesoft.com/
9 *
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2 of the License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * Yunhong Jiang <yunhong.jiang@intel.com>
25 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
26 * Based on Xen 3.1 code.
27 */
28
29 #include <linux/kvm_host.h>
30 #include <linux/kvm.h>
31 #include <linux/mm.h>
32 #include <linux/highmem.h>
33 #include <linux/smp.h>
34 #include <linux/hrtimer.h>
35 #include <linux/io.h>
36 #include <linux/slab.h>
37 #include <asm/processor.h>
38 #include <asm/page.h>
39 #include <asm/current.h>
40 #include <trace/events/kvm.h>
41
42 #include "ioapic.h"
43 #include "lapic.h"
44 #include "irq.h"
45
46 #if 0
47 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
48 #else
49 #define ioapic_debug(fmt, arg...)
50 #endif
51 static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
52
53 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
54 unsigned long addr,
55 unsigned long length)
56 {
57 unsigned long result = 0;
58
59 switch (ioapic->ioregsel) {
60 case IOAPIC_REG_VERSION:
61 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
62 | (IOAPIC_VERSION_ID & 0xff));
63 break;
64
65 case IOAPIC_REG_APIC_ID:
66 case IOAPIC_REG_ARB_ID:
67 result = ((ioapic->id & 0xf) << 24);
68 break;
69
70 default:
71 {
72 u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
73 u64 redir_content;
74
75 ASSERT(redir_index < IOAPIC_NUM_PINS);
76
77 redir_content = ioapic->redirtbl[redir_index].bits;
78 result = (ioapic->ioregsel & 0x1) ?
79 (redir_content >> 32) & 0xffffffff :
80 redir_content & 0xffffffff;
81 break;
82 }
83 }
84
85 return result;
86 }
87
88 static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
89 {
90 union kvm_ioapic_redirect_entry *pent;
91 int injected = -1;
92
93 pent = &ioapic->redirtbl[idx];
94
95 if (!pent->fields.mask) {
96 injected = ioapic_deliver(ioapic, idx);
97 if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
98 pent->fields.remote_irr = 1;
99 }
100
101 return injected;
102 }
103
104 static void update_handled_vectors(struct kvm_ioapic *ioapic)
105 {
106 DECLARE_BITMAP(handled_vectors, 256);
107 int i;
108
109 memset(handled_vectors, 0, sizeof(handled_vectors));
110 for (i = 0; i < IOAPIC_NUM_PINS; ++i)
111 __set_bit(ioapic->redirtbl[i].fields.vector, handled_vectors);
112 memcpy(ioapic->handled_vectors, handled_vectors,
113 sizeof(handled_vectors));
114 smp_wmb();
115 }
116
117 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
118 {
119 unsigned index;
120 bool mask_before, mask_after;
121 union kvm_ioapic_redirect_entry *e;
122
123 switch (ioapic->ioregsel) {
124 case IOAPIC_REG_VERSION:
125 /* Writes are ignored. */
126 break;
127
128 case IOAPIC_REG_APIC_ID:
129 ioapic->id = (val >> 24) & 0xf;
130 break;
131
132 case IOAPIC_REG_ARB_ID:
133 break;
134
135 default:
136 index = (ioapic->ioregsel - 0x10) >> 1;
137
138 ioapic_debug("change redir index %x val %x\n", index, val);
139 if (index >= IOAPIC_NUM_PINS)
140 return;
141 e = &ioapic->redirtbl[index];
142 mask_before = e->fields.mask;
143 if (ioapic->ioregsel & 1) {
144 e->bits &= 0xffffffff;
145 e->bits |= (u64) val << 32;
146 } else {
147 e->bits &= ~0xffffffffULL;
148 e->bits |= (u32) val;
149 e->fields.remote_irr = 0;
150 }
151 update_handled_vectors(ioapic);
152 mask_after = e->fields.mask;
153 if (mask_before != mask_after)
154 kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
155 if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
156 && ioapic->irr & (1 << index))
157 ioapic_service(ioapic, index);
158 break;
159 }
160 }
161
162 static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
163 {
164 union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
165 struct kvm_lapic_irq irqe;
166
167 ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
168 "vector=%x trig_mode=%x\n",
169 entry->fields.dest, entry->fields.dest_mode,
170 entry->fields.delivery_mode, entry->fields.vector,
171 entry->fields.trig_mode);
172
173 irqe.dest_id = entry->fields.dest_id;
174 irqe.vector = entry->fields.vector;
175 irqe.dest_mode = entry->fields.dest_mode;
176 irqe.trig_mode = entry->fields.trig_mode;
177 irqe.delivery_mode = entry->fields.delivery_mode << 8;
178 irqe.level = 1;
179 irqe.shorthand = 0;
180
181 #ifdef CONFIG_X86
182 /* Always delivery PIT interrupt to vcpu 0 */
183 if (irq == 0) {
184 irqe.dest_mode = 0; /* Physical mode. */
185 /* need to read apic_id from apic regiest since
186 * it can be rewritten */
187 irqe.dest_id = ioapic->kvm->bsp_vcpu->vcpu_id;
188 }
189 #endif
190 return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
191 }
192
193 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
194 {
195 u32 old_irr = ioapic->irr;
196 u32 mask = 1 << irq;
197 union kvm_ioapic_redirect_entry entry;
198 int ret = 1;
199
200 mutex_lock(&ioapic->lock);
201 if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
202 entry = ioapic->redirtbl[irq];
203 level ^= entry.fields.polarity;
204 if (!level)
205 ioapic->irr &= ~mask;
206 else {
207 int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
208 ioapic->irr |= mask;
209 if ((edge && old_irr != ioapic->irr) ||
210 (!edge && !entry.fields.remote_irr))
211 ret = ioapic_service(ioapic, irq);
212 else
213 ret = 0; /* report coalesced interrupt */
214 }
215 trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
216 }
217 mutex_unlock(&ioapic->lock);
218
219 return ret;
220 }
221
222 static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
223 int trigger_mode)
224 {
225 int i;
226
227 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
228 union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
229
230 if (ent->fields.vector != vector)
231 continue;
232
233 /*
234 * We are dropping lock while calling ack notifiers because ack
235 * notifier callbacks for assigned devices call into IOAPIC
236 * recursively. Since remote_irr is cleared only after call
237 * to notifiers if the same vector will be delivered while lock
238 * is dropped it will be put into irr and will be delivered
239 * after ack notifier returns.
240 */
241 mutex_unlock(&ioapic->lock);
242 kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, i);
243 mutex_lock(&ioapic->lock);
244
245 if (trigger_mode != IOAPIC_LEVEL_TRIG)
246 continue;
247
248 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
249 ent->fields.remote_irr = 0;
250 if (!ent->fields.mask && (ioapic->irr & (1 << i)))
251 ioapic_service(ioapic, i);
252 }
253 }
254
255 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
256 {
257 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
258
259 smp_rmb();
260 if (!test_bit(vector, ioapic->handled_vectors))
261 return;
262 mutex_lock(&ioapic->lock);
263 __kvm_ioapic_update_eoi(ioapic, vector, trigger_mode);
264 mutex_unlock(&ioapic->lock);
265 }
266
267 static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
268 {
269 return container_of(dev, struct kvm_ioapic, dev);
270 }
271
272 static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
273 {
274 return ((addr >= ioapic->base_address &&
275 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
276 }
277
278 static int ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
279 void *val)
280 {
281 struct kvm_ioapic *ioapic = to_ioapic(this);
282 u32 result;
283 if (!ioapic_in_range(ioapic, addr))
284 return -EOPNOTSUPP;
285
286 ioapic_debug("addr %lx\n", (unsigned long)addr);
287 ASSERT(!(addr & 0xf)); /* check alignment */
288
289 addr &= 0xff;
290 mutex_lock(&ioapic->lock);
291 switch (addr) {
292 case IOAPIC_REG_SELECT:
293 result = ioapic->ioregsel;
294 break;
295
296 case IOAPIC_REG_WINDOW:
297 result = ioapic_read_indirect(ioapic, addr, len);
298 break;
299
300 default:
301 result = 0;
302 break;
303 }
304 mutex_unlock(&ioapic->lock);
305
306 switch (len) {
307 case 8:
308 *(u64 *) val = result;
309 break;
310 case 1:
311 case 2:
312 case 4:
313 memcpy(val, (char *)&result, len);
314 break;
315 default:
316 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
317 }
318 return 0;
319 }
320
321 static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
322 const void *val)
323 {
324 struct kvm_ioapic *ioapic = to_ioapic(this);
325 u32 data;
326 if (!ioapic_in_range(ioapic, addr))
327 return -EOPNOTSUPP;
328
329 ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
330 (void*)addr, len, val);
331 ASSERT(!(addr & 0xf)); /* check alignment */
332
333 if (len == 4 || len == 8)
334 data = *(u32 *) val;
335 else {
336 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
337 return 0;
338 }
339
340 addr &= 0xff;
341 mutex_lock(&ioapic->lock);
342 switch (addr) {
343 case IOAPIC_REG_SELECT:
344 ioapic->ioregsel = data;
345 break;
346
347 case IOAPIC_REG_WINDOW:
348 ioapic_write_indirect(ioapic, data);
349 break;
350 #ifdef CONFIG_IA64
351 case IOAPIC_REG_EOI:
352 __kvm_ioapic_update_eoi(ioapic, data, IOAPIC_LEVEL_TRIG);
353 break;
354 #endif
355
356 default:
357 break;
358 }
359 mutex_unlock(&ioapic->lock);
360 return 0;
361 }
362
363 void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
364 {
365 int i;
366
367 for (i = 0; i < IOAPIC_NUM_PINS; i++)
368 ioapic->redirtbl[i].fields.mask = 1;
369 ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
370 ioapic->ioregsel = 0;
371 ioapic->irr = 0;
372 ioapic->id = 0;
373 update_handled_vectors(ioapic);
374 }
375
376 static const struct kvm_io_device_ops ioapic_mmio_ops = {
377 .read = ioapic_mmio_read,
378 .write = ioapic_mmio_write,
379 };
380
381 int kvm_ioapic_init(struct kvm *kvm)
382 {
383 struct kvm_ioapic *ioapic;
384 int ret;
385
386 ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
387 if (!ioapic)
388 return -ENOMEM;
389 mutex_init(&ioapic->lock);
390 kvm->arch.vioapic = ioapic;
391 kvm_ioapic_reset(ioapic);
392 kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
393 ioapic->kvm = kvm;
394 mutex_lock(&kvm->slots_lock);
395 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
396 mutex_unlock(&kvm->slots_lock);
397 if (ret < 0) {
398 kvm->arch.vioapic = NULL;
399 kfree(ioapic);
400 }
401
402 return ret;
403 }
404
405 void kvm_ioapic_destroy(struct kvm *kvm)
406 {
407 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
408
409 if (ioapic) {
410 kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
411 kvm->arch.vioapic = NULL;
412 kfree(ioapic);
413 }
414 }
415
416 int kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
417 {
418 struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
419 if (!ioapic)
420 return -EINVAL;
421
422 mutex_lock(&ioapic->lock);
423 memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
424 mutex_unlock(&ioapic->lock);
425 return 0;
426 }
427
428 int kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
429 {
430 struct kvm_ioapic *ioapic = ioapic_irqchip(kvm);
431 if (!ioapic)
432 return -EINVAL;
433
434 mutex_lock(&ioapic->lock);
435 memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
436 update_handled_vectors(ioapic);
437 mutex_unlock(&ioapic->lock);
438 return 0;
439 }