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1 /*
2 * QEMU System Emulator header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #ifndef VL_H
25 #define VL_H
26
27 /* we put basic includes here to avoid repeating them in device drivers */
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <stdarg.h>
31 #include <string.h>
32 #include <inttypes.h>
33 #include <limits.h>
34 #include <time.h>
35 #include <ctype.h>
36 #include <errno.h>
37 #include <unistd.h>
38 #include <fcntl.h>
39 #include <sys/stat.h>
40
41 #ifndef O_LARGEFILE
42 #define O_LARGEFILE 0
43 #endif
44 #ifndef O_BINARY
45 #define O_BINARY 0
46 #endif
47
48 #ifndef ENOMEDIUM
49 #define ENOMEDIUM ENODEV
50 #endif
51
52 #ifdef _WIN32
53 #include <windows.h>
54 #define fsync _commit
55 #define lseek _lseeki64
56 #define ENOTSUP 4096
57 extern int qemu_ftruncate64(int, int64_t);
58 #define ftruncate qemu_ftruncate64
59
60
61 static inline char *realpath(const char *path, char *resolved_path)
62 {
63 _fullpath(resolved_path, path, _MAX_PATH);
64 return resolved_path;
65 }
66
67 #define PRId64 "I64d"
68 #define PRIx64 "I64x"
69 #define PRIu64 "I64u"
70 #define PRIo64 "I64o"
71 #endif
72
73 #ifdef QEMU_TOOL
74
75 /* we use QEMU_TOOL on code which does not depend on the target CPU
76 type */
77 #include "config-host.h"
78 #include <setjmp.h>
79 #include "osdep.h"
80 #include "bswap.h"
81
82 #else
83
84 #include "cpu.h"
85
86 #endif /* !defined(QEMU_TOOL) */
87
88 #ifndef glue
89 #define xglue(x, y) x ## y
90 #define glue(x, y) xglue(x, y)
91 #define stringify(s) tostring(s)
92 #define tostring(s) #s
93 #endif
94
95 #ifndef likely
96 #if __GNUC__ < 3
97 #define __builtin_expect(x, n) (x)
98 #endif
99
100 #define likely(x) __builtin_expect(!!(x), 1)
101 #define unlikely(x) __builtin_expect(!!(x), 0)
102 #endif
103
104 #ifndef MIN
105 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
106 #endif
107 #ifndef MAX
108 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
109 #endif
110
111 #ifndef always_inline
112 #if (__GNUC__ < 3) || defined(__APPLE__)
113 #define always_inline inline
114 #else
115 #define always_inline __attribute__ (( always_inline )) inline
116 #endif
117 #endif
118
119 #include "audio/audio.h"
120
121 /* cutils.c */
122 void pstrcpy(char *buf, int buf_size, const char *str);
123 char *pstrcat(char *buf, int buf_size, const char *s);
124 int strstart(const char *str, const char *val, const char **ptr);
125 int stristart(const char *str, const char *val, const char **ptr);
126 time_t mktimegm(struct tm *tm);
127
128 /* vl.c */
129 uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
130
131 void hw_error(const char *fmt, ...);
132
133 extern const char *bios_dir;
134 extern const char *bios_name;
135
136 extern int vm_running;
137 extern const char *qemu_name;
138
139 typedef struct vm_change_state_entry VMChangeStateEntry;
140 typedef void VMChangeStateHandler(void *opaque, int running);
141 typedef void VMStopHandler(void *opaque, int reason);
142
143 VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
144 void *opaque);
145 void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
146
147 int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
148 void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
149
150 void vm_start(void);
151 void vm_stop(int reason);
152
153 typedef void QEMUResetHandler(void *opaque);
154
155 void qemu_register_reset(QEMUResetHandler *func, void *opaque);
156 void qemu_system_reset_request(void);
157 void qemu_system_shutdown_request(void);
158 void qemu_system_powerdown_request(void);
159 #if !defined(TARGET_SPARC)
160 // Please implement a power failure function to signal the OS
161 #define qemu_system_powerdown() do{}while(0)
162 #else
163 void qemu_system_powerdown(void);
164 #endif
165
166 void main_loop_wait(int timeout);
167
168 extern int ram_size;
169 extern int bios_size;
170 extern int rtc_utc;
171 extern int rtc_start_date;
172 extern int cirrus_vga_enabled;
173 extern int vmsvga_enabled;
174 extern int graphic_width;
175 extern int graphic_height;
176 extern int graphic_depth;
177 extern const char *keyboard_layout;
178 extern int kqemu_allowed;
179 extern int win2k_install_hack;
180 extern int alt_grab;
181 extern int usb_enabled;
182 extern int smp_cpus;
183 extern int cursor_hide;
184 extern int graphic_rotate;
185 extern int no_quit;
186 extern int semihosting_enabled;
187 extern int autostart;
188 extern int old_param;
189 extern const char *bootp_filename;
190
191 #define MAX_OPTION_ROMS 16
192 extern const char *option_rom[MAX_OPTION_ROMS];
193 extern int nb_option_roms;
194
195 #ifdef TARGET_SPARC
196 #define MAX_PROM_ENVS 128
197 extern const char *prom_envs[MAX_PROM_ENVS];
198 extern unsigned int nb_prom_envs;
199 #endif
200
201 /* XXX: make it dynamic */
202 #define MAX_BIOS_SIZE (4 * 1024 * 1024)
203 #if defined (TARGET_PPC)
204 #define BIOS_SIZE (1024 * 1024)
205 #elif defined (TARGET_SPARC64)
206 #define BIOS_SIZE ((512 + 32) * 1024)
207 #elif defined(TARGET_MIPS)
208 #define BIOS_SIZE (4 * 1024 * 1024)
209 #endif
210
211 /* keyboard/mouse support */
212
213 #define MOUSE_EVENT_LBUTTON 0x01
214 #define MOUSE_EVENT_RBUTTON 0x02
215 #define MOUSE_EVENT_MBUTTON 0x04
216
217 typedef void QEMUPutKBDEvent(void *opaque, int keycode);
218 typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
219
220 typedef struct QEMUPutMouseEntry {
221 QEMUPutMouseEvent *qemu_put_mouse_event;
222 void *qemu_put_mouse_event_opaque;
223 int qemu_put_mouse_event_absolute;
224 char *qemu_put_mouse_event_name;
225
226 /* used internally by qemu for handling mice */
227 struct QEMUPutMouseEntry *next;
228 } QEMUPutMouseEntry;
229
230 void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
231 QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
232 void *opaque, int absolute,
233 const char *name);
234 void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
235
236 void kbd_put_keycode(int keycode);
237 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
238 int kbd_mouse_is_absolute(void);
239
240 void do_info_mice(void);
241 void do_mouse_set(int index);
242
243 /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
244 constants) */
245 #define QEMU_KEY_ESC1(c) ((c) | 0xe100)
246 #define QEMU_KEY_BACKSPACE 0x007f
247 #define QEMU_KEY_UP QEMU_KEY_ESC1('A')
248 #define QEMU_KEY_DOWN QEMU_KEY_ESC1('B')
249 #define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C')
250 #define QEMU_KEY_LEFT QEMU_KEY_ESC1('D')
251 #define QEMU_KEY_HOME QEMU_KEY_ESC1(1)
252 #define QEMU_KEY_END QEMU_KEY_ESC1(4)
253 #define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5)
254 #define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6)
255 #define QEMU_KEY_DELETE QEMU_KEY_ESC1(3)
256
257 #define QEMU_KEY_CTRL_UP 0xe400
258 #define QEMU_KEY_CTRL_DOWN 0xe401
259 #define QEMU_KEY_CTRL_LEFT 0xe402
260 #define QEMU_KEY_CTRL_RIGHT 0xe403
261 #define QEMU_KEY_CTRL_HOME 0xe404
262 #define QEMU_KEY_CTRL_END 0xe405
263 #define QEMU_KEY_CTRL_PAGEUP 0xe406
264 #define QEMU_KEY_CTRL_PAGEDOWN 0xe407
265
266 void kbd_put_keysym(int keysym);
267
268 /* async I/O support */
269
270 typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
271 typedef int IOCanRWHandler(void *opaque);
272 typedef void IOHandler(void *opaque);
273
274 int qemu_set_fd_handler2(int fd,
275 IOCanRWHandler *fd_read_poll,
276 IOHandler *fd_read,
277 IOHandler *fd_write,
278 void *opaque);
279 int qemu_set_fd_handler(int fd,
280 IOHandler *fd_read,
281 IOHandler *fd_write,
282 void *opaque);
283
284 /* Polling handling */
285
286 /* return TRUE if no sleep should be done afterwards */
287 typedef int PollingFunc(void *opaque);
288
289 int qemu_add_polling_cb(PollingFunc *func, void *opaque);
290 void qemu_del_polling_cb(PollingFunc *func, void *opaque);
291
292 #ifdef _WIN32
293 /* Wait objects handling */
294 typedef void WaitObjectFunc(void *opaque);
295
296 int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
297 void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
298 #endif
299
300 typedef struct QEMUBH QEMUBH;
301
302 /* character device */
303
304 #define CHR_EVENT_BREAK 0 /* serial break char */
305 #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
306 #define CHR_EVENT_RESET 2 /* new connection established */
307
308
309 #define CHR_IOCTL_SERIAL_SET_PARAMS 1
310 typedef struct {
311 int speed;
312 int parity;
313 int data_bits;
314 int stop_bits;
315 } QEMUSerialSetParams;
316
317 #define CHR_IOCTL_SERIAL_SET_BREAK 2
318
319 #define CHR_IOCTL_PP_READ_DATA 3
320 #define CHR_IOCTL_PP_WRITE_DATA 4
321 #define CHR_IOCTL_PP_READ_CONTROL 5
322 #define CHR_IOCTL_PP_WRITE_CONTROL 6
323 #define CHR_IOCTL_PP_READ_STATUS 7
324 #define CHR_IOCTL_PP_EPP_READ_ADDR 8
325 #define CHR_IOCTL_PP_EPP_READ 9
326 #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
327 #define CHR_IOCTL_PP_EPP_WRITE 11
328
329 typedef void IOEventHandler(void *opaque, int event);
330
331 typedef struct CharDriverState {
332 int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
333 void (*chr_update_read_handler)(struct CharDriverState *s);
334 int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
335 IOEventHandler *chr_event;
336 IOCanRWHandler *chr_can_read;
337 IOReadHandler *chr_read;
338 void *handler_opaque;
339 void (*chr_send_event)(struct CharDriverState *chr, int event);
340 void (*chr_close)(struct CharDriverState *chr);
341 void *opaque;
342 int focus;
343 QEMUBH *bh;
344 } CharDriverState;
345
346 CharDriverState *qemu_chr_open(const char *filename);
347 void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
348 int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
349 void qemu_chr_send_event(CharDriverState *s, int event);
350 void qemu_chr_add_handlers(CharDriverState *s,
351 IOCanRWHandler *fd_can_read,
352 IOReadHandler *fd_read,
353 IOEventHandler *fd_event,
354 void *opaque);
355 int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
356 void qemu_chr_reset(CharDriverState *s);
357 int qemu_chr_can_read(CharDriverState *s);
358 void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
359
360 /* consoles */
361
362 typedef struct DisplayState DisplayState;
363 typedef struct TextConsole TextConsole;
364
365 struct DisplayState {
366 uint8_t *data;
367 int linesize;
368 int depth;
369 int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
370 int width;
371 int height;
372 void *opaque;
373 struct QEMUTimer *gui_timer;
374
375 void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
376 void (*dpy_resize)(struct DisplayState *s, int w, int h);
377 void (*dpy_refresh)(struct DisplayState *s);
378 void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
379 int dst_x, int dst_y, int w, int h);
380 void (*dpy_fill)(struct DisplayState *s, int x, int y,
381 int w, int h, uint32_t c);
382 void (*mouse_set)(int x, int y, int on);
383 void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
384 uint8_t *image, uint8_t *mask);
385 };
386
387 static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
388 {
389 s->dpy_update(s, x, y, w, h);
390 }
391
392 static inline void dpy_resize(DisplayState *s, int w, int h)
393 {
394 s->dpy_resize(s, w, h);
395 }
396
397 typedef void (*vga_hw_update_ptr)(void *);
398 typedef void (*vga_hw_invalidate_ptr)(void *);
399 typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
400
401 TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
402 vga_hw_invalidate_ptr invalidate,
403 vga_hw_screen_dump_ptr screen_dump,
404 void *opaque);
405 void vga_hw_update(void);
406 void vga_hw_invalidate(void);
407 void vga_hw_screen_dump(const char *filename);
408
409 int is_graphic_console(void);
410 CharDriverState *text_console_init(DisplayState *ds, const char *p);
411 void console_select(unsigned int index);
412 void console_color_init(DisplayState *ds);
413
414 /* serial ports */
415
416 #define MAX_SERIAL_PORTS 4
417
418 extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
419
420 /* parallel ports */
421
422 #define MAX_PARALLEL_PORTS 3
423
424 extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
425
426 struct ParallelIOArg {
427 void *buffer;
428 int count;
429 };
430
431 /* VLANs support */
432
433 typedef struct VLANClientState VLANClientState;
434
435 struct VLANClientState {
436 IOReadHandler *fd_read;
437 /* Packets may still be sent if this returns zero. It's used to
438 rate-limit the slirp code. */
439 IOCanRWHandler *fd_can_read;
440 void *opaque;
441 struct VLANClientState *next;
442 struct VLANState *vlan;
443 char info_str[256];
444 };
445
446 typedef struct VLANState {
447 int id;
448 VLANClientState *first_client;
449 struct VLANState *next;
450 unsigned int nb_guest_devs, nb_host_devs;
451 } VLANState;
452
453 VLANState *qemu_find_vlan(int id);
454 VLANClientState *qemu_new_vlan_client(VLANState *vlan,
455 IOReadHandler *fd_read,
456 IOCanRWHandler *fd_can_read,
457 void *opaque);
458 int qemu_can_send_packet(VLANClientState *vc);
459 void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
460 void qemu_handler_true(void *opaque);
461
462 void do_info_network(void);
463
464 /* TAP win32 */
465 int tap_win32_init(VLANState *vlan, const char *ifname);
466
467 /* NIC info */
468
469 #define MAX_NICS 8
470
471 typedef struct NICInfo {
472 uint8_t macaddr[6];
473 const char *model;
474 VLANState *vlan;
475 } NICInfo;
476
477 extern int nb_nics;
478 extern NICInfo nd_table[MAX_NICS];
479
480 /* SLIRP */
481 void do_info_slirp(void);
482
483 /* timers */
484
485 typedef struct QEMUClock QEMUClock;
486 typedef struct QEMUTimer QEMUTimer;
487 typedef void QEMUTimerCB(void *opaque);
488
489 /* The real time clock should be used only for stuff which does not
490 change the virtual machine state, as it is run even if the virtual
491 machine is stopped. The real time clock has a frequency of 1000
492 Hz. */
493 extern QEMUClock *rt_clock;
494
495 /* The virtual clock is only run during the emulation. It is stopped
496 when the virtual machine is stopped. Virtual timers use a high
497 precision clock, usually cpu cycles (use ticks_per_sec). */
498 extern QEMUClock *vm_clock;
499
500 int64_t qemu_get_clock(QEMUClock *clock);
501
502 QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
503 void qemu_free_timer(QEMUTimer *ts);
504 void qemu_del_timer(QEMUTimer *ts);
505 void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
506 int qemu_timer_pending(QEMUTimer *ts);
507
508 extern int64_t ticks_per_sec;
509
510 int64_t cpu_get_ticks(void);
511 void cpu_enable_ticks(void);
512 void cpu_disable_ticks(void);
513
514 /* VM Load/Save */
515
516 typedef struct QEMUFile QEMUFile;
517
518 QEMUFile *qemu_fopen(const char *filename, const char *mode);
519 void qemu_fflush(QEMUFile *f);
520 void qemu_fclose(QEMUFile *f);
521 void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
522 void qemu_put_byte(QEMUFile *f, int v);
523 void qemu_put_be16(QEMUFile *f, unsigned int v);
524 void qemu_put_be32(QEMUFile *f, unsigned int v);
525 void qemu_put_be64(QEMUFile *f, uint64_t v);
526 int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
527 int qemu_get_byte(QEMUFile *f);
528 unsigned int qemu_get_be16(QEMUFile *f);
529 unsigned int qemu_get_be32(QEMUFile *f);
530 uint64_t qemu_get_be64(QEMUFile *f);
531
532 static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
533 {
534 qemu_put_be64(f, *pv);
535 }
536
537 static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
538 {
539 qemu_put_be32(f, *pv);
540 }
541
542 static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
543 {
544 qemu_put_be16(f, *pv);
545 }
546
547 static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
548 {
549 qemu_put_byte(f, *pv);
550 }
551
552 static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
553 {
554 *pv = qemu_get_be64(f);
555 }
556
557 static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
558 {
559 *pv = qemu_get_be32(f);
560 }
561
562 static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
563 {
564 *pv = qemu_get_be16(f);
565 }
566
567 static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
568 {
569 *pv = qemu_get_byte(f);
570 }
571
572 #if TARGET_LONG_BITS == 64
573 #define qemu_put_betl qemu_put_be64
574 #define qemu_get_betl qemu_get_be64
575 #define qemu_put_betls qemu_put_be64s
576 #define qemu_get_betls qemu_get_be64s
577 #else
578 #define qemu_put_betl qemu_put_be32
579 #define qemu_get_betl qemu_get_be32
580 #define qemu_put_betls qemu_put_be32s
581 #define qemu_get_betls qemu_get_be32s
582 #endif
583
584 int64_t qemu_ftell(QEMUFile *f);
585 int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
586
587 typedef void SaveStateHandler(QEMUFile *f, void *opaque);
588 typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
589
590 int register_savevm(const char *idstr,
591 int instance_id,
592 int version_id,
593 SaveStateHandler *save_state,
594 LoadStateHandler *load_state,
595 void *opaque);
596 void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
597 void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
598
599 void cpu_save(QEMUFile *f, void *opaque);
600 int cpu_load(QEMUFile *f, void *opaque, int version_id);
601
602 void do_savevm(const char *name);
603 void do_loadvm(const char *name);
604 void do_delvm(const char *name);
605 void do_info_snapshots(void);
606
607 /* bottom halves */
608 typedef void QEMUBHFunc(void *opaque);
609
610 QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
611 void qemu_bh_schedule(QEMUBH *bh);
612 void qemu_bh_cancel(QEMUBH *bh);
613 void qemu_bh_delete(QEMUBH *bh);
614 int qemu_bh_poll(void);
615
616 /* block.c */
617 typedef struct BlockDriverState BlockDriverState;
618 typedef struct BlockDriver BlockDriver;
619
620 extern BlockDriver bdrv_raw;
621 extern BlockDriver bdrv_host_device;
622 extern BlockDriver bdrv_cow;
623 extern BlockDriver bdrv_qcow;
624 extern BlockDriver bdrv_vmdk;
625 extern BlockDriver bdrv_cloop;
626 extern BlockDriver bdrv_dmg;
627 extern BlockDriver bdrv_bochs;
628 extern BlockDriver bdrv_vpc;
629 extern BlockDriver bdrv_vvfat;
630 extern BlockDriver bdrv_qcow2;
631 extern BlockDriver bdrv_parallels;
632
633 typedef struct BlockDriverInfo {
634 /* in bytes, 0 if irrelevant */
635 int cluster_size;
636 /* offset at which the VM state can be saved (0 if not possible) */
637 int64_t vm_state_offset;
638 } BlockDriverInfo;
639
640 typedef struct QEMUSnapshotInfo {
641 char id_str[128]; /* unique snapshot id */
642 /* the following fields are informative. They are not needed for
643 the consistency of the snapshot */
644 char name[256]; /* user choosen name */
645 uint32_t vm_state_size; /* VM state info size */
646 uint32_t date_sec; /* UTC date of the snapshot */
647 uint32_t date_nsec;
648 uint64_t vm_clock_nsec; /* VM clock relative to boot */
649 } QEMUSnapshotInfo;
650
651 #define BDRV_O_RDONLY 0x0000
652 #define BDRV_O_RDWR 0x0002
653 #define BDRV_O_ACCESS 0x0003
654 #define BDRV_O_CREAT 0x0004 /* create an empty file */
655 #define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */
656 #define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to
657 use a disk image format on top of
658 it (default for
659 bdrv_file_open()) */
660
661 void bdrv_init(void);
662 BlockDriver *bdrv_find_format(const char *format_name);
663 int bdrv_create(BlockDriver *drv,
664 const char *filename, int64_t size_in_sectors,
665 const char *backing_file, int flags);
666 BlockDriverState *bdrv_new(const char *device_name);
667 void bdrv_delete(BlockDriverState *bs);
668 int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
669 int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
670 int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
671 BlockDriver *drv);
672 void bdrv_close(BlockDriverState *bs);
673 int bdrv_read(BlockDriverState *bs, int64_t sector_num,
674 uint8_t *buf, int nb_sectors);
675 int bdrv_write(BlockDriverState *bs, int64_t sector_num,
676 const uint8_t *buf, int nb_sectors);
677 int bdrv_pread(BlockDriverState *bs, int64_t offset,
678 void *buf, int count);
679 int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
680 const void *buf, int count);
681 int bdrv_truncate(BlockDriverState *bs, int64_t offset);
682 int64_t bdrv_getlength(BlockDriverState *bs);
683 void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
684 int bdrv_commit(BlockDriverState *bs);
685 void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
686 /* async block I/O */
687 typedef struct BlockDriverAIOCB BlockDriverAIOCB;
688 typedef void BlockDriverCompletionFunc(void *opaque, int ret);
689
690 BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
691 uint8_t *buf, int nb_sectors,
692 BlockDriverCompletionFunc *cb, void *opaque);
693 BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
694 const uint8_t *buf, int nb_sectors,
695 BlockDriverCompletionFunc *cb, void *opaque);
696 void bdrv_aio_cancel(BlockDriverAIOCB *acb);
697
698 void qemu_aio_init(void);
699 void qemu_aio_poll(void);
700 void qemu_aio_flush(void);
701 void qemu_aio_wait_start(void);
702 void qemu_aio_wait(void);
703 void qemu_aio_wait_end(void);
704
705 int qemu_key_check(BlockDriverState *bs, const char *name);
706
707 /* Ensure contents are flushed to disk. */
708 void bdrv_flush(BlockDriverState *bs);
709
710 #define BDRV_TYPE_HD 0
711 #define BDRV_TYPE_CDROM 1
712 #define BDRV_TYPE_FLOPPY 2
713 #define BIOS_ATA_TRANSLATION_AUTO 0
714 #define BIOS_ATA_TRANSLATION_NONE 1
715 #define BIOS_ATA_TRANSLATION_LBA 2
716 #define BIOS_ATA_TRANSLATION_LARGE 3
717 #define BIOS_ATA_TRANSLATION_RECHS 4
718
719 void bdrv_set_geometry_hint(BlockDriverState *bs,
720 int cyls, int heads, int secs);
721 void bdrv_set_type_hint(BlockDriverState *bs, int type);
722 void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
723 void bdrv_get_geometry_hint(BlockDriverState *bs,
724 int *pcyls, int *pheads, int *psecs);
725 int bdrv_get_type_hint(BlockDriverState *bs);
726 int bdrv_get_translation_hint(BlockDriverState *bs);
727 int bdrv_is_removable(BlockDriverState *bs);
728 int bdrv_is_read_only(BlockDriverState *bs);
729 int bdrv_is_inserted(BlockDriverState *bs);
730 int bdrv_media_changed(BlockDriverState *bs);
731 int bdrv_is_locked(BlockDriverState *bs);
732 void bdrv_set_locked(BlockDriverState *bs, int locked);
733 void bdrv_eject(BlockDriverState *bs, int eject_flag);
734 void bdrv_set_change_cb(BlockDriverState *bs,
735 void (*change_cb)(void *opaque), void *opaque);
736 void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
737 void bdrv_info(void);
738 BlockDriverState *bdrv_find(const char *name);
739 void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
740 int bdrv_is_encrypted(BlockDriverState *bs);
741 int bdrv_set_key(BlockDriverState *bs, const char *key);
742 void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
743 void *opaque);
744 const char *bdrv_get_device_name(BlockDriverState *bs);
745 int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
746 const uint8_t *buf, int nb_sectors);
747 int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
748
749 void bdrv_get_backing_filename(BlockDriverState *bs,
750 char *filename, int filename_size);
751 int bdrv_snapshot_create(BlockDriverState *bs,
752 QEMUSnapshotInfo *sn_info);
753 int bdrv_snapshot_goto(BlockDriverState *bs,
754 const char *snapshot_id);
755 int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
756 int bdrv_snapshot_list(BlockDriverState *bs,
757 QEMUSnapshotInfo **psn_info);
758 char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
759
760 char *get_human_readable_size(char *buf, int buf_size, int64_t size);
761 int path_is_absolute(const char *path);
762 void path_combine(char *dest, int dest_size,
763 const char *base_path,
764 const char *filename);
765
766
767 /* monitor.c */
768 void monitor_init(CharDriverState *hd, int show_banner);
769 void term_puts(const char *str);
770 void term_vprintf(const char *fmt, va_list ap);
771 void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
772 void term_print_filename(const char *filename);
773 void term_flush(void);
774 void term_print_help(void);
775 void monitor_readline(const char *prompt, int is_password,
776 char *buf, int buf_size);
777
778 /* readline.c */
779 typedef void ReadLineFunc(void *opaque, const char *str);
780
781 extern int completion_index;
782 void add_completion(const char *str);
783 void readline_handle_byte(int ch);
784 void readline_find_completion(const char *cmdline);
785 const char *readline_get_history(unsigned int index);
786 void readline_start(const char *prompt, int is_password,
787 ReadLineFunc *readline_func, void *opaque);
788
789 void kqemu_record_dump(void);
790
791 /* sdl.c */
792 void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
793
794 /* cocoa.m */
795 void cocoa_display_init(DisplayState *ds, int full_screen);
796
797 /* vnc.c */
798 void vnc_display_init(DisplayState *ds);
799 void vnc_display_close(DisplayState *ds);
800 int vnc_display_open(DisplayState *ds, const char *display);
801 int vnc_display_password(DisplayState *ds, const char *password);
802 void do_info_vnc(void);
803
804 /* x_keymap.c */
805 extern uint8_t _translate_keycode(const int key);
806
807 #ifndef QEMU_TOOL
808
809 typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
810 const char *boot_device,
811 DisplayState *ds, const char **fd_filename, int snapshot,
812 const char *kernel_filename, const char *kernel_cmdline,
813 const char *initrd_filename, const char *cpu_model);
814
815 typedef struct QEMUMachine {
816 const char *name;
817 const char *desc;
818 QEMUMachineInitFunc *init;
819 struct QEMUMachine *next;
820 } QEMUMachine;
821
822 int qemu_register_machine(QEMUMachine *m);
823
824 typedef void SetIRQFunc(void *opaque, int irq_num, int level);
825
826 #include "hw/irq.h"
827
828 /* ISA bus */
829
830 extern target_phys_addr_t isa_mem_base;
831
832 typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
833 typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
834
835 int register_ioport_read(int start, int length, int size,
836 IOPortReadFunc *func, void *opaque);
837 int register_ioport_write(int start, int length, int size,
838 IOPortWriteFunc *func, void *opaque);
839 void isa_unassign_ioport(int start, int length);
840
841 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
842
843 /* PCI bus */
844
845 extern target_phys_addr_t pci_mem_base;
846
847 typedef struct PCIBus PCIBus;
848 typedef struct PCIDevice PCIDevice;
849
850 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
851 uint32_t address, uint32_t data, int len);
852 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
853 uint32_t address, int len);
854 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
855 uint32_t addr, uint32_t size, int type);
856
857 #define PCI_ADDRESS_SPACE_MEM 0x00
858 #define PCI_ADDRESS_SPACE_IO 0x01
859 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
860
861 typedef struct PCIIORegion {
862 uint32_t addr; /* current PCI mapping address. -1 means not mapped */
863 uint32_t size;
864 uint8_t type;
865 PCIMapIORegionFunc *map_func;
866 } PCIIORegion;
867
868 #define PCI_ROM_SLOT 6
869 #define PCI_NUM_REGIONS 7
870
871 #define PCI_DEVICES_MAX 64
872
873 #define PCI_VENDOR_ID 0x00 /* 16 bits */
874 #define PCI_DEVICE_ID 0x02 /* 16 bits */
875 #define PCI_COMMAND 0x04 /* 16 bits */
876 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
877 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
878 #define PCI_CLASS_DEVICE 0x0a /* Device class */
879 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
880 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
881 #define PCI_MIN_GNT 0x3e /* 8 bits */
882 #define PCI_MAX_LAT 0x3f /* 8 bits */
883
884 struct PCIDevice {
885 /* PCI config space */
886 uint8_t config[256];
887
888 /* the following fields are read only */
889 PCIBus *bus;
890 int devfn;
891 char name[64];
892 PCIIORegion io_regions[PCI_NUM_REGIONS];
893
894 /* do not access the following fields */
895 PCIConfigReadFunc *config_read;
896 PCIConfigWriteFunc *config_write;
897 /* ??? This is a PC-specific hack, and should be removed. */
898 int irq_index;
899
900 /* IRQ objects for the INTA-INTD pins. */
901 qemu_irq *irq;
902
903 /* Current IRQ levels. Used internally by the generic PCI code. */
904 int irq_state[4];
905 };
906
907 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
908 int instance_size, int devfn,
909 PCIConfigReadFunc *config_read,
910 PCIConfigWriteFunc *config_write);
911
912 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
913 uint32_t size, int type,
914 PCIMapIORegionFunc *map_func);
915
916 uint32_t pci_default_read_config(PCIDevice *d,
917 uint32_t address, int len);
918 void pci_default_write_config(PCIDevice *d,
919 uint32_t address, uint32_t val, int len);
920 void pci_device_save(PCIDevice *s, QEMUFile *f);
921 int pci_device_load(PCIDevice *s, QEMUFile *f);
922
923 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
924 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
925 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
926 qemu_irq *pic, int devfn_min, int nirq);
927
928 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
929 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
930 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
931 int pci_bus_num(PCIBus *s);
932 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
933
934 void pci_info(void);
935 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
936 pci_map_irq_fn map_irq, const char *name);
937
938 /* prep_pci.c */
939 PCIBus *pci_prep_init(qemu_irq *pic);
940
941 /* apb_pci.c */
942 PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
943 qemu_irq *pic);
944
945 PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
946
947 /* piix_pci.c */
948 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
949 void i440fx_set_smm(PCIDevice *d, int val);
950 int piix3_init(PCIBus *bus, int devfn);
951 void i440fx_init_memory_mappings(PCIDevice *d);
952
953 int piix4_init(PCIBus *bus, int devfn);
954
955 /* openpic.c */
956 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
957 enum {
958 OPENPIC_OUTPUT_INT = 0, /* IRQ */
959 OPENPIC_OUTPUT_CINT, /* critical IRQ */
960 OPENPIC_OUTPUT_MCK, /* Machine check event */
961 OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
962 OPENPIC_OUTPUT_RESET, /* Core reset event */
963 OPENPIC_OUTPUT_NB,
964 };
965 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
966 qemu_irq **irqs, qemu_irq irq_out);
967
968 /* gt64xxx.c */
969 PCIBus *pci_gt64120_init(qemu_irq *pic);
970
971 #ifdef HAS_AUDIO
972 struct soundhw {
973 const char *name;
974 const char *descr;
975 int enabled;
976 int isa;
977 union {
978 int (*init_isa) (AudioState *s, qemu_irq *pic);
979 int (*init_pci) (PCIBus *bus, AudioState *s);
980 } init;
981 };
982
983 extern struct soundhw soundhw[];
984 #endif
985
986 /* vga.c */
987
988 #ifndef TARGET_SPARC
989 #define VGA_RAM_SIZE (8192 * 1024)
990 #else
991 #define VGA_RAM_SIZE (9 * 1024 * 1024)
992 #endif
993
994 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
995 unsigned long vga_ram_offset, int vga_ram_size);
996 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
997 unsigned long vga_ram_offset, int vga_ram_size,
998 unsigned long vga_bios_offset, int vga_bios_size);
999 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
1000 unsigned long vga_ram_offset, int vga_ram_size,
1001 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
1002 int it_shift);
1003
1004 /* cirrus_vga.c */
1005 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1006 unsigned long vga_ram_offset, int vga_ram_size);
1007 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
1008 unsigned long vga_ram_offset, int vga_ram_size);
1009
1010 /* vmware_vga.c */
1011 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1012 unsigned long vga_ram_offset, int vga_ram_size);
1013
1014 /* ide.c */
1015 #define MAX_DISKS 4
1016
1017 extern BlockDriverState *bs_table[MAX_DISKS + 1];
1018 extern BlockDriverState *sd_bdrv;
1019 extern BlockDriverState *mtd_bdrv;
1020
1021 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
1022 BlockDriverState *hd0, BlockDriverState *hd1);
1023 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
1024 int secondary_ide_enabled);
1025 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1026 qemu_irq *pic);
1027 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1028 qemu_irq *pic);
1029
1030 /* cdrom.c */
1031 int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
1032 int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
1033
1034 /* ds1225y.c */
1035 typedef struct ds1225y_t ds1225y_t;
1036 ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1037
1038 /* es1370.c */
1039 int es1370_init (PCIBus *bus, AudioState *s);
1040
1041 /* sb16.c */
1042 int SB16_init (AudioState *s, qemu_irq *pic);
1043
1044 /* adlib.c */
1045 int Adlib_init (AudioState *s, qemu_irq *pic);
1046
1047 /* gus.c */
1048 int GUS_init (AudioState *s, qemu_irq *pic);
1049
1050 /* dma.c */
1051 typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1052 int DMA_get_channel_mode (int nchan);
1053 int DMA_read_memory (int nchan, void *buf, int pos, int size);
1054 int DMA_write_memory (int nchan, void *buf, int pos, int size);
1055 void DMA_hold_DREQ (int nchan);
1056 void DMA_release_DREQ (int nchan);
1057 void DMA_schedule(int nchan);
1058 void DMA_run (void);
1059 void DMA_init (int high_page_enable);
1060 void DMA_register_channel (int nchan,
1061 DMA_transfer_handler transfer_handler,
1062 void *opaque);
1063 /* fdc.c */
1064 #define MAX_FD 2
1065 extern BlockDriverState *fd_table[MAX_FD];
1066
1067 typedef struct fdctrl_t fdctrl_t;
1068
1069 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1070 target_phys_addr_t io_base,
1071 BlockDriverState **fds);
1072 fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1073 BlockDriverState **fds);
1074 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1075
1076 /* eepro100.c */
1077
1078 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1079 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1080 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1081
1082 /* ne2000.c */
1083
1084 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1085 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1086
1087 /* rtl8139.c */
1088
1089 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1090
1091 /* pcnet.c */
1092
1093 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1094 void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1095 qemu_irq irq, qemu_irq *reset);
1096
1097 /* mipsnet.c */
1098 void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
1099
1100 /* vmmouse.c */
1101 void *vmmouse_init(void *m);
1102
1103 /* vmport.c */
1104 #ifdef TARGET_I386
1105 void vmport_init(CPUState *env);
1106 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
1107 #endif
1108
1109 /* pckbd.c */
1110
1111 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1112 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1113 target_phys_addr_t base, int it_shift);
1114
1115 /* mc146818rtc.c */
1116
1117 typedef struct RTCState RTCState;
1118
1119 RTCState *rtc_init(int base, qemu_irq irq);
1120 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1121 void rtc_set_memory(RTCState *s, int addr, int val);
1122 void rtc_set_date(RTCState *s, const struct tm *tm);
1123
1124 /* serial.c */
1125
1126 typedef struct SerialState SerialState;
1127 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1128 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1129 qemu_irq irq, CharDriverState *chr,
1130 int ioregister);
1131 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1132 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1133 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1134 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1135 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1136 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1137
1138 /* parallel.c */
1139
1140 typedef struct ParallelState ParallelState;
1141 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1142 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1143
1144 /* i8259.c */
1145
1146 typedef struct PicState2 PicState2;
1147 extern PicState2 *isa_pic;
1148 void pic_set_irq(int irq, int level);
1149 void pic_set_irq_new(void *opaque, int irq, int level);
1150 qemu_irq *i8259_init(qemu_irq parent_irq);
1151 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1152 void *alt_irq_opaque);
1153 int pic_read_irq(PicState2 *s);
1154 void pic_update_irq(PicState2 *s);
1155 uint32_t pic_intack_read(PicState2 *s);
1156 void pic_info(void);
1157 void irq_info(void);
1158
1159 /* APIC */
1160 typedef struct IOAPICState IOAPICState;
1161
1162 int apic_init(CPUState *env);
1163 int apic_accept_pic_intr(CPUState *env);
1164 int apic_get_interrupt(CPUState *env);
1165 IOAPICState *ioapic_init(void);
1166 void ioapic_set_irq(void *opaque, int vector, int level);
1167
1168 /* i8254.c */
1169
1170 #define PIT_FREQ 1193182
1171
1172 typedef struct PITState PITState;
1173
1174 PITState *pit_init(int base, qemu_irq irq);
1175 void pit_set_gate(PITState *pit, int channel, int val);
1176 int pit_get_gate(PITState *pit, int channel);
1177 int pit_get_initial_count(PITState *pit, int channel);
1178 int pit_get_mode(PITState *pit, int channel);
1179 int pit_get_out(PITState *pit, int channel, int64_t current_time);
1180
1181 /* jazz_led.c */
1182 extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1183
1184 /* pcspk.c */
1185 void pcspk_init(PITState *);
1186 int pcspk_audio_init(AudioState *, qemu_irq *pic);
1187
1188 #include "hw/i2c.h"
1189
1190 #include "hw/smbus.h"
1191
1192 /* acpi.c */
1193 extern int acpi_enabled;
1194 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1195 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1196 void acpi_bios_init(void);
1197
1198 /* Axis ETRAX. */
1199 extern QEMUMachine bareetraxfs_machine;
1200
1201 /* pc.c */
1202 extern QEMUMachine pc_machine;
1203 extern QEMUMachine isapc_machine;
1204 extern int fd_bootchk;
1205
1206 void ioport_set_a20(int enable);
1207 int ioport_get_a20(void);
1208
1209 /* ppc.c */
1210 extern QEMUMachine prep_machine;
1211 extern QEMUMachine core99_machine;
1212 extern QEMUMachine heathrow_machine;
1213 extern QEMUMachine ref405ep_machine;
1214 extern QEMUMachine taihu_machine;
1215
1216 /* mips_r4k.c */
1217 extern QEMUMachine mips_machine;
1218
1219 /* mips_malta.c */
1220 extern QEMUMachine mips_malta_machine;
1221
1222 /* mips_pica61.c */
1223 extern QEMUMachine mips_pica61_machine;
1224
1225 /* mips_mipssim.c */
1226 extern QEMUMachine mips_mipssim_machine;
1227
1228 /* mips_int.c */
1229 extern void cpu_mips_irq_init_cpu(CPUState *env);
1230
1231 /* mips_timer.c */
1232 extern void cpu_mips_clock_init(CPUState *);
1233 extern void cpu_mips_irqctrl_init (void);
1234
1235 /* shix.c */
1236 extern QEMUMachine shix_machine;
1237
1238 /* r2d.c */
1239 extern QEMUMachine r2d_machine;
1240
1241 #ifdef TARGET_PPC
1242 /* PowerPC hardware exceptions management helpers */
1243 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1244 typedef struct clk_setup_t clk_setup_t;
1245 struct clk_setup_t {
1246 clk_setup_cb cb;
1247 void *opaque;
1248 };
1249 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1250 {
1251 if (clk->cb != NULL)
1252 (*clk->cb)(clk->opaque, freq);
1253 }
1254
1255 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1256 /* Embedded PowerPC DCR management */
1257 typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1258 typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1259 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1260 int (*dcr_write_error)(int dcrn));
1261 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1262 dcr_read_cb drc_read, dcr_write_cb dcr_write);
1263 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1264 /* Embedded PowerPC reset */
1265 void ppc40x_core_reset (CPUState *env);
1266 void ppc40x_chip_reset (CPUState *env);
1267 void ppc40x_system_reset (CPUState *env);
1268 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1269
1270 extern CPUWriteMemoryFunc *PPC_io_write[];
1271 extern CPUReadMemoryFunc *PPC_io_read[];
1272 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1273 #endif
1274
1275 /* sun4m.c */
1276 extern QEMUMachine ss5_machine, ss10_machine;
1277
1278 /* iommu.c */
1279 void *iommu_init(target_phys_addr_t addr);
1280 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1281 uint8_t *buf, int len, int is_write);
1282 static inline void sparc_iommu_memory_read(void *opaque,
1283 target_phys_addr_t addr,
1284 uint8_t *buf, int len)
1285 {
1286 sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1287 }
1288
1289 static inline void sparc_iommu_memory_write(void *opaque,
1290 target_phys_addr_t addr,
1291 uint8_t *buf, int len)
1292 {
1293 sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1294 }
1295
1296 /* tcx.c */
1297 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1298 unsigned long vram_offset, int vram_size, int width, int height,
1299 int depth);
1300
1301 /* slavio_intctl.c */
1302 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1303 const uint32_t *intbit_to_level,
1304 qemu_irq **irq, qemu_irq **cpu_irq,
1305 qemu_irq **parent_irq, unsigned int cputimer);
1306 void slavio_pic_info(void *opaque);
1307 void slavio_irq_info(void *opaque);
1308
1309 /* loader.c */
1310 int get_image_size(const char *filename);
1311 int load_image(const char *filename, uint8_t *addr);
1312 int load_elf(const char *filename, int64_t virt_to_phys_addend,
1313 uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1314 int load_aout(const char *filename, uint8_t *addr);
1315 int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1316
1317 /* slavio_timer.c */
1318 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
1319 qemu_irq *cpu_irqs);
1320
1321 /* slavio_serial.c */
1322 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1323 CharDriverState *chr1, CharDriverState *chr2);
1324 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1325
1326 /* slavio_misc.c */
1327 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1328 qemu_irq irq);
1329 void slavio_set_power_fail(void *opaque, int power_failing);
1330
1331 /* esp.c */
1332 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1333 void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1334 void *dma_opaque, qemu_irq irq, qemu_irq *reset);
1335
1336 /* sparc32_dma.c */
1337 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1338 void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
1339 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1340 uint8_t *buf, int len, int do_bswap);
1341 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1342 uint8_t *buf, int len, int do_bswap);
1343 void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1344 void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1345
1346 /* cs4231.c */
1347 void cs_init(target_phys_addr_t base, int irq, void *intctl);
1348
1349 /* sun4u.c */
1350 extern QEMUMachine sun4u_machine;
1351
1352 /* NVRAM helpers */
1353 typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr);
1354 typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val);
1355 typedef struct nvram_t {
1356 void *opaque;
1357 nvram_read_t read_fn;
1358 nvram_write_t write_fn;
1359 } nvram_t;
1360
1361 #include "hw/m48t59.h"
1362
1363 void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value);
1364 uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr);
1365 void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value);
1366 uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr);
1367 void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value);
1368 uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr);
1369 void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
1370 const unsigned char *str, uint32_t max);
1371 int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max);
1372 void NVRAM_set_crc (nvram_t *nvram, uint32_t addr,
1373 uint32_t start, uint32_t count);
1374 int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
1375 const unsigned char *arch,
1376 uint32_t RAM_size, int boot_device,
1377 uint32_t kernel_image, uint32_t kernel_size,
1378 const char *cmdline,
1379 uint32_t initrd_image, uint32_t initrd_size,
1380 uint32_t NVRAM_image,
1381 int width, int height, int depth);
1382
1383 /* adb.c */
1384
1385 #define MAX_ADB_DEVICES 16
1386
1387 #define ADB_MAX_OUT_LEN 16
1388
1389 typedef struct ADBDevice ADBDevice;
1390
1391 /* buf = NULL means polling */
1392 typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1393 const uint8_t *buf, int len);
1394 typedef int ADBDeviceReset(ADBDevice *d);
1395
1396 struct ADBDevice {
1397 struct ADBBusState *bus;
1398 int devaddr;
1399 int handler;
1400 ADBDeviceRequest *devreq;
1401 ADBDeviceReset *devreset;
1402 void *opaque;
1403 };
1404
1405 typedef struct ADBBusState {
1406 ADBDevice devices[MAX_ADB_DEVICES];
1407 int nb_devices;
1408 int poll_index;
1409 } ADBBusState;
1410
1411 int adb_request(ADBBusState *s, uint8_t *buf_out,
1412 const uint8_t *buf, int len);
1413 int adb_poll(ADBBusState *s, uint8_t *buf_out);
1414
1415 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1416 ADBDeviceRequest *devreq,
1417 ADBDeviceReset *devreset,
1418 void *opaque);
1419 void adb_kbd_init(ADBBusState *bus);
1420 void adb_mouse_init(ADBBusState *bus);
1421
1422 extern ADBBusState adb_bus;
1423
1424 #include "hw/usb.h"
1425
1426 /* usb ports of the VM */
1427
1428 void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1429 usb_attachfn attach);
1430
1431 #define VM_USB_HUB_SIZE 8
1432
1433 void do_usb_add(const char *devname);
1434 void do_usb_del(const char *devname);
1435 void usb_info(void);
1436
1437 /* scsi-disk.c */
1438 enum scsi_reason {
1439 SCSI_REASON_DONE, /* Command complete. */
1440 SCSI_REASON_DATA /* Transfer complete, more data required. */
1441 };
1442
1443 typedef struct SCSIDevice SCSIDevice;
1444 typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1445 uint32_t arg);
1446
1447 SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1448 int tcq,
1449 scsi_completionfn completion,
1450 void *opaque);
1451 void scsi_disk_destroy(SCSIDevice *s);
1452
1453 int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1454 /* SCSI data transfers are asynchrnonous. However, unlike the block IO
1455 layer the completion routine may be called directly by
1456 scsi_{read,write}_data. */
1457 void scsi_read_data(SCSIDevice *s, uint32_t tag);
1458 int scsi_write_data(SCSIDevice *s, uint32_t tag);
1459 void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1460 uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1461
1462 /* lsi53c895a.c */
1463 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1464 void *lsi_scsi_init(PCIBus *bus, int devfn);
1465
1466 /* integratorcp.c */
1467 extern QEMUMachine integratorcp_machine;
1468
1469 /* versatilepb.c */
1470 extern QEMUMachine versatilepb_machine;
1471 extern QEMUMachine versatileab_machine;
1472
1473 /* realview.c */
1474 extern QEMUMachine realview_machine;
1475
1476 /* spitz.c */
1477 extern QEMUMachine akitapda_machine;
1478 extern QEMUMachine spitzpda_machine;
1479 extern QEMUMachine borzoipda_machine;
1480 extern QEMUMachine terrierpda_machine;
1481
1482 /* palm.c */
1483 extern QEMUMachine palmte_machine;
1484
1485 /* ps2.c */
1486 void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1487 void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1488 void ps2_write_mouse(void *, int val);
1489 void ps2_write_keyboard(void *, int val);
1490 uint32_t ps2_read_data(void *);
1491 void ps2_queue(void *, int b);
1492 void ps2_keyboard_set_translation(void *opaque, int mode);
1493 void ps2_mouse_fake_event(void *opaque);
1494
1495 /* smc91c111.c */
1496 void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1497
1498 /* pl031.c */
1499 void pl031_init(uint32_t base, qemu_irq irq);
1500
1501 /* pl110.c */
1502 void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1503
1504 /* pl011.c */
1505 void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1506
1507 /* pl050.c */
1508 void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1509
1510 /* pl080.c */
1511 void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1512
1513 /* pl181.c */
1514 void pl181_init(uint32_t base, BlockDriverState *bd,
1515 qemu_irq irq0, qemu_irq irq1);
1516
1517 /* pl190.c */
1518 qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1519
1520 /* arm-timer.c */
1521 void sp804_init(uint32_t base, qemu_irq irq);
1522 void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1523
1524 /* arm_sysctl.c */
1525 void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1526
1527 /* arm_gic.c */
1528 qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1529
1530 /* arm_boot.c */
1531
1532 void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1533 const char *kernel_cmdline, const char *initrd_filename,
1534 int board_id, target_phys_addr_t loader_start);
1535
1536 /* sh7750.c */
1537 struct SH7750State;
1538
1539 struct SH7750State *sh7750_init(CPUState * cpu);
1540
1541 typedef struct {
1542 /* The callback will be triggered if any of the designated lines change */
1543 uint16_t portamask_trigger;
1544 uint16_t portbmask_trigger;
1545 /* Return 0 if no action was taken */
1546 int (*port_change_cb) (uint16_t porta, uint16_t portb,
1547 uint16_t * periph_pdtra,
1548 uint16_t * periph_portdira,
1549 uint16_t * periph_pdtrb,
1550 uint16_t * periph_portdirb);
1551 } sh7750_io_device;
1552
1553 int sh7750_register_io_device(struct SH7750State *s,
1554 sh7750_io_device * device);
1555 /* sh_timer.c */
1556 #define TMU012_FEAT_TOCR (1 << 0)
1557 #define TMU012_FEAT_3CHAN (1 << 1)
1558 #define TMU012_FEAT_EXTCLK (1 << 2)
1559 void tmu012_init(uint32_t base, int feat, uint32_t freq);
1560
1561 /* sh_serial.c */
1562 #define SH_SERIAL_FEAT_SCIF (1 << 0)
1563 void sh_serial_init (target_phys_addr_t base, int feat,
1564 uint32_t freq, CharDriverState *chr);
1565
1566 /* tc58128.c */
1567 int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1568
1569 /* NOR flash devices */
1570 #define MAX_PFLASH 4
1571 extern BlockDriverState *pflash_table[MAX_PFLASH];
1572 typedef struct pflash_t pflash_t;
1573
1574 pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1575 BlockDriverState *bs,
1576 uint32_t sector_len, int nb_blocs, int width,
1577 uint16_t id0, uint16_t id1,
1578 uint16_t id2, uint16_t id3);
1579
1580 /* nand.c */
1581 struct nand_flash_s;
1582 struct nand_flash_s *nand_init(int manf_id, int chip_id);
1583 void nand_done(struct nand_flash_s *s);
1584 void nand_setpins(struct nand_flash_s *s,
1585 int cle, int ale, int ce, int wp, int gnd);
1586 void nand_getpins(struct nand_flash_s *s, int *rb);
1587 void nand_setio(struct nand_flash_s *s, uint8_t value);
1588 uint8_t nand_getio(struct nand_flash_s *s);
1589
1590 #define NAND_MFR_TOSHIBA 0x98
1591 #define NAND_MFR_SAMSUNG 0xec
1592 #define NAND_MFR_FUJITSU 0x04
1593 #define NAND_MFR_NATIONAL 0x8f
1594 #define NAND_MFR_RENESAS 0x07
1595 #define NAND_MFR_STMICRO 0x20
1596 #define NAND_MFR_HYNIX 0xad
1597 #define NAND_MFR_MICRON 0x2c
1598
1599 /* ecc.c */
1600 struct ecc_state_s {
1601 uint8_t cp; /* Column parity */
1602 uint16_t lp[2]; /* Line parity */
1603 uint16_t count;
1604 };
1605
1606 uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
1607 void ecc_reset(struct ecc_state_s *s);
1608 void ecc_put(QEMUFile *f, struct ecc_state_s *s);
1609 void ecc_get(QEMUFile *f, struct ecc_state_s *s);
1610
1611 /* GPIO */
1612 typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1613
1614 /* ads7846.c */
1615 struct ads7846_state_s;
1616 uint32_t ads7846_read(void *opaque);
1617 void ads7846_write(void *opaque, uint32_t value);
1618 struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1619
1620 /* max111x.c */
1621 struct max111x_s;
1622 uint32_t max111x_read(void *opaque);
1623 void max111x_write(void *opaque, uint32_t value);
1624 struct max111x_s *max1110_init(qemu_irq cb);
1625 struct max111x_s *max1111_init(qemu_irq cb);
1626 void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1627
1628 /* PCMCIA/Cardbus */
1629
1630 struct pcmcia_socket_s {
1631 qemu_irq irq;
1632 int attached;
1633 const char *slot_string;
1634 const char *card_string;
1635 };
1636
1637 void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1638 void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1639 void pcmcia_info(void);
1640
1641 struct pcmcia_card_s {
1642 void *state;
1643 struct pcmcia_socket_s *slot;
1644 int (*attach)(void *state);
1645 int (*detach)(void *state);
1646 const uint8_t *cis;
1647 int cis_len;
1648
1649 /* Only valid if attached */
1650 uint8_t (*attr_read)(void *state, uint32_t address);
1651 void (*attr_write)(void *state, uint32_t address, uint8_t value);
1652 uint16_t (*common_read)(void *state, uint32_t address);
1653 void (*common_write)(void *state, uint32_t address, uint16_t value);
1654 uint16_t (*io_read)(void *state, uint32_t address);
1655 void (*io_write)(void *state, uint32_t address, uint16_t value);
1656 };
1657
1658 #define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */
1659 #define CISTPL_NO_LINK 0x14 /* No Link Tuple */
1660 #define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */
1661 #define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */
1662 #define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */
1663 #define CISTPL_CONFIG 0x1a /* Configuration Tuple */
1664 #define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */
1665 #define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */
1666 #define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */
1667 #define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */
1668 #define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */
1669 #define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */
1670 #define CISTPL_FUNCID 0x21 /* Function ID Tuple */
1671 #define CISTPL_FUNCE 0x22 /* Function Extension Tuple */
1672 #define CISTPL_END 0xff /* Tuple End */
1673 #define CISTPL_ENDMARK 0xff
1674
1675 /* dscm1xxxx.c */
1676 struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1677
1678 /* ptimer.c */
1679 typedef struct ptimer_state ptimer_state;
1680 typedef void (*ptimer_cb)(void *opaque);
1681
1682 ptimer_state *ptimer_init(QEMUBH *bh);
1683 void ptimer_set_period(ptimer_state *s, int64_t period);
1684 void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1685 void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1686 uint64_t ptimer_get_count(ptimer_state *s);
1687 void ptimer_set_count(ptimer_state *s, uint64_t count);
1688 void ptimer_run(ptimer_state *s, int oneshot);
1689 void ptimer_stop(ptimer_state *s);
1690 void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1691 void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1692
1693 #include "hw/pxa.h"
1694
1695 #include "hw/omap.h"
1696
1697 /* tsc210x.c */
1698 struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio);
1699 struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip);
1700
1701 /* mcf_uart.c */
1702 uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1703 void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1704 void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1705 void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1706 CharDriverState *chr);
1707
1708 /* mcf_intc.c */
1709 qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1710
1711 /* mcf_fec.c */
1712 void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1713
1714 /* mcf5206.c */
1715 qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1716
1717 /* an5206.c */
1718 extern QEMUMachine an5206_machine;
1719
1720 /* mcf5208.c */
1721 extern QEMUMachine mcf5208evb_machine;
1722
1723 /* dummy_m68k.c */
1724 extern QEMUMachine dummy_m68k_machine;
1725
1726 #include "gdbstub.h"
1727
1728 #endif /* defined(QEMU_TOOL) */
1729 #endif /* VL_H */
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