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1 /*
2 * QEMU System Emulator header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #ifndef VL_H
25 #define VL_H
26
27 /* we put basic includes here to avoid repeating them in device drivers */
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <stdarg.h>
31 #include <string.h>
32 #include <inttypes.h>
33 #include <limits.h>
34 #include <time.h>
35 #include <ctype.h>
36 #include <errno.h>
37 #include <unistd.h>
38 #include <fcntl.h>
39 #include <sys/stat.h>
40
41 #ifndef O_LARGEFILE
42 #define O_LARGEFILE 0
43 #endif
44 #ifndef O_BINARY
45 #define O_BINARY 0
46 #endif
47
48 #ifndef ENOMEDIUM
49 #define ENOMEDIUM ENODEV
50 #endif
51
52 #ifdef _WIN32
53 #include <windows.h>
54 #define fsync _commit
55 #define lseek _lseeki64
56 #define ENOTSUP 4096
57 extern int qemu_ftruncate64(int, int64_t);
58 #define ftruncate qemu_ftruncate64
59
60
61 static inline char *realpath(const char *path, char *resolved_path)
62 {
63 _fullpath(resolved_path, path, _MAX_PATH);
64 return resolved_path;
65 }
66
67 #define PRId64 "I64d"
68 #define PRIx64 "I64x"
69 #define PRIu64 "I64u"
70 #define PRIo64 "I64o"
71 #endif
72
73 #ifdef QEMU_TOOL
74
75 /* we use QEMU_TOOL in the command line tools which do not depend on
76 the target CPU type */
77 #include "config-host.h"
78 #include <setjmp.h>
79 #include "osdep.h"
80 #include "bswap.h"
81
82 #else
83
84 #include "audio/audio.h"
85 #include "cpu.h"
86
87 #endif /* !defined(QEMU_TOOL) */
88
89 #ifndef glue
90 #define xglue(x, y) x ## y
91 #define glue(x, y) xglue(x, y)
92 #define stringify(s) tostring(s)
93 #define tostring(s) #s
94 #endif
95
96 #ifndef MIN
97 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
98 #endif
99 #ifndef MAX
100 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
101 #endif
102
103 /* cutils.c */
104 void pstrcpy(char *buf, int buf_size, const char *str);
105 char *pstrcat(char *buf, int buf_size, const char *s);
106 int strstart(const char *str, const char *val, const char **ptr);
107 int stristart(const char *str, const char *val, const char **ptr);
108
109 /* vl.c */
110 uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
111
112 void hw_error(const char *fmt, ...);
113
114 extern const char *bios_dir;
115
116 extern int vm_running;
117 extern const char *qemu_name;
118
119 typedef struct vm_change_state_entry VMChangeStateEntry;
120 typedef void VMChangeStateHandler(void *opaque, int running);
121 typedef void VMStopHandler(void *opaque, int reason);
122
123 VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
124 void *opaque);
125 void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
126
127 int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
128 void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
129
130 void vm_start(void);
131 void vm_stop(int reason);
132
133 typedef void QEMUResetHandler(void *opaque);
134
135 void qemu_register_reset(QEMUResetHandler *func, void *opaque);
136 void qemu_system_reset_request(void);
137 void qemu_system_shutdown_request(void);
138 void qemu_system_powerdown_request(void);
139 #if !defined(TARGET_SPARC)
140 // Please implement a power failure function to signal the OS
141 #define qemu_system_powerdown() do{}while(0)
142 #else
143 void qemu_system_powerdown(void);
144 #endif
145
146 void main_loop_wait(int timeout);
147
148 extern int ram_size;
149 extern int bios_size;
150 extern int rtc_utc;
151 extern int cirrus_vga_enabled;
152 extern int vmsvga_enabled;
153 extern int graphic_width;
154 extern int graphic_height;
155 extern int graphic_depth;
156 extern const char *keyboard_layout;
157 extern int kqemu_allowed;
158 extern int win2k_install_hack;
159 extern int usb_enabled;
160 extern int smp_cpus;
161 extern int cursor_hide;
162 extern int graphic_rotate;
163 extern int no_quit;
164 extern int semihosting_enabled;
165 extern int autostart;
166 extern const char *bootp_filename;
167
168 #define MAX_OPTION_ROMS 16
169 extern const char *option_rom[MAX_OPTION_ROMS];
170 extern int nb_option_roms;
171
172 /* XXX: make it dynamic */
173 #define MAX_BIOS_SIZE (4 * 1024 * 1024)
174 #if defined (TARGET_PPC) || defined (TARGET_SPARC64)
175 #define BIOS_SIZE ((512 + 32) * 1024)
176 #elif defined(TARGET_MIPS)
177 #define BIOS_SIZE (4 * 1024 * 1024)
178 #endif
179
180 /* keyboard/mouse support */
181
182 #define MOUSE_EVENT_LBUTTON 0x01
183 #define MOUSE_EVENT_RBUTTON 0x02
184 #define MOUSE_EVENT_MBUTTON 0x04
185
186 typedef void QEMUPutKBDEvent(void *opaque, int keycode);
187 typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
188
189 typedef struct QEMUPutMouseEntry {
190 QEMUPutMouseEvent *qemu_put_mouse_event;
191 void *qemu_put_mouse_event_opaque;
192 int qemu_put_mouse_event_absolute;
193 char *qemu_put_mouse_event_name;
194
195 /* used internally by qemu for handling mice */
196 struct QEMUPutMouseEntry *next;
197 } QEMUPutMouseEntry;
198
199 void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
200 QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
201 void *opaque, int absolute,
202 const char *name);
203 void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
204
205 void kbd_put_keycode(int keycode);
206 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
207 int kbd_mouse_is_absolute(void);
208
209 void do_info_mice(void);
210 void do_mouse_set(int index);
211
212 /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
213 constants) */
214 #define QEMU_KEY_ESC1(c) ((c) | 0xe100)
215 #define QEMU_KEY_BACKSPACE 0x007f
216 #define QEMU_KEY_UP QEMU_KEY_ESC1('A')
217 #define QEMU_KEY_DOWN QEMU_KEY_ESC1('B')
218 #define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C')
219 #define QEMU_KEY_LEFT QEMU_KEY_ESC1('D')
220 #define QEMU_KEY_HOME QEMU_KEY_ESC1(1)
221 #define QEMU_KEY_END QEMU_KEY_ESC1(4)
222 #define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5)
223 #define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6)
224 #define QEMU_KEY_DELETE QEMU_KEY_ESC1(3)
225
226 #define QEMU_KEY_CTRL_UP 0xe400
227 #define QEMU_KEY_CTRL_DOWN 0xe401
228 #define QEMU_KEY_CTRL_LEFT 0xe402
229 #define QEMU_KEY_CTRL_RIGHT 0xe403
230 #define QEMU_KEY_CTRL_HOME 0xe404
231 #define QEMU_KEY_CTRL_END 0xe405
232 #define QEMU_KEY_CTRL_PAGEUP 0xe406
233 #define QEMU_KEY_CTRL_PAGEDOWN 0xe407
234
235 void kbd_put_keysym(int keysym);
236
237 /* async I/O support */
238
239 typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
240 typedef int IOCanRWHandler(void *opaque);
241 typedef void IOHandler(void *opaque);
242
243 int qemu_set_fd_handler2(int fd,
244 IOCanRWHandler *fd_read_poll,
245 IOHandler *fd_read,
246 IOHandler *fd_write,
247 void *opaque);
248 int qemu_set_fd_handler(int fd,
249 IOHandler *fd_read,
250 IOHandler *fd_write,
251 void *opaque);
252
253 /* Polling handling */
254
255 /* return TRUE if no sleep should be done afterwards */
256 typedef int PollingFunc(void *opaque);
257
258 int qemu_add_polling_cb(PollingFunc *func, void *opaque);
259 void qemu_del_polling_cb(PollingFunc *func, void *opaque);
260
261 #ifdef _WIN32
262 /* Wait objects handling */
263 typedef void WaitObjectFunc(void *opaque);
264
265 int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
266 void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
267 #endif
268
269 typedef struct QEMUBH QEMUBH;
270
271 /* character device */
272
273 #define CHR_EVENT_BREAK 0 /* serial break char */
274 #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
275 #define CHR_EVENT_RESET 2 /* new connection established */
276
277
278 #define CHR_IOCTL_SERIAL_SET_PARAMS 1
279 typedef struct {
280 int speed;
281 int parity;
282 int data_bits;
283 int stop_bits;
284 } QEMUSerialSetParams;
285
286 #define CHR_IOCTL_SERIAL_SET_BREAK 2
287
288 #define CHR_IOCTL_PP_READ_DATA 3
289 #define CHR_IOCTL_PP_WRITE_DATA 4
290 #define CHR_IOCTL_PP_READ_CONTROL 5
291 #define CHR_IOCTL_PP_WRITE_CONTROL 6
292 #define CHR_IOCTL_PP_READ_STATUS 7
293 #define CHR_IOCTL_PP_EPP_READ_ADDR 8
294 #define CHR_IOCTL_PP_EPP_READ 9
295 #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
296 #define CHR_IOCTL_PP_EPP_WRITE 11
297
298 typedef void IOEventHandler(void *opaque, int event);
299
300 typedef struct CharDriverState {
301 int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
302 void (*chr_update_read_handler)(struct CharDriverState *s);
303 int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
304 IOEventHandler *chr_event;
305 IOCanRWHandler *chr_can_read;
306 IOReadHandler *chr_read;
307 void *handler_opaque;
308 void (*chr_send_event)(struct CharDriverState *chr, int event);
309 void (*chr_close)(struct CharDriverState *chr);
310 void *opaque;
311 int focus;
312 QEMUBH *bh;
313 } CharDriverState;
314
315 CharDriverState *qemu_chr_open(const char *filename);
316 void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
317 int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
318 void qemu_chr_send_event(CharDriverState *s, int event);
319 void qemu_chr_add_handlers(CharDriverState *s,
320 IOCanRWHandler *fd_can_read,
321 IOReadHandler *fd_read,
322 IOEventHandler *fd_event,
323 void *opaque);
324 int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
325 void qemu_chr_reset(CharDriverState *s);
326 int qemu_chr_can_read(CharDriverState *s);
327 void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
328
329 /* consoles */
330
331 typedef struct DisplayState DisplayState;
332 typedef struct TextConsole TextConsole;
333
334 typedef void (*vga_hw_update_ptr)(void *);
335 typedef void (*vga_hw_invalidate_ptr)(void *);
336 typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
337
338 TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
339 vga_hw_invalidate_ptr invalidate,
340 vga_hw_screen_dump_ptr screen_dump,
341 void *opaque);
342 void vga_hw_update(void);
343 void vga_hw_invalidate(void);
344 void vga_hw_screen_dump(const char *filename);
345
346 int is_graphic_console(void);
347 CharDriverState *text_console_init(DisplayState *ds);
348 void console_select(unsigned int index);
349
350 /* serial ports */
351
352 #define MAX_SERIAL_PORTS 4
353
354 extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
355
356 /* parallel ports */
357
358 #define MAX_PARALLEL_PORTS 3
359
360 extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
361
362 struct ParallelIOArg {
363 void *buffer;
364 int count;
365 };
366
367 /* VLANs support */
368
369 typedef struct VLANClientState VLANClientState;
370
371 struct VLANClientState {
372 IOReadHandler *fd_read;
373 /* Packets may still be sent if this returns zero. It's used to
374 rate-limit the slirp code. */
375 IOCanRWHandler *fd_can_read;
376 void *opaque;
377 struct VLANClientState *next;
378 struct VLANState *vlan;
379 char info_str[256];
380 };
381
382 typedef struct VLANState {
383 int id;
384 VLANClientState *first_client;
385 struct VLANState *next;
386 } VLANState;
387
388 VLANState *qemu_find_vlan(int id);
389 VLANClientState *qemu_new_vlan_client(VLANState *vlan,
390 IOReadHandler *fd_read,
391 IOCanRWHandler *fd_can_read,
392 void *opaque);
393 int qemu_can_send_packet(VLANClientState *vc);
394 void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
395 void qemu_handler_true(void *opaque);
396
397 void do_info_network(void);
398
399 /* TAP win32 */
400 int tap_win32_init(VLANState *vlan, const char *ifname);
401
402 /* NIC info */
403
404 #define MAX_NICS 8
405
406 typedef struct NICInfo {
407 uint8_t macaddr[6];
408 const char *model;
409 VLANState *vlan;
410 } NICInfo;
411
412 extern int nb_nics;
413 extern NICInfo nd_table[MAX_NICS];
414
415 /* timers */
416
417 typedef struct QEMUClock QEMUClock;
418 typedef struct QEMUTimer QEMUTimer;
419 typedef void QEMUTimerCB(void *opaque);
420
421 /* The real time clock should be used only for stuff which does not
422 change the virtual machine state, as it is run even if the virtual
423 machine is stopped. The real time clock has a frequency of 1000
424 Hz. */
425 extern QEMUClock *rt_clock;
426
427 /* The virtual clock is only run during the emulation. It is stopped
428 when the virtual machine is stopped. Virtual timers use a high
429 precision clock, usually cpu cycles (use ticks_per_sec). */
430 extern QEMUClock *vm_clock;
431
432 int64_t qemu_get_clock(QEMUClock *clock);
433
434 QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
435 void qemu_free_timer(QEMUTimer *ts);
436 void qemu_del_timer(QEMUTimer *ts);
437 void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
438 int qemu_timer_pending(QEMUTimer *ts);
439
440 extern int64_t ticks_per_sec;
441 extern int pit_min_timer_count;
442
443 int64_t cpu_get_ticks(void);
444 void cpu_enable_ticks(void);
445 void cpu_disable_ticks(void);
446
447 /* VM Load/Save */
448
449 typedef struct QEMUFile QEMUFile;
450
451 QEMUFile *qemu_fopen(const char *filename, const char *mode);
452 void qemu_fflush(QEMUFile *f);
453 void qemu_fclose(QEMUFile *f);
454 void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
455 void qemu_put_byte(QEMUFile *f, int v);
456 void qemu_put_be16(QEMUFile *f, unsigned int v);
457 void qemu_put_be32(QEMUFile *f, unsigned int v);
458 void qemu_put_be64(QEMUFile *f, uint64_t v);
459 int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
460 int qemu_get_byte(QEMUFile *f);
461 unsigned int qemu_get_be16(QEMUFile *f);
462 unsigned int qemu_get_be32(QEMUFile *f);
463 uint64_t qemu_get_be64(QEMUFile *f);
464
465 static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
466 {
467 qemu_put_be64(f, *pv);
468 }
469
470 static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
471 {
472 qemu_put_be32(f, *pv);
473 }
474
475 static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
476 {
477 qemu_put_be16(f, *pv);
478 }
479
480 static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
481 {
482 qemu_put_byte(f, *pv);
483 }
484
485 static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
486 {
487 *pv = qemu_get_be64(f);
488 }
489
490 static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
491 {
492 *pv = qemu_get_be32(f);
493 }
494
495 static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
496 {
497 *pv = qemu_get_be16(f);
498 }
499
500 static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
501 {
502 *pv = qemu_get_byte(f);
503 }
504
505 #if TARGET_LONG_BITS == 64
506 #define qemu_put_betl qemu_put_be64
507 #define qemu_get_betl qemu_get_be64
508 #define qemu_put_betls qemu_put_be64s
509 #define qemu_get_betls qemu_get_be64s
510 #else
511 #define qemu_put_betl qemu_put_be32
512 #define qemu_get_betl qemu_get_be32
513 #define qemu_put_betls qemu_put_be32s
514 #define qemu_get_betls qemu_get_be32s
515 #endif
516
517 int64_t qemu_ftell(QEMUFile *f);
518 int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
519
520 typedef void SaveStateHandler(QEMUFile *f, void *opaque);
521 typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
522
523 int register_savevm(const char *idstr,
524 int instance_id,
525 int version_id,
526 SaveStateHandler *save_state,
527 LoadStateHandler *load_state,
528 void *opaque);
529 void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
530 void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
531
532 void cpu_save(QEMUFile *f, void *opaque);
533 int cpu_load(QEMUFile *f, void *opaque, int version_id);
534
535 void do_savevm(const char *name);
536 void do_loadvm(const char *name);
537 void do_delvm(const char *name);
538 void do_info_snapshots(void);
539
540 /* bottom halves */
541 typedef void QEMUBHFunc(void *opaque);
542
543 QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
544 void qemu_bh_schedule(QEMUBH *bh);
545 void qemu_bh_cancel(QEMUBH *bh);
546 void qemu_bh_delete(QEMUBH *bh);
547 int qemu_bh_poll(void);
548
549 /* block.c */
550 typedef struct BlockDriverState BlockDriverState;
551 typedef struct BlockDriver BlockDriver;
552
553 extern BlockDriver bdrv_raw;
554 extern BlockDriver bdrv_host_device;
555 extern BlockDriver bdrv_cow;
556 extern BlockDriver bdrv_qcow;
557 extern BlockDriver bdrv_vmdk;
558 extern BlockDriver bdrv_cloop;
559 extern BlockDriver bdrv_dmg;
560 extern BlockDriver bdrv_bochs;
561 extern BlockDriver bdrv_vpc;
562 extern BlockDriver bdrv_vvfat;
563 extern BlockDriver bdrv_qcow2;
564
565 typedef struct BlockDriverInfo {
566 /* in bytes, 0 if irrelevant */
567 int cluster_size;
568 /* offset at which the VM state can be saved (0 if not possible) */
569 int64_t vm_state_offset;
570 } BlockDriverInfo;
571
572 typedef struct QEMUSnapshotInfo {
573 char id_str[128]; /* unique snapshot id */
574 /* the following fields are informative. They are not needed for
575 the consistency of the snapshot */
576 char name[256]; /* user choosen name */
577 uint32_t vm_state_size; /* VM state info size */
578 uint32_t date_sec; /* UTC date of the snapshot */
579 uint32_t date_nsec;
580 uint64_t vm_clock_nsec; /* VM clock relative to boot */
581 } QEMUSnapshotInfo;
582
583 #define BDRV_O_RDONLY 0x0000
584 #define BDRV_O_RDWR 0x0002
585 #define BDRV_O_ACCESS 0x0003
586 #define BDRV_O_CREAT 0x0004 /* create an empty file */
587 #define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */
588 #define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to
589 use a disk image format on top of
590 it (default for
591 bdrv_file_open()) */
592
593 void bdrv_init(void);
594 BlockDriver *bdrv_find_format(const char *format_name);
595 int bdrv_create(BlockDriver *drv,
596 const char *filename, int64_t size_in_sectors,
597 const char *backing_file, int flags);
598 BlockDriverState *bdrv_new(const char *device_name);
599 void bdrv_delete(BlockDriverState *bs);
600 int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
601 int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
602 int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
603 BlockDriver *drv);
604 void bdrv_close(BlockDriverState *bs);
605 int bdrv_read(BlockDriverState *bs, int64_t sector_num,
606 uint8_t *buf, int nb_sectors);
607 int bdrv_write(BlockDriverState *bs, int64_t sector_num,
608 const uint8_t *buf, int nb_sectors);
609 int bdrv_pread(BlockDriverState *bs, int64_t offset,
610 void *buf, int count);
611 int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
612 const void *buf, int count);
613 int bdrv_truncate(BlockDriverState *bs, int64_t offset);
614 int64_t bdrv_getlength(BlockDriverState *bs);
615 void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
616 int bdrv_commit(BlockDriverState *bs);
617 void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
618 /* async block I/O */
619 typedef struct BlockDriverAIOCB BlockDriverAIOCB;
620 typedef void BlockDriverCompletionFunc(void *opaque, int ret);
621
622 BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
623 uint8_t *buf, int nb_sectors,
624 BlockDriverCompletionFunc *cb, void *opaque);
625 BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
626 const uint8_t *buf, int nb_sectors,
627 BlockDriverCompletionFunc *cb, void *opaque);
628 void bdrv_aio_cancel(BlockDriverAIOCB *acb);
629
630 void qemu_aio_init(void);
631 void qemu_aio_poll(void);
632 void qemu_aio_flush(void);
633 void qemu_aio_wait_start(void);
634 void qemu_aio_wait(void);
635 void qemu_aio_wait_end(void);
636
637 int qemu_key_check(BlockDriverState *bs, const char *name);
638
639 /* Ensure contents are flushed to disk. */
640 void bdrv_flush(BlockDriverState *bs);
641
642 #define BDRV_TYPE_HD 0
643 #define BDRV_TYPE_CDROM 1
644 #define BDRV_TYPE_FLOPPY 2
645 #define BIOS_ATA_TRANSLATION_AUTO 0
646 #define BIOS_ATA_TRANSLATION_NONE 1
647 #define BIOS_ATA_TRANSLATION_LBA 2
648 #define BIOS_ATA_TRANSLATION_LARGE 3
649 #define BIOS_ATA_TRANSLATION_RECHS 4
650
651 void bdrv_set_geometry_hint(BlockDriverState *bs,
652 int cyls, int heads, int secs);
653 void bdrv_set_type_hint(BlockDriverState *bs, int type);
654 void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
655 void bdrv_get_geometry_hint(BlockDriverState *bs,
656 int *pcyls, int *pheads, int *psecs);
657 int bdrv_get_type_hint(BlockDriverState *bs);
658 int bdrv_get_translation_hint(BlockDriverState *bs);
659 int bdrv_is_removable(BlockDriverState *bs);
660 int bdrv_is_read_only(BlockDriverState *bs);
661 int bdrv_is_inserted(BlockDriverState *bs);
662 int bdrv_media_changed(BlockDriverState *bs);
663 int bdrv_is_locked(BlockDriverState *bs);
664 void bdrv_set_locked(BlockDriverState *bs, int locked);
665 void bdrv_eject(BlockDriverState *bs, int eject_flag);
666 void bdrv_set_change_cb(BlockDriverState *bs,
667 void (*change_cb)(void *opaque), void *opaque);
668 void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
669 void bdrv_info(void);
670 BlockDriverState *bdrv_find(const char *name);
671 void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
672 int bdrv_is_encrypted(BlockDriverState *bs);
673 int bdrv_set_key(BlockDriverState *bs, const char *key);
674 void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
675 void *opaque);
676 const char *bdrv_get_device_name(BlockDriverState *bs);
677 int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
678 const uint8_t *buf, int nb_sectors);
679 int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
680
681 void bdrv_get_backing_filename(BlockDriverState *bs,
682 char *filename, int filename_size);
683 int bdrv_snapshot_create(BlockDriverState *bs,
684 QEMUSnapshotInfo *sn_info);
685 int bdrv_snapshot_goto(BlockDriverState *bs,
686 const char *snapshot_id);
687 int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
688 int bdrv_snapshot_list(BlockDriverState *bs,
689 QEMUSnapshotInfo **psn_info);
690 char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
691
692 char *get_human_readable_size(char *buf, int buf_size, int64_t size);
693 int path_is_absolute(const char *path);
694 void path_combine(char *dest, int dest_size,
695 const char *base_path,
696 const char *filename);
697
698 #ifndef QEMU_TOOL
699
700 typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
701 int boot_device,
702 DisplayState *ds, const char **fd_filename, int snapshot,
703 const char *kernel_filename, const char *kernel_cmdline,
704 const char *initrd_filename, const char *cpu_model);
705
706 typedef struct QEMUMachine {
707 const char *name;
708 const char *desc;
709 QEMUMachineInitFunc *init;
710 struct QEMUMachine *next;
711 } QEMUMachine;
712
713 int qemu_register_machine(QEMUMachine *m);
714
715 typedef void SetIRQFunc(void *opaque, int irq_num, int level);
716
717 #if defined(TARGET_PPC)
718 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
719 #endif
720
721 #if defined(TARGET_MIPS)
722 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
723 #endif
724
725 #include "hw/irq.h"
726
727 /* ISA bus */
728
729 extern target_phys_addr_t isa_mem_base;
730
731 typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
732 typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
733
734 int register_ioport_read(int start, int length, int size,
735 IOPortReadFunc *func, void *opaque);
736 int register_ioport_write(int start, int length, int size,
737 IOPortWriteFunc *func, void *opaque);
738 void isa_unassign_ioport(int start, int length);
739
740 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
741
742 /* PCI bus */
743
744 extern target_phys_addr_t pci_mem_base;
745
746 typedef struct PCIBus PCIBus;
747 typedef struct PCIDevice PCIDevice;
748
749 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
750 uint32_t address, uint32_t data, int len);
751 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
752 uint32_t address, int len);
753 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
754 uint32_t addr, uint32_t size, int type);
755
756 #define PCI_ADDRESS_SPACE_MEM 0x00
757 #define PCI_ADDRESS_SPACE_IO 0x01
758 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
759
760 typedef struct PCIIORegion {
761 uint32_t addr; /* current PCI mapping address. -1 means not mapped */
762 uint32_t size;
763 uint8_t type;
764 PCIMapIORegionFunc *map_func;
765 } PCIIORegion;
766
767 #define PCI_ROM_SLOT 6
768 #define PCI_NUM_REGIONS 7
769
770 #define PCI_DEVICES_MAX 64
771
772 #define PCI_VENDOR_ID 0x00 /* 16 bits */
773 #define PCI_DEVICE_ID 0x02 /* 16 bits */
774 #define PCI_COMMAND 0x04 /* 16 bits */
775 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
776 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
777 #define PCI_CLASS_DEVICE 0x0a /* Device class */
778 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
779 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
780 #define PCI_MIN_GNT 0x3e /* 8 bits */
781 #define PCI_MAX_LAT 0x3f /* 8 bits */
782
783 struct PCIDevice {
784 /* PCI config space */
785 uint8_t config[256];
786
787 /* the following fields are read only */
788 PCIBus *bus;
789 int devfn;
790 char name[64];
791 PCIIORegion io_regions[PCI_NUM_REGIONS];
792
793 /* do not access the following fields */
794 PCIConfigReadFunc *config_read;
795 PCIConfigWriteFunc *config_write;
796 /* ??? This is a PC-specific hack, and should be removed. */
797 int irq_index;
798
799 /* IRQ objects for the INTA-INTD pins. */
800 qemu_irq *irq;
801
802 /* Current IRQ levels. Used internally by the generic PCI code. */
803 int irq_state[4];
804 };
805
806 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
807 int instance_size, int devfn,
808 PCIConfigReadFunc *config_read,
809 PCIConfigWriteFunc *config_write);
810
811 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
812 uint32_t size, int type,
813 PCIMapIORegionFunc *map_func);
814
815 uint32_t pci_default_read_config(PCIDevice *d,
816 uint32_t address, int len);
817 void pci_default_write_config(PCIDevice *d,
818 uint32_t address, uint32_t val, int len);
819 void pci_device_save(PCIDevice *s, QEMUFile *f);
820 int pci_device_load(PCIDevice *s, QEMUFile *f);
821
822 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
823 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
824 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
825 qemu_irq *pic, int devfn_min, int nirq);
826
827 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
828 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
829 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
830 int pci_bus_num(PCIBus *s);
831 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
832
833 void pci_info(void);
834 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
835 pci_map_irq_fn map_irq, const char *name);
836
837 /* prep_pci.c */
838 PCIBus *pci_prep_init(qemu_irq *pic);
839
840 /* grackle_pci.c */
841 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
842
843 /* unin_pci.c */
844 PCIBus *pci_pmac_init(qemu_irq *pic);
845
846 /* apb_pci.c */
847 PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base,
848 qemu_irq *pic);
849
850 PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
851
852 /* piix_pci.c */
853 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
854 void i440fx_set_smm(PCIDevice *d, int val);
855 int piix3_init(PCIBus *bus, int devfn);
856 void i440fx_init_memory_mappings(PCIDevice *d);
857
858 int piix4_init(PCIBus *bus, int devfn);
859
860 /* openpic.c */
861 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
862 enum {
863 OPENPIC_OUTPUT_INT = 0, /* IRQ */
864 OPENPIC_OUTPUT_CINT, /* critical IRQ */
865 OPENPIC_OUTPUT_MCK, /* Machine check event */
866 OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
867 OPENPIC_OUTPUT_RESET, /* Core reset event */
868 OPENPIC_OUTPUT_NB,
869 };
870 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
871 qemu_irq **irqs, qemu_irq irq_out);
872
873 /* heathrow_pic.c */
874 qemu_irq *heathrow_pic_init(int *pmem_index);
875
876 /* gt64xxx.c */
877 PCIBus *pci_gt64120_init(qemu_irq *pic);
878
879 #ifdef HAS_AUDIO
880 struct soundhw {
881 const char *name;
882 const char *descr;
883 int enabled;
884 int isa;
885 union {
886 int (*init_isa) (AudioState *s, qemu_irq *pic);
887 int (*init_pci) (PCIBus *bus, AudioState *s);
888 } init;
889 };
890
891 extern struct soundhw soundhw[];
892 #endif
893
894 /* vga.c */
895
896 #ifndef TARGET_SPARC
897 #define VGA_RAM_SIZE (8192 * 1024)
898 #else
899 #define VGA_RAM_SIZE (9 * 1024 * 1024)
900 #endif
901
902 struct DisplayState {
903 uint8_t *data;
904 int linesize;
905 int depth;
906 int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
907 int width;
908 int height;
909 void *opaque;
910
911 void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
912 void (*dpy_resize)(struct DisplayState *s, int w, int h);
913 void (*dpy_refresh)(struct DisplayState *s);
914 void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
915 int dst_x, int dst_y, int w, int h);
916 void (*dpy_fill)(struct DisplayState *s, int x, int y,
917 int w, int h, uint32_t c);
918 void (*mouse_set)(int x, int y, int on);
919 void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
920 uint8_t *image, uint8_t *mask);
921 };
922
923 static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
924 {
925 s->dpy_update(s, x, y, w, h);
926 }
927
928 static inline void dpy_resize(DisplayState *s, int w, int h)
929 {
930 s->dpy_resize(s, w, h);
931 }
932
933 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
934 unsigned long vga_ram_offset, int vga_ram_size);
935 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
936 unsigned long vga_ram_offset, int vga_ram_size,
937 unsigned long vga_bios_offset, int vga_bios_size);
938 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
939 unsigned long vga_ram_offset, int vga_ram_size,
940 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
941 int it_shift);
942
943 /* cirrus_vga.c */
944 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
945 unsigned long vga_ram_offset, int vga_ram_size);
946 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
947 unsigned long vga_ram_offset, int vga_ram_size);
948
949 /* vmware_vga.c */
950 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
951 unsigned long vga_ram_offset, int vga_ram_size);
952
953 /* sdl.c */
954 void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
955
956 /* cocoa.m */
957 void cocoa_display_init(DisplayState *ds, int full_screen);
958
959 /* vnc.c */
960 void vnc_display_init(DisplayState *ds, const char *display);
961 void do_info_vnc(void);
962
963 /* x_keymap.c */
964 extern uint8_t _translate_keycode(const int key);
965
966 /* ide.c */
967 #define MAX_DISKS 4
968
969 extern BlockDriverState *bs_table[MAX_DISKS + 1];
970 extern BlockDriverState *sd_bdrv;
971 extern BlockDriverState *mtd_bdrv;
972
973 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
974 BlockDriverState *hd0, BlockDriverState *hd1);
975 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
976 int secondary_ide_enabled);
977 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
978 qemu_irq *pic);
979 int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
980
981 /* cdrom.c */
982 int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
983 int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
984
985 /* ds1225y.c */
986 typedef struct ds1225y_t ds1225y_t;
987 ds1225y_t *ds1225y_init(target_ulong mem_base, const char *filename);
988
989 /* es1370.c */
990 int es1370_init (PCIBus *bus, AudioState *s);
991
992 /* sb16.c */
993 int SB16_init (AudioState *s, qemu_irq *pic);
994
995 /* adlib.c */
996 int Adlib_init (AudioState *s, qemu_irq *pic);
997
998 /* gus.c */
999 int GUS_init (AudioState *s, qemu_irq *pic);
1000
1001 /* dma.c */
1002 typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1003 int DMA_get_channel_mode (int nchan);
1004 int DMA_read_memory (int nchan, void *buf, int pos, int size);
1005 int DMA_write_memory (int nchan, void *buf, int pos, int size);
1006 void DMA_hold_DREQ (int nchan);
1007 void DMA_release_DREQ (int nchan);
1008 void DMA_schedule(int nchan);
1009 void DMA_run (void);
1010 void DMA_init (int high_page_enable);
1011 void DMA_register_channel (int nchan,
1012 DMA_transfer_handler transfer_handler,
1013 void *opaque);
1014 /* fdc.c */
1015 #define MAX_FD 2
1016 extern BlockDriverState *fd_table[MAX_FD];
1017
1018 typedef struct fdctrl_t fdctrl_t;
1019
1020 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1021 uint32_t io_base,
1022 BlockDriverState **fds);
1023 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1024
1025 /* eepro100.c */
1026
1027 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1028 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1029 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1030
1031 /* ne2000.c */
1032
1033 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1034 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1035
1036 /* rtl8139.c */
1037
1038 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1039
1040 /* pcnet.c */
1041
1042 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1043 void pcnet_h_reset(void *opaque);
1044 void *lance_init(NICInfo *nd, uint32_t leaddr, void *dma_opaque, qemu_irq irq);
1045
1046 /* vmmouse.c */
1047 void *vmmouse_init(void *m);
1048
1049 /* pckbd.c */
1050
1051 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1052 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, target_ulong base, int it_shift);
1053
1054 /* mc146818rtc.c */
1055
1056 typedef struct RTCState RTCState;
1057
1058 RTCState *rtc_init(int base, qemu_irq irq);
1059 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1060 void rtc_set_memory(RTCState *s, int addr, int val);
1061 void rtc_set_date(RTCState *s, const struct tm *tm);
1062
1063 /* serial.c */
1064
1065 typedef struct SerialState SerialState;
1066 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1067 SerialState *serial_mm_init (target_ulong base, int it_shift,
1068 qemu_irq irq, CharDriverState *chr,
1069 int ioregister);
1070 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1071 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1072 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1073 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1074 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1075 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1076
1077 /* parallel.c */
1078
1079 typedef struct ParallelState ParallelState;
1080 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1081
1082 /* i8259.c */
1083
1084 typedef struct PicState2 PicState2;
1085 extern PicState2 *isa_pic;
1086 void pic_set_irq(int irq, int level);
1087 void pic_set_irq_new(void *opaque, int irq, int level);
1088 qemu_irq *i8259_init(qemu_irq parent_irq);
1089 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1090 void *alt_irq_opaque);
1091 int pic_read_irq(PicState2 *s);
1092 void pic_update_irq(PicState2 *s);
1093 uint32_t pic_intack_read(PicState2 *s);
1094 void pic_info(void);
1095 void irq_info(void);
1096
1097 /* APIC */
1098 typedef struct IOAPICState IOAPICState;
1099
1100 int apic_init(CPUState *env);
1101 int apic_get_interrupt(CPUState *env);
1102 IOAPICState *ioapic_init(void);
1103 void ioapic_set_irq(void *opaque, int vector, int level);
1104
1105 /* i8254.c */
1106
1107 #define PIT_FREQ 1193182
1108
1109 typedef struct PITState PITState;
1110
1111 PITState *pit_init(int base, qemu_irq irq);
1112 void pit_set_gate(PITState *pit, int channel, int val);
1113 int pit_get_gate(PITState *pit, int channel);
1114 int pit_get_initial_count(PITState *pit, int channel);
1115 int pit_get_mode(PITState *pit, int channel);
1116 int pit_get_out(PITState *pit, int channel, int64_t current_time);
1117
1118 /* pcspk.c */
1119 void pcspk_init(PITState *);
1120 int pcspk_audio_init(AudioState *, qemu_irq *pic);
1121
1122 #include "hw/smbus.h"
1123
1124 /* acpi.c */
1125 extern int acpi_enabled;
1126 void piix4_pm_init(PCIBus *bus, int devfn);
1127 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1128 void acpi_bios_init(void);
1129
1130 /* smbus_eeprom.c */
1131 SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf);
1132
1133 /* pc.c */
1134 extern QEMUMachine pc_machine;
1135 extern QEMUMachine isapc_machine;
1136 extern int fd_bootchk;
1137
1138 void ioport_set_a20(int enable);
1139 int ioport_get_a20(void);
1140
1141 /* ppc.c */
1142 extern QEMUMachine prep_machine;
1143 extern QEMUMachine core99_machine;
1144 extern QEMUMachine heathrow_machine;
1145 extern QEMUMachine ref405ep_machine;
1146 extern QEMUMachine taihu_machine;
1147
1148 /* mips_r4k.c */
1149 extern QEMUMachine mips_machine;
1150
1151 /* mips_malta.c */
1152 extern QEMUMachine mips_malta_machine;
1153
1154 /* mips_int.c */
1155 extern void cpu_mips_irq_init_cpu(CPUState *env);
1156
1157 /* mips_pica61.c */
1158 extern QEMUMachine mips_pica61_machine;
1159
1160 /* mips_timer.c */
1161 extern void cpu_mips_clock_init(CPUState *);
1162 extern void cpu_mips_irqctrl_init (void);
1163
1164 /* shix.c */
1165 extern QEMUMachine shix_machine;
1166
1167 #ifdef TARGET_PPC
1168 /* PowerPC hardware exceptions management helpers */
1169 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1170 typedef struct clk_setup_t clk_setup_t;
1171 struct clk_setup_t {
1172 clk_setup_cb cb;
1173 void *opaque;
1174 };
1175 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1176 {
1177 if (clk->cb != NULL)
1178 (*clk->cb)(clk->opaque, freq);
1179 }
1180
1181 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1182 /* Embedded PowerPC DCR management */
1183 typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1184 typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1185 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1186 int (*dcr_write_error)(int dcrn));
1187 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1188 dcr_read_cb drc_read, dcr_write_cb dcr_write);
1189 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1190 /* Embedded PowerPC reset */
1191 void ppc40x_core_reset (CPUState *env);
1192 void ppc40x_chip_reset (CPUState *env);
1193 void ppc40x_system_reset (CPUState *env);
1194 #endif
1195 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1196
1197 extern CPUWriteMemoryFunc *PPC_io_write[];
1198 extern CPUReadMemoryFunc *PPC_io_read[];
1199 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1200
1201 /* sun4m.c */
1202 extern QEMUMachine ss5_machine, ss10_machine;
1203
1204 /* iommu.c */
1205 void *iommu_init(uint32_t addr);
1206 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1207 uint8_t *buf, int len, int is_write);
1208 static inline void sparc_iommu_memory_read(void *opaque,
1209 target_phys_addr_t addr,
1210 uint8_t *buf, int len)
1211 {
1212 sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1213 }
1214
1215 static inline void sparc_iommu_memory_write(void *opaque,
1216 target_phys_addr_t addr,
1217 uint8_t *buf, int len)
1218 {
1219 sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1220 }
1221
1222 /* tcx.c */
1223 void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
1224 unsigned long vram_offset, int vram_size, int width, int height,
1225 int depth);
1226
1227 /* slavio_intctl.c */
1228 void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);
1229 void *slavio_intctl_init(uint32_t addr, uint32_t addrg,
1230 const uint32_t *intbit_to_level,
1231 qemu_irq **irq);
1232 void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
1233 void slavio_pic_info(void *opaque);
1234 void slavio_irq_info(void *opaque);
1235
1236 /* loader.c */
1237 int get_image_size(const char *filename);
1238 int load_image(const char *filename, uint8_t *addr);
1239 int load_elf(const char *filename, int64_t virt_to_phys_addend,
1240 uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1241 int load_aout(const char *filename, uint8_t *addr);
1242 int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1243
1244 /* slavio_timer.c */
1245 void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu,
1246 void *intctl);
1247
1248 /* slavio_serial.c */
1249 SerialState *slavio_serial_init(int base, qemu_irq irq, CharDriverState *chr1,
1250 CharDriverState *chr2);
1251 void slavio_serial_ms_kbd_init(int base, qemu_irq);
1252
1253 /* slavio_misc.c */
1254 void *slavio_misc_init(uint32_t base, qemu_irq irq);
1255 void slavio_set_power_fail(void *opaque, int power_failing);
1256
1257 /* esp.c */
1258 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1259 void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque);
1260 void esp_reset(void *opaque);
1261
1262 /* sparc32_dma.c */
1263 void *sparc32_dma_init(uint32_t daddr, qemu_irq espirq, qemu_irq leirq,
1264 void *iommu);
1265 void ledma_set_irq(void *opaque, int isr);
1266 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1267 uint8_t *buf, int len, int do_bswap);
1268 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1269 uint8_t *buf, int len, int do_bswap);
1270 void espdma_raise_irq(void *opaque);
1271 void espdma_clear_irq(void *opaque);
1272 void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1273 void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1274 void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque,
1275 void *lance_opaque);
1276
1277 /* cs4231.c */
1278 void cs_init(target_phys_addr_t base, int irq, void *intctl);
1279
1280 /* sun4u.c */
1281 extern QEMUMachine sun4u_machine;
1282
1283 /* NVRAM helpers */
1284 #include "hw/m48t59.h"
1285
1286 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1287 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1288 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1289 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1290 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1291 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1292 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1293 const unsigned char *str, uint32_t max);
1294 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1295 void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1296 uint32_t start, uint32_t count);
1297 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1298 const unsigned char *arch,
1299 uint32_t RAM_size, int boot_device,
1300 uint32_t kernel_image, uint32_t kernel_size,
1301 const char *cmdline,
1302 uint32_t initrd_image, uint32_t initrd_size,
1303 uint32_t NVRAM_image,
1304 int width, int height, int depth);
1305
1306 /* adb.c */
1307
1308 #define MAX_ADB_DEVICES 16
1309
1310 #define ADB_MAX_OUT_LEN 16
1311
1312 typedef struct ADBDevice ADBDevice;
1313
1314 /* buf = NULL means polling */
1315 typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1316 const uint8_t *buf, int len);
1317 typedef int ADBDeviceReset(ADBDevice *d);
1318
1319 struct ADBDevice {
1320 struct ADBBusState *bus;
1321 int devaddr;
1322 int handler;
1323 ADBDeviceRequest *devreq;
1324 ADBDeviceReset *devreset;
1325 void *opaque;
1326 };
1327
1328 typedef struct ADBBusState {
1329 ADBDevice devices[MAX_ADB_DEVICES];
1330 int nb_devices;
1331 int poll_index;
1332 } ADBBusState;
1333
1334 int adb_request(ADBBusState *s, uint8_t *buf_out,
1335 const uint8_t *buf, int len);
1336 int adb_poll(ADBBusState *s, uint8_t *buf_out);
1337
1338 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1339 ADBDeviceRequest *devreq,
1340 ADBDeviceReset *devreset,
1341 void *opaque);
1342 void adb_kbd_init(ADBBusState *bus);
1343 void adb_mouse_init(ADBBusState *bus);
1344
1345 /* cuda.c */
1346
1347 extern ADBBusState adb_bus;
1348 int cuda_init(qemu_irq irq);
1349
1350 #include "hw/usb.h"
1351
1352 /* usb ports of the VM */
1353
1354 void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1355 usb_attachfn attach);
1356
1357 #define VM_USB_HUB_SIZE 8
1358
1359 void do_usb_add(const char *devname);
1360 void do_usb_del(const char *devname);
1361 void usb_info(void);
1362
1363 /* scsi-disk.c */
1364 enum scsi_reason {
1365 SCSI_REASON_DONE, /* Command complete. */
1366 SCSI_REASON_DATA /* Transfer complete, more data required. */
1367 };
1368
1369 typedef struct SCSIDevice SCSIDevice;
1370 typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1371 uint32_t arg);
1372
1373 SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1374 int tcq,
1375 scsi_completionfn completion,
1376 void *opaque);
1377 void scsi_disk_destroy(SCSIDevice *s);
1378
1379 int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1380 /* SCSI data transfers are asynchrnonous. However, unlike the block IO
1381 layer the completion routine may be called directly by
1382 scsi_{read,write}_data. */
1383 void scsi_read_data(SCSIDevice *s, uint32_t tag);
1384 int scsi_write_data(SCSIDevice *s, uint32_t tag);
1385 void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1386 uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1387
1388 /* lsi53c895a.c */
1389 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1390 void *lsi_scsi_init(PCIBus *bus, int devfn);
1391
1392 /* integratorcp.c */
1393 extern QEMUMachine integratorcp_machine;
1394
1395 /* versatilepb.c */
1396 extern QEMUMachine versatilepb_machine;
1397 extern QEMUMachine versatileab_machine;
1398
1399 /* realview.c */
1400 extern QEMUMachine realview_machine;
1401
1402 /* spitz.c */
1403 extern QEMUMachine akitapda_machine;
1404 extern QEMUMachine spitzpda_machine;
1405 extern QEMUMachine borzoipda_machine;
1406 extern QEMUMachine terrierpda_machine;
1407
1408 /* ps2.c */
1409 void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1410 void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1411 void ps2_write_mouse(void *, int val);
1412 void ps2_write_keyboard(void *, int val);
1413 uint32_t ps2_read_data(void *);
1414 void ps2_queue(void *, int b);
1415 void ps2_keyboard_set_translation(void *opaque, int mode);
1416 void ps2_mouse_fake_event(void *opaque);
1417
1418 /* smc91c111.c */
1419 void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1420
1421 /* pl110.c */
1422 void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1423
1424 /* pl011.c */
1425 void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1426
1427 /* pl050.c */
1428 void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1429
1430 /* pl080.c */
1431 void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1432
1433 /* pl181.c */
1434 void pl181_init(uint32_t base, BlockDriverState *bd,
1435 qemu_irq irq0, qemu_irq irq1);
1436
1437 /* pl190.c */
1438 qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1439
1440 /* arm-timer.c */
1441 void sp804_init(uint32_t base, qemu_irq irq);
1442 void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1443
1444 /* arm_sysctl.c */
1445 void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1446
1447 /* arm_gic.c */
1448 qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1449
1450 /* arm_boot.c */
1451
1452 void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1453 const char *kernel_cmdline, const char *initrd_filename,
1454 int board_id, target_phys_addr_t loader_start);
1455
1456 /* sh7750.c */
1457 struct SH7750State;
1458
1459 struct SH7750State *sh7750_init(CPUState * cpu);
1460
1461 typedef struct {
1462 /* The callback will be triggered if any of the designated lines change */
1463 uint16_t portamask_trigger;
1464 uint16_t portbmask_trigger;
1465 /* Return 0 if no action was taken */
1466 int (*port_change_cb) (uint16_t porta, uint16_t portb,
1467 uint16_t * periph_pdtra,
1468 uint16_t * periph_portdira,
1469 uint16_t * periph_pdtrb,
1470 uint16_t * periph_portdirb);
1471 } sh7750_io_device;
1472
1473 int sh7750_register_io_device(struct SH7750State *s,
1474 sh7750_io_device * device);
1475 /* tc58128.c */
1476 int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1477
1478 /* NOR flash devices */
1479 #define MAX_PFLASH 4
1480 extern BlockDriverState *pflash_table[MAX_PFLASH];
1481 typedef struct pflash_t pflash_t;
1482
1483 pflash_t *pflash_register (target_ulong base, ram_addr_t off,
1484 BlockDriverState *bs,
1485 target_ulong sector_len, int nb_blocs, int width,
1486 uint16_t id0, uint16_t id1,
1487 uint16_t id2, uint16_t id3);
1488
1489 /* nand.c */
1490 struct nand_flash_s;
1491 struct nand_flash_s *nand_init(int manf_id, int chip_id);
1492 void nand_done(struct nand_flash_s *s);
1493 void nand_setpins(struct nand_flash_s *s,
1494 int cle, int ale, int ce, int wp, int gnd);
1495 void nand_getpins(struct nand_flash_s *s, int *rb);
1496 void nand_setio(struct nand_flash_s *s, uint8_t value);
1497 uint8_t nand_getio(struct nand_flash_s *s);
1498
1499 #define NAND_MFR_TOSHIBA 0x98
1500 #define NAND_MFR_SAMSUNG 0xec
1501 #define NAND_MFR_FUJITSU 0x04
1502 #define NAND_MFR_NATIONAL 0x8f
1503 #define NAND_MFR_RENESAS 0x07
1504 #define NAND_MFR_STMICRO 0x20
1505 #define NAND_MFR_HYNIX 0xad
1506 #define NAND_MFR_MICRON 0x2c
1507
1508 #include "ecc.h"
1509
1510 /* GPIO */
1511 typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1512
1513 /* ads7846.c */
1514 struct ads7846_state_s;
1515 uint32_t ads7846_read(void *opaque);
1516 void ads7846_write(void *opaque, uint32_t value);
1517 struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1518
1519 /* max111x.c */
1520 struct max111x_s;
1521 uint32_t max111x_read(void *opaque);
1522 void max111x_write(void *opaque, uint32_t value);
1523 struct max111x_s *max1110_init(qemu_irq cb);
1524 struct max111x_s *max1111_init(qemu_irq cb);
1525 void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1526
1527 /* PCMCIA/Cardbus */
1528
1529 struct pcmcia_socket_s {
1530 qemu_irq irq;
1531 int attached;
1532 const char *slot_string;
1533 const char *card_string;
1534 };
1535
1536 void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1537 void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1538 void pcmcia_info(void);
1539
1540 struct pcmcia_card_s {
1541 void *state;
1542 struct pcmcia_socket_s *slot;
1543 int (*attach)(void *state);
1544 int (*detach)(void *state);
1545 const uint8_t *cis;
1546 int cis_len;
1547
1548 /* Only valid if attached */
1549 uint8_t (*attr_read)(void *state, uint16_t address);
1550 void (*attr_write)(void *state, uint16_t address, uint8_t value);
1551 uint16_t (*common_read)(void *state, uint16_t address);
1552 void (*common_write)(void *state, uint16_t address, uint16_t value);
1553 uint16_t (*io_read)(void *state, uint16_t address);
1554 void (*io_write)(void *state, uint16_t address, uint16_t value);
1555 };
1556
1557 #define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */
1558 #define CISTPL_NO_LINK 0x14 /* No Link Tuple */
1559 #define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */
1560 #define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */
1561 #define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */
1562 #define CISTPL_CONFIG 0x1a /* Configuration Tuple */
1563 #define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */
1564 #define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */
1565 #define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */
1566 #define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */
1567 #define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */
1568 #define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */
1569 #define CISTPL_FUNCID 0x21 /* Function ID Tuple */
1570 #define CISTPL_FUNCE 0x22 /* Function Extension Tuple */
1571 #define CISTPL_END 0xff /* Tuple End */
1572 #define CISTPL_ENDMARK 0xff
1573
1574 /* dscm1xxxx.c */
1575 struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1576
1577 #include "hw/pxa.h"
1578
1579 #include "gdbstub.h"
1580
1581 #endif /* defined(QEMU_TOOL) */
1582
1583 /* monitor.c */
1584 void monitor_init(CharDriverState *hd, int show_banner);
1585 void term_puts(const char *str);
1586 void term_vprintf(const char *fmt, va_list ap);
1587 void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1588 void term_print_filename(const char *filename);
1589 void term_flush(void);
1590 void term_print_help(void);
1591 void monitor_readline(const char *prompt, int is_password,
1592 char *buf, int buf_size);
1593
1594 /* readline.c */
1595 typedef void ReadLineFunc(void *opaque, const char *str);
1596
1597 extern int completion_index;
1598 void add_completion(const char *str);
1599 void readline_handle_byte(int ch);
1600 void readline_find_completion(const char *cmdline);
1601 const char *readline_get_history(unsigned int index);
1602 void readline_start(const char *prompt, int is_password,
1603 ReadLineFunc *readline_func, void *opaque);
1604
1605 void kqemu_record_dump(void);
1606
1607 #endif /* VL_H */
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