vl.h

   1 /*
   2  * QEMU System Emulator header
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #ifndef VL_H
  25 #define VL_H
  26
  27 /* we put basic includes here to avoid repeating them in device drivers */
  28 #include <stdlib.h>
  29 #include <stdio.h>
  30 #include <stdarg.h>
  31 #include <string.h>
  32 #include <inttypes.h>
  33 #include <limits.h>
  34 #include <time.h>
  35 #include <ctype.h>
  36 #include <errno.h>
  37 #include <unistd.h>
  38 #include <fcntl.h>
  39 #include <sys/stat.h>
  40
  41 #ifndef O_LARGEFILE
  42 #define O_LARGEFILE 0
  43 #endif
  44 #ifndef O_BINARY
  45 #define O_BINARY 0
  46 #endif
  47
  48 #ifndef ENOMEDIUM
  49 #define ENOMEDIUM ENODEV
  50 #endif
  51
  52 #ifdef _WIN32
  53 #include <windows.h>
  54 #define fsync _commit
  55 #define lseek _lseeki64
  56 #define ENOTSUP 4096
  57 extern int qemu_ftruncate64(int, int64_t);
  58 #define ftruncate qemu_ftruncate64
  59
  60
  61 static inline char *realpath(const char *path, char *resolved_path)
  62 {
  63     _fullpath(resolved_path, path, _MAX_PATH);
  64     return resolved_path;
  65 }
  66
  67 #define PRId64 "I64d"
  68 #define PRIx64 "I64x"
  69 #define PRIu64 "I64u"
  70 #define PRIo64 "I64o"
  71 #endif
  72
  73 #ifdef QEMU_TOOL
  74
  75 /* we use QEMU_TOOL in the command line tools which do not depend on
  76    the target CPU type */
  77 #include "config-host.h"
  78 #include <setjmp.h>
  79 #include "osdep.h"
  80 #include "bswap.h"
  81
  82 #else
  83
  84 #include "audio/audio.h"
  85 #include "cpu.h"
  86
  87 #endif /* !defined(QEMU_TOOL) */
  88
  89 #ifndef glue
  90 #define xglue(x, y) x ## y
  91 #define glue(x, y) xglue(x, y)
  92 #define stringify(s)    tostring(s)
  93 #define tostring(s)     #s
  94 #endif
  95
  96 #ifndef MIN
  97 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
  98 #endif
  99 #ifndef MAX
 100 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
 101 #endif
 102
 103 /* cutils.c */
 104 void pstrcpy(char *buf, int buf_size, const char *str);
 105 char *pstrcat(char *buf, int buf_size, const char *s);
 106 int strstart(const char *str, const char *val, const char **ptr);
 107 int stristart(const char *str, const char *val, const char **ptr);
 108
 109 /* vl.c */
 110 uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
 111
 112 void hw_error(const char *fmt, ...);
 113
 114 extern const char *bios_dir;
 115
 116 extern int vm_running;
 117 extern const char *qemu_name;
 118
 119 typedef struct vm_change_state_entry VMChangeStateEntry;
 120 typedef void VMChangeStateHandler(void *opaque, int running);
 121 typedef void VMStopHandler(void *opaque, int reason);
 122
 123 VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
 124                                                      void *opaque);
 125 void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
 126
 127 int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
 128 void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
 129
 130 void vm_start(void);
 131 void vm_stop(int reason);
 132
 133 typedef void QEMUResetHandler(void *opaque);
 134
 135 void qemu_register_reset(QEMUResetHandler *func, void *opaque);
 136 void qemu_system_reset_request(void);
 137 void qemu_system_shutdown_request(void);
 138 void qemu_system_powerdown_request(void);
 139 #if !defined(TARGET_SPARC)
 140 // Please implement a power failure function to signal the OS
 141 #define qemu_system_powerdown() do{}while(0)
 142 #else
 143 void qemu_system_powerdown(void);
 144 #endif
 145
 146 void main_loop_wait(int timeout);
 147
 148 extern int ram_size;
 149 extern int bios_size;
 150 extern int rtc_utc;
 151 extern int cirrus_vga_enabled;
 152 extern int vmsvga_enabled;
 153 extern int graphic_width;
 154 extern int graphic_height;
 155 extern int graphic_depth;
 156 extern const char *keyboard_layout;
 157 extern int kqemu_allowed;
 158 extern int win2k_install_hack;
 159 extern int usb_enabled;
 160 extern int smp_cpus;
 161 extern int no_quit;
 162 extern int semihosting_enabled;
 163 extern int autostart;
 164 extern const char *bootp_filename;
 165
 166 #define MAX_OPTION_ROMS 16
 167 extern const char *option_rom[MAX_OPTION_ROMS];
 168 extern int nb_option_roms;
 169
 170 /* XXX: make it dynamic */
 171 #define MAX_BIOS_SIZE (4 * 1024 * 1024)
 172 #if defined (TARGET_PPC) || defined (TARGET_SPARC64)
 173 #define BIOS_SIZE ((512 + 32) * 1024)
 174 #elif defined(TARGET_MIPS)
 175 #define BIOS_SIZE (4 * 1024 * 1024)
 176 #endif
 177
 178 /* keyboard/mouse support */
 179
 180 #define MOUSE_EVENT_LBUTTON 0x01
 181 #define MOUSE_EVENT_RBUTTON 0x02
 182 #define MOUSE_EVENT_MBUTTON 0x04
 183
 184 typedef void QEMUPutKBDEvent(void *opaque, int keycode);
 185 typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
 186
 187 typedef struct QEMUPutMouseEntry {
 188     QEMUPutMouseEvent *qemu_put_mouse_event;
 189     void *qemu_put_mouse_event_opaque;
 190     int qemu_put_mouse_event_absolute;
 191     char *qemu_put_mouse_event_name;
 192
 193     /* used internally by qemu for handling mice */
 194     struct QEMUPutMouseEntry *next;
 195 } QEMUPutMouseEntry;
 196
 197 void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
 198 QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
 199                                                 void *opaque, int absolute,
 200                                                 const char *name);
 201 void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
 202
 203 void kbd_put_keycode(int keycode);
 204 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
 205 int kbd_mouse_is_absolute(void);
 206
 207 void do_info_mice(void);
 208 void do_mouse_set(int index);
 209
 210 /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
 211    constants) */
 212 #define QEMU_KEY_ESC1(c) ((c) | 0xe100)
 213 #define QEMU_KEY_BACKSPACE  0x007f
 214 #define QEMU_KEY_UP         QEMU_KEY_ESC1('A')
 215 #define QEMU_KEY_DOWN       QEMU_KEY_ESC1('B')
 216 #define QEMU_KEY_RIGHT      QEMU_KEY_ESC1('C')
 217 #define QEMU_KEY_LEFT       QEMU_KEY_ESC1('D')
 218 #define QEMU_KEY_HOME       QEMU_KEY_ESC1(1)
 219 #define QEMU_KEY_END        QEMU_KEY_ESC1(4)
 220 #define QEMU_KEY_PAGEUP     QEMU_KEY_ESC1(5)
 221 #define QEMU_KEY_PAGEDOWN   QEMU_KEY_ESC1(6)
 222 #define QEMU_KEY_DELETE     QEMU_KEY_ESC1(3)
 223
 224 #define QEMU_KEY_CTRL_UP         0xe400
 225 #define QEMU_KEY_CTRL_DOWN       0xe401
 226 #define QEMU_KEY_CTRL_LEFT       0xe402
 227 #define QEMU_KEY_CTRL_RIGHT      0xe403
 228 #define QEMU_KEY_CTRL_HOME       0xe404
 229 #define QEMU_KEY_CTRL_END        0xe405
 230 #define QEMU_KEY_CTRL_PAGEUP     0xe406
 231 #define QEMU_KEY_CTRL_PAGEDOWN   0xe407
 232
 233 void kbd_put_keysym(int keysym);
 234
 235 /* async I/O support */
 236
 237 typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
 238 typedef int IOCanRWHandler(void *opaque);
 239 typedef void IOHandler(void *opaque);
 240
 241 int qemu_set_fd_handler2(int fd,
 242                          IOCanRWHandler *fd_read_poll,
 243                          IOHandler *fd_read,
 244                          IOHandler *fd_write,
 245                          void *opaque);
 246 int qemu_set_fd_handler(int fd,
 247                         IOHandler *fd_read,
 248                         IOHandler *fd_write,
 249                         void *opaque);
 250
 251 /* Polling handling */
 252
 253 /* return TRUE if no sleep should be done afterwards */
 254 typedef int PollingFunc(void *opaque);
 255
 256 int qemu_add_polling_cb(PollingFunc *func, void *opaque);
 257 void qemu_del_polling_cb(PollingFunc *func, void *opaque);
 258
 259 #ifdef _WIN32
 260 /* Wait objects handling */
 261 typedef void WaitObjectFunc(void *opaque);
 262
 263 int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
 264 void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
 265 #endif
 266
 267 typedef struct QEMUBH QEMUBH;
 268
 269 /* character device */
 270
 271 #define CHR_EVENT_BREAK 0 /* serial break char */
 272 #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
 273 #define CHR_EVENT_RESET 2 /* new connection established */
 274
 275
 276 #define CHR_IOCTL_SERIAL_SET_PARAMS   1
 277 typedef struct {
 278     int speed;
 279     int parity;
 280     int data_bits;
 281     int stop_bits;
 282 } QEMUSerialSetParams;
 283
 284 #define CHR_IOCTL_SERIAL_SET_BREAK    2
 285
 286 #define CHR_IOCTL_PP_READ_DATA        3
 287 #define CHR_IOCTL_PP_WRITE_DATA       4
 288 #define CHR_IOCTL_PP_READ_CONTROL     5
 289 #define CHR_IOCTL_PP_WRITE_CONTROL    6
 290 #define CHR_IOCTL_PP_READ_STATUS      7
 291 #define CHR_IOCTL_PP_EPP_READ_ADDR    8
 292 #define CHR_IOCTL_PP_EPP_READ         9
 293 #define CHR_IOCTL_PP_EPP_WRITE_ADDR  10
 294 #define CHR_IOCTL_PP_EPP_WRITE       11
 295
 296 typedef void IOEventHandler(void *opaque, int event);
 297
 298 typedef struct CharDriverState {
 299     int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
 300     void (*chr_update_read_handler)(struct CharDriverState *s);
 301     int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
 302     IOEventHandler *chr_event;
 303     IOCanRWHandler *chr_can_read;
 304     IOReadHandler *chr_read;
 305     void *handler_opaque;
 306     void (*chr_send_event)(struct CharDriverState *chr, int event);
 307     void (*chr_close)(struct CharDriverState *chr);
 308     void *opaque;
 309     int focus;
 310     QEMUBH *bh;
 311 } CharDriverState;
 312
 313 CharDriverState *qemu_chr_open(const char *filename);
 314 void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
 315 int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
 316 void qemu_chr_send_event(CharDriverState *s, int event);
 317 void qemu_chr_add_handlers(CharDriverState *s,
 318                            IOCanRWHandler *fd_can_read,
 319                            IOReadHandler *fd_read,
 320                            IOEventHandler *fd_event,
 321                            void *opaque);
 322 int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
 323 void qemu_chr_reset(CharDriverState *s);
 324 int qemu_chr_can_read(CharDriverState *s);
 325 void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
 326
 327 /* consoles */
 328
 329 typedef struct DisplayState DisplayState;
 330 typedef struct TextConsole TextConsole;
 331
 332 typedef void (*vga_hw_update_ptr)(void *);
 333 typedef void (*vga_hw_invalidate_ptr)(void *);
 334 typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
 335
 336 TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
 337                                   vga_hw_invalidate_ptr invalidate,
 338                                   vga_hw_screen_dump_ptr screen_dump,
 339                                   void *opaque);
 340 void vga_hw_update(void);
 341 void vga_hw_invalidate(void);
 342 void vga_hw_screen_dump(const char *filename);
 343
 344 int is_graphic_console(void);
 345 CharDriverState *text_console_init(DisplayState *ds);
 346 void console_select(unsigned int index);
 347
 348 /* serial ports */
 349
 350 #define MAX_SERIAL_PORTS 4
 351
 352 extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
 353
 354 /* parallel ports */
 355
 356 #define MAX_PARALLEL_PORTS 3
 357
 358 extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
 359
 360 struct ParallelIOArg {
 361     void *buffer;
 362     int count;
 363 };
 364
 365 /* VLANs support */
 366
 367 typedef struct VLANClientState VLANClientState;
 368
 369 struct VLANClientState {
 370     IOReadHandler *fd_read;
 371     /* Packets may still be sent if this returns zero.  It's used to
 372        rate-limit the slirp code.  */
 373     IOCanRWHandler *fd_can_read;
 374     void *opaque;
 375     struct VLANClientState *next;
 376     struct VLANState *vlan;
 377     char info_str[256];
 378 };
 379
 380 typedef struct VLANState {
 381     int id;
 382     VLANClientState *first_client;
 383     struct VLANState *next;
 384 } VLANState;
 385
 386 VLANState *qemu_find_vlan(int id);
 387 VLANClientState *qemu_new_vlan_client(VLANState *vlan,
 388                                       IOReadHandler *fd_read,
 389                                       IOCanRWHandler *fd_can_read,
 390                                       void *opaque);
 391 int qemu_can_send_packet(VLANClientState *vc);
 392 void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
 393 void qemu_handler_true(void *opaque);
 394
 395 void do_info_network(void);
 396
 397 /* TAP win32 */
 398 int tap_win32_init(VLANState *vlan, const char *ifname);
 399
 400 /* NIC info */
 401
 402 #define MAX_NICS 8
 403
 404 typedef struct NICInfo {
 405     uint8_t macaddr[6];
 406     const char *model;
 407     VLANState *vlan;
 408 } NICInfo;
 409
 410 extern int nb_nics;
 411 extern NICInfo nd_table[MAX_NICS];
 412
 413 /* timers */
 414
 415 typedef struct QEMUClock QEMUClock;
 416 typedef struct QEMUTimer QEMUTimer;
 417 typedef void QEMUTimerCB(void *opaque);
 418
 419 /* The real time clock should be used only for stuff which does not
 420    change the virtual machine state, as it is run even if the virtual
 421    machine is stopped. The real time clock has a frequency of 1000
 422    Hz. */
 423 extern QEMUClock *rt_clock;
 424
 425 /* The virtual clock is only run during the emulation. It is stopped
 426    when the virtual machine is stopped. Virtual timers use a high
 427    precision clock, usually cpu cycles (use ticks_per_sec). */
 428 extern QEMUClock *vm_clock;
 429
 430 int64_t qemu_get_clock(QEMUClock *clock);
 431
 432 QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
 433 void qemu_free_timer(QEMUTimer *ts);
 434 void qemu_del_timer(QEMUTimer *ts);
 435 void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
 436 int qemu_timer_pending(QEMUTimer *ts);
 437
 438 extern int64_t ticks_per_sec;
 439 extern int pit_min_timer_count;
 440
 441 int64_t cpu_get_ticks(void);
 442 void cpu_enable_ticks(void);
 443 void cpu_disable_ticks(void);
 444
 445 /* VM Load/Save */
 446
 447 typedef struct QEMUFile QEMUFile;
 448
 449 QEMUFile *qemu_fopen(const char *filename, const char *mode);
 450 void qemu_fflush(QEMUFile *f);
 451 void qemu_fclose(QEMUFile *f);
 452 void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
 453 void qemu_put_byte(QEMUFile *f, int v);
 454 void qemu_put_be16(QEMUFile *f, unsigned int v);
 455 void qemu_put_be32(QEMUFile *f, unsigned int v);
 456 void qemu_put_be64(QEMUFile *f, uint64_t v);
 457 int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
 458 int qemu_get_byte(QEMUFile *f);
 459 unsigned int qemu_get_be16(QEMUFile *f);
 460 unsigned int qemu_get_be32(QEMUFile *f);
 461 uint64_t qemu_get_be64(QEMUFile *f);
 462
 463 static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
 464 {
 465     qemu_put_be64(f, *pv);
 466 }
 467
 468 static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
 469 {
 470     qemu_put_be32(f, *pv);
 471 }
 472
 473 static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
 474 {
 475     qemu_put_be16(f, *pv);
 476 }
 477
 478 static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
 479 {
 480     qemu_put_byte(f, *pv);
 481 }
 482
 483 static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
 484 {
 485     *pv = qemu_get_be64(f);
 486 }
 487
 488 static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
 489 {
 490     *pv = qemu_get_be32(f);
 491 }
 492
 493 static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
 494 {
 495     *pv = qemu_get_be16(f);
 496 }
 497
 498 static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
 499 {
 500     *pv = qemu_get_byte(f);
 501 }
 502
 503 #if TARGET_LONG_BITS == 64
 504 #define qemu_put_betl qemu_put_be64
 505 #define qemu_get_betl qemu_get_be64
 506 #define qemu_put_betls qemu_put_be64s
 507 #define qemu_get_betls qemu_get_be64s
 508 #else
 509 #define qemu_put_betl qemu_put_be32
 510 #define qemu_get_betl qemu_get_be32
 511 #define qemu_put_betls qemu_put_be32s
 512 #define qemu_get_betls qemu_get_be32s
 513 #endif
 514
 515 int64_t qemu_ftell(QEMUFile *f);
 516 int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
 517
 518 typedef void SaveStateHandler(QEMUFile *f, void *opaque);
 519 typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
 520
 521 int register_savevm(const char *idstr,
 522                     int instance_id,
 523                     int version_id,
 524                     SaveStateHandler *save_state,
 525                     LoadStateHandler *load_state,
 526                     void *opaque);
 527 void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
 528 void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
 529
 530 void cpu_save(QEMUFile *f, void *opaque);
 531 int cpu_load(QEMUFile *f, void *opaque, int version_id);
 532
 533 void do_savevm(const char *name);
 534 void do_loadvm(const char *name);
 535 void do_delvm(const char *name);
 536 void do_info_snapshots(void);
 537
 538 /* bottom halves */
 539 typedef void QEMUBHFunc(void *opaque);
 540
 541 QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
 542 void qemu_bh_schedule(QEMUBH *bh);
 543 void qemu_bh_cancel(QEMUBH *bh);
 544 void qemu_bh_delete(QEMUBH *bh);
 545 int qemu_bh_poll(void);
 546
 547 /* block.c */
 548 typedef struct BlockDriverState BlockDriverState;
 549 typedef struct BlockDriver BlockDriver;
 550
 551 extern BlockDriver bdrv_raw;
 552 extern BlockDriver bdrv_host_device;
 553 extern BlockDriver bdrv_cow;
 554 extern BlockDriver bdrv_qcow;
 555 extern BlockDriver bdrv_vmdk;
 556 extern BlockDriver bdrv_cloop;
 557 extern BlockDriver bdrv_dmg;
 558 extern BlockDriver bdrv_bochs;
 559 extern BlockDriver bdrv_vpc;
 560 extern BlockDriver bdrv_vvfat;
 561 extern BlockDriver bdrv_qcow2;
 562
 563 typedef struct BlockDriverInfo {
 564     /* in bytes, 0 if irrelevant */
 565     int cluster_size;
 566     /* offset at which the VM state can be saved (0 if not possible) */
 567     int64_t vm_state_offset;
 568 } BlockDriverInfo;
 569
 570 typedef struct QEMUSnapshotInfo {
 571     char id_str[128]; /* unique snapshot id */
 572     /* the following fields are informative. They are not needed for
 573        the consistency of the snapshot */
 574     char name[256]; /* user choosen name */
 575     uint32_t vm_state_size; /* VM state info size */
 576     uint32_t date_sec; /* UTC date of the snapshot */
 577     uint32_t date_nsec;
 578     uint64_t vm_clock_nsec; /* VM clock relative to boot */
 579 } QEMUSnapshotInfo;
 580
 581 #define BDRV_O_RDONLY      0x0000
 582 #define BDRV_O_RDWR        0x0002
 583 #define BDRV_O_ACCESS      0x0003
 584 #define BDRV_O_CREAT       0x0004 /* create an empty file */
 585 #define BDRV_O_SNAPSHOT    0x0008 /* open the file read only and save writes in a snapshot */
 586 #define BDRV_O_FILE        0x0010 /* open as a raw file (do not try to
 587                                      use a disk image format on top of
 588                                      it (default for
 589                                      bdrv_file_open()) */
 590
 591 void bdrv_init(void);
 592 BlockDriver *bdrv_find_format(const char *format_name);
 593 int bdrv_create(BlockDriver *drv,
 594                 const char *filename, int64_t size_in_sectors,
 595                 const char *backing_file, int flags);
 596 BlockDriverState *bdrv_new(const char *device_name);
 597 void bdrv_delete(BlockDriverState *bs);
 598 int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
 599 int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
 600 int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
 601                BlockDriver *drv);
 602 void bdrv_close(BlockDriverState *bs);
 603 int bdrv_read(BlockDriverState *bs, int64_t sector_num,
 604               uint8_t *buf, int nb_sectors);
 605 int bdrv_write(BlockDriverState *bs, int64_t sector_num,
 606                const uint8_t *buf, int nb_sectors);
 607 int bdrv_pread(BlockDriverState *bs, int64_t offset,
 608                void *buf, int count);
 609 int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
 610                 const void *buf, int count);
 611 int bdrv_truncate(BlockDriverState *bs, int64_t offset);
 612 int64_t bdrv_getlength(BlockDriverState *bs);
 613 void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
 614 int bdrv_commit(BlockDriverState *bs);
 615 void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
 616 /* async block I/O */
 617 typedef struct BlockDriverAIOCB BlockDriverAIOCB;
 618 typedef void BlockDriverCompletionFunc(void *opaque, int ret);
 619
 620 BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
 621                                 uint8_t *buf, int nb_sectors,
 622                                 BlockDriverCompletionFunc *cb, void *opaque);
 623 BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
 624                                  const uint8_t *buf, int nb_sectors,
 625                                  BlockDriverCompletionFunc *cb, void *opaque);
 626 void bdrv_aio_cancel(BlockDriverAIOCB *acb);
 627
 628 void qemu_aio_init(void);
 629 void qemu_aio_poll(void);
 630 void qemu_aio_flush(void);
 631 void qemu_aio_wait_start(void);
 632 void qemu_aio_wait(void);
 633 void qemu_aio_wait_end(void);
 634
 635 /* Ensure contents are flushed to disk.  */
 636 void bdrv_flush(BlockDriverState *bs);
 637
 638 #define BDRV_TYPE_HD     0
 639 #define BDRV_TYPE_CDROM  1
 640 #define BDRV_TYPE_FLOPPY 2
 641 #define BIOS_ATA_TRANSLATION_AUTO   0
 642 #define BIOS_ATA_TRANSLATION_NONE   1
 643 #define BIOS_ATA_TRANSLATION_LBA    2
 644 #define BIOS_ATA_TRANSLATION_LARGE  3
 645 #define BIOS_ATA_TRANSLATION_RECHS  4
 646
 647 void bdrv_set_geometry_hint(BlockDriverState *bs,
 648                             int cyls, int heads, int secs);
 649 void bdrv_set_type_hint(BlockDriverState *bs, int type);
 650 void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
 651 void bdrv_get_geometry_hint(BlockDriverState *bs,
 652                             int *pcyls, int *pheads, int *psecs);
 653 int bdrv_get_type_hint(BlockDriverState *bs);
 654 int bdrv_get_translation_hint(BlockDriverState *bs);
 655 int bdrv_is_removable(BlockDriverState *bs);
 656 int bdrv_is_read_only(BlockDriverState *bs);
 657 int bdrv_is_inserted(BlockDriverState *bs);
 658 int bdrv_media_changed(BlockDriverState *bs);
 659 int bdrv_is_locked(BlockDriverState *bs);
 660 void bdrv_set_locked(BlockDriverState *bs, int locked);
 661 void bdrv_eject(BlockDriverState *bs, int eject_flag);
 662 void bdrv_set_change_cb(BlockDriverState *bs,
 663                         void (*change_cb)(void *opaque), void *opaque);
 664 void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
 665 void bdrv_info(void);
 666 BlockDriverState *bdrv_find(const char *name);
 667 void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
 668 int bdrv_is_encrypted(BlockDriverState *bs);
 669 int bdrv_set_key(BlockDriverState *bs, const char *key);
 670 void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
 671                          void *opaque);
 672 const char *bdrv_get_device_name(BlockDriverState *bs);
 673 int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
 674                           const uint8_t *buf, int nb_sectors);
 675 int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
 676
 677 void bdrv_get_backing_filename(BlockDriverState *bs,
 678                                char *filename, int filename_size);
 679 int bdrv_snapshot_create(BlockDriverState *bs,
 680                          QEMUSnapshotInfo *sn_info);
 681 int bdrv_snapshot_goto(BlockDriverState *bs,
 682                        const char *snapshot_id);
 683 int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
 684 int bdrv_snapshot_list(BlockDriverState *bs,
 685                        QEMUSnapshotInfo **psn_info);
 686 char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
 687
 688 char *get_human_readable_size(char *buf, int buf_size, int64_t size);
 689 int path_is_absolute(const char *path);
 690 void path_combine(char *dest, int dest_size,
 691                   const char *base_path,
 692                   const char *filename);
 693
 694 #ifndef QEMU_TOOL
 695
 696 typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size,
 697                                  int boot_device,
 698              DisplayState *ds, const char **fd_filename, int snapshot,
 699              const char *kernel_filename, const char *kernel_cmdline,
 700              const char *initrd_filename, const char *cpu_model);
 701
 702 typedef struct QEMUMachine {
 703     const char *name;
 704     const char *desc;
 705     QEMUMachineInitFunc *init;
 706     struct QEMUMachine *next;
 707 } QEMUMachine;
 708
 709 int qemu_register_machine(QEMUMachine *m);
 710
 711 typedef void SetIRQFunc(void *opaque, int irq_num, int level);
 712
 713 #if defined(TARGET_PPC)
 714 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 715 #endif
 716
 717 #if defined(TARGET_MIPS)
 718 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 719 #endif
 720
 721 #include "hw/irq.h"
 722
 723 /* ISA bus */
 724
 725 extern target_phys_addr_t isa_mem_base;
 726
 727 typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
 728 typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
 729
 730 int register_ioport_read(int start, int length, int size,
 731                          IOPortReadFunc *func, void *opaque);
 732 int register_ioport_write(int start, int length, int size,
 733                           IOPortWriteFunc *func, void *opaque);
 734 void isa_unassign_ioport(int start, int length);
 735
 736 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
 737
 738 /* PCI bus */
 739
 740 extern target_phys_addr_t pci_mem_base;
 741
 742 typedef struct PCIBus PCIBus;
 743 typedef struct PCIDevice PCIDevice;
 744
 745 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
 746                                 uint32_t address, uint32_t data, int len);
 747 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
 748                                    uint32_t address, int len);
 749 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
 750                                 uint32_t addr, uint32_t size, int type);
 751
 752 #define PCI_ADDRESS_SPACE_MEM           0x00
 753 #define PCI_ADDRESS_SPACE_IO            0x01
 754 #define PCI_ADDRESS_SPACE_MEM_PREFETCH  0x08
 755
 756 typedef struct PCIIORegion {
 757     uint32_t addr; /* current PCI mapping address. -1 means not mapped */
 758     uint32_t size;
 759     uint8_t type;
 760     PCIMapIORegionFunc *map_func;
 761 } PCIIORegion;
 762
 763 #define PCI_ROM_SLOT 6
 764 #define PCI_NUM_REGIONS 7
 765
 766 #define PCI_DEVICES_MAX 64
 767
 768 #define PCI_VENDOR_ID           0x00    /* 16 bits */
 769 #define PCI_DEVICE_ID           0x02    /* 16 bits */
 770 #define PCI_COMMAND             0x04    /* 16 bits */
 771 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
 772 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
 773 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
 774 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 775 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 776 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 777 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 778
 779 struct PCIDevice {
 780     /* PCI config space */
 781     uint8_t config[256];
 782
 783     /* the following fields are read only */
 784     PCIBus *bus;
 785     int devfn;
 786     char name[64];
 787     PCIIORegion io_regions[PCI_NUM_REGIONS];
 788
 789     /* do not access the following fields */
 790     PCIConfigReadFunc *config_read;
 791     PCIConfigWriteFunc *config_write;
 792     /* ??? This is a PC-specific hack, and should be removed.  */
 793     int irq_index;
 794
 795     /* IRQ objects for the INTA-INTD pins.  */
 796     qemu_irq *irq;
 797
 798     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 799     int irq_state[4];
 800 };
 801
 802 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 803                                int instance_size, int devfn,
 804                                PCIConfigReadFunc *config_read,
 805                                PCIConfigWriteFunc *config_write);
 806
 807 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 808                             uint32_t size, int type,
 809                             PCIMapIORegionFunc *map_func);
 810
 811 uint32_t pci_default_read_config(PCIDevice *d,
 812                                  uint32_t address, int len);
 813 void pci_default_write_config(PCIDevice *d,
 814                               uint32_t address, uint32_t val, int len);
 815 void pci_device_save(PCIDevice *s, QEMUFile *f);
 816 int pci_device_load(PCIDevice *s, QEMUFile *f);
 817
 818 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
 819 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 820 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 821                          qemu_irq *pic, int devfn_min, int nirq);
 822
 823 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
 824 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
 825 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
 826 int pci_bus_num(PCIBus *s);
 827 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
 828
 829 void pci_info(void);
 830 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
 831                         pci_map_irq_fn map_irq, const char *name);
 832
 833 /* prep_pci.c */
 834 PCIBus *pci_prep_init(qemu_irq *pic);
 835
 836 /* grackle_pci.c */
 837 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
 838
 839 /* unin_pci.c */
 840 PCIBus *pci_pmac_init(qemu_irq *pic);
 841
 842 /* apb_pci.c */
 843 PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base,
 844                      qemu_irq *pic);
 845
 846 PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
 847
 848 /* piix_pci.c */
 849 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
 850 void i440fx_set_smm(PCIDevice *d, int val);
 851 int piix3_init(PCIBus *bus, int devfn);
 852 void i440fx_init_memory_mappings(PCIDevice *d);
 853
 854 int piix4_init(PCIBus *bus, int devfn);
 855
 856 /* openpic.c */
 857 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
 858 enum {
 859     OPENPIC_OUTPUT_INT = 0, /* IRQ                       */
 860     OPENPIC_OUTPUT_CINT,    /* critical IRQ              */
 861     OPENPIC_OUTPUT_MCK,     /* Machine check event       */
 862     OPENPIC_OUTPUT_DEBUG,   /* Inconditional debug event */
 863     OPENPIC_OUTPUT_RESET,   /* Core reset event          */
 864     OPENPIC_OUTPUT_NB,
 865 };
 866 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
 867                         qemu_irq **irqs, qemu_irq irq_out);
 868
 869 /* heathrow_pic.c */
 870 qemu_irq *heathrow_pic_init(int *pmem_index);
 871
 872 /* gt64xxx.c */
 873 PCIBus *pci_gt64120_init(qemu_irq *pic);
 874
 875 #ifdef HAS_AUDIO
 876 struct soundhw {
 877     const char *name;
 878     const char *descr;
 879     int enabled;
 880     int isa;
 881     union {
 882         int (*init_isa) (AudioState *s, qemu_irq *pic);
 883         int (*init_pci) (PCIBus *bus, AudioState *s);
 884     } init;
 885 };
 886
 887 extern struct soundhw soundhw[];
 888 #endif
 889
 890 /* vga.c */
 891
 892 #define VGA_RAM_SIZE (8192 * 1024)
 893
 894 struct DisplayState {
 895     uint8_t *data;
 896     int linesize;
 897     int depth;
 898     int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
 899     int width;
 900     int height;
 901     void *opaque;
 902
 903     void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
 904     void (*dpy_resize)(struct DisplayState *s, int w, int h);
 905     void (*dpy_refresh)(struct DisplayState *s);
 906     void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
 907                      int dst_x, int dst_y, int w, int h);
 908     void (*dpy_fill)(struct DisplayState *s, int x, int y,
 909                      int w, int h, uint32_t c);
 910     void (*mouse_set)(int x, int y, int on);
 911     void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
 912                           uint8_t *image, uint8_t *mask);
 913 };
 914
 915 static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
 916 {
 917     s->dpy_update(s, x, y, w, h);
 918 }
 919
 920 static inline void dpy_resize(DisplayState *s, int w, int h)
 921 {
 922     s->dpy_resize(s, w, h);
 923 }
 924
 925 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
 926                  unsigned long vga_ram_offset, int vga_ram_size);
 927 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
 928                  unsigned long vga_ram_offset, int vga_ram_size,
 929                  unsigned long vga_bios_offset, int vga_bios_size);
 930
 931 /* cirrus_vga.c */
 932 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
 933                          unsigned long vga_ram_offset, int vga_ram_size);
 934 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
 935                          unsigned long vga_ram_offset, int vga_ram_size);
 936
 937 /* vmware_vga.c */
 938 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
 939                      unsigned long vga_ram_offset, int vga_ram_size);
 940
 941 /* sdl.c */
 942 void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
 943
 944 /* cocoa.m */
 945 void cocoa_display_init(DisplayState *ds, int full_screen);
 946
 947 /* vnc.c */
 948 void vnc_display_init(DisplayState *ds, const char *display);
 949 void do_info_vnc(void);
 950
 951 /* x_keymap.c */
 952 extern uint8_t _translate_keycode(const int key);
 953
 954 /* ide.c */
 955 #define MAX_DISKS 4
 956
 957 extern BlockDriverState *bs_table[MAX_DISKS + 1];
 958 extern BlockDriverState *sd_bdrv;
 959
 960 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
 961                   BlockDriverState *hd0, BlockDriverState *hd1);
 962 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
 963                          int secondary_ide_enabled);
 964 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
 965                         qemu_irq *pic);
 966 int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
 967
 968 /* cdrom.c */
 969 int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
 970 int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
 971
 972 /* ds1225y.c */
 973 typedef struct ds1225y_t ds1225y_t;
 974 ds1225y_t *ds1225y_init(target_ulong mem_base, const char *filename);
 975
 976 /* es1370.c */
 977 int es1370_init (PCIBus *bus, AudioState *s);
 978
 979 /* sb16.c */
 980 int SB16_init (AudioState *s, qemu_irq *pic);
 981
 982 /* adlib.c */
 983 int Adlib_init (AudioState *s, qemu_irq *pic);
 984
 985 /* gus.c */
 986 int GUS_init (AudioState *s, qemu_irq *pic);
 987
 988 /* dma.c */
 989 typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
 990 int DMA_get_channel_mode (int nchan);
 991 int DMA_read_memory (int nchan, void *buf, int pos, int size);
 992 int DMA_write_memory (int nchan, void *buf, int pos, int size);
 993 void DMA_hold_DREQ (int nchan);
 994 void DMA_release_DREQ (int nchan);
 995 void DMA_schedule(int nchan);
 996 void DMA_run (void);
 997 void DMA_init (int high_page_enable);
 998 void DMA_register_channel (int nchan,
 999                            DMA_transfer_handler transfer_handler,
1000                            void *opaque);
1001 /* fdc.c */
1002 #define MAX_FD 2
1003 extern BlockDriverState *fd_table[MAX_FD];
1004
1005 typedef struct fdctrl_t fdctrl_t;
1006
1007 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1008                        uint32_t io_base,
1009                        BlockDriverState **fds);
1010 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1011
1012 /* eepro100.c */
1013
1014 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1015 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1016 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1017
1018 /* ne2000.c */
1019
1020 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1021 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1022
1023 /* rtl8139.c */
1024
1025 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1026
1027 /* pcnet.c */
1028
1029 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1030 void pcnet_h_reset(void *opaque);
1031 void *lance_init(NICInfo *nd, uint32_t leaddr, void *dma_opaque, qemu_irq irq);
1032
1033 /* vmmouse.c */
1034 void *vmmouse_init(void *m);
1035
1036 /* pckbd.c */
1037
1038 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1039 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, target_ulong base, int it_shift);
1040
1041 /* mc146818rtc.c */
1042
1043 typedef struct RTCState RTCState;
1044
1045 RTCState *rtc_init(int base, qemu_irq irq);
1046 RTCState *rtc_mm_init(target_phys_addr_t base, qemu_irq irq);
1047 void rtc_set_memory(RTCState *s, int addr, int val);
1048 void rtc_set_date(RTCState *s, const struct tm *tm);
1049
1050 /* serial.c */
1051
1052 typedef struct SerialState SerialState;
1053 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1054 SerialState *serial_mm_init (target_ulong base, int it_shift,
1055                              qemu_irq irq, CharDriverState *chr,
1056                              int ioregister);
1057 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1058 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1059 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1060 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1061 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1062 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1063
1064 /* parallel.c */
1065
1066 typedef struct ParallelState ParallelState;
1067 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1068
1069 /* i8259.c */
1070
1071 typedef struct PicState2 PicState2;
1072 extern PicState2 *isa_pic;
1073 void pic_set_irq(int irq, int level);
1074 void pic_set_irq_new(void *opaque, int irq, int level);
1075 qemu_irq *i8259_init(qemu_irq parent_irq);
1076 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1077                           void *alt_irq_opaque);
1078 int pic_read_irq(PicState2 *s);
1079 void pic_update_irq(PicState2 *s);
1080 uint32_t pic_intack_read(PicState2 *s);
1081 void pic_info(void);
1082 void irq_info(void);
1083
1084 /* APIC */
1085 typedef struct IOAPICState IOAPICState;
1086
1087 int apic_init(CPUState *env);
1088 int apic_get_interrupt(CPUState *env);
1089 IOAPICState *ioapic_init(void);
1090 void ioapic_set_irq(void *opaque, int vector, int level);
1091
1092 /* i8254.c */
1093
1094 #define PIT_FREQ 1193182
1095
1096 typedef struct PITState PITState;
1097
1098 PITState *pit_init(int base, qemu_irq irq);
1099 void pit_set_gate(PITState *pit, int channel, int val);
1100 int pit_get_gate(PITState *pit, int channel);
1101 int pit_get_initial_count(PITState *pit, int channel);
1102 int pit_get_mode(PITState *pit, int channel);
1103 int pit_get_out(PITState *pit, int channel, int64_t current_time);
1104
1105 /* pcspk.c */
1106 void pcspk_init(PITState *);
1107 int pcspk_audio_init(AudioState *, qemu_irq *pic);
1108
1109 #include "hw/smbus.h"
1110
1111 /* acpi.c */
1112 extern int acpi_enabled;
1113 void piix4_pm_init(PCIBus *bus, int devfn);
1114 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1115 void acpi_bios_init(void);
1116
1117 /* smbus_eeprom.c */
1118 SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf);
1119
1120 /* pc.c */
1121 extern QEMUMachine pc_machine;
1122 extern QEMUMachine isapc_machine;
1123 extern int fd_bootchk;
1124
1125 void ioport_set_a20(int enable);
1126 int ioport_get_a20(void);
1127
1128 /* ppc.c */
1129 extern QEMUMachine prep_machine;
1130 extern QEMUMachine core99_machine;
1131 extern QEMUMachine heathrow_machine;
1132
1133 /* mips_r4k.c */
1134 extern QEMUMachine mips_machine;
1135
1136 /* mips_malta.c */
1137 extern QEMUMachine mips_malta_machine;
1138
1139 /* mips_int.c */
1140 extern void cpu_mips_irq_init_cpu(CPUState *env);
1141
1142 /* mips_pica61.c */
1143 extern QEMUMachine mips_pica61_machine;
1144
1145 /* mips_timer.c */
1146 extern void cpu_mips_clock_init(CPUState *);
1147 extern void cpu_mips_irqctrl_init (void);
1148
1149 /* shix.c */
1150 extern QEMUMachine shix_machine;
1151
1152 #ifdef TARGET_PPC
1153 /* PowerPC hardware exceptions management helpers */
1154 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1155 typedef struct clk_setup_t clk_setup_t;
1156 struct clk_setup_t {
1157     clk_setup_cb cb;
1158     void *opaque;
1159 };
1160 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1161 {
1162     if (clk->cb != NULL)
1163         (*clk->cb)(clk->opaque, freq);
1164 }
1165
1166 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1167 /* Embedded PowerPC DCR management */
1168 typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1169 typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1170 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1171                   int (*dcr_write_error)(int dcrn));
1172 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1173                       dcr_read_cb drc_read, dcr_write_cb dcr_write);
1174 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1175 /* PowerPC 405 core */
1176 CPUPPCState *ppc405_init (const unsigned char *cpu_model,
1177                           clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
1178                           uint32_t sysclk);
1179 void ppc40x_core_reset (CPUState *env);
1180 void ppc40x_chip_reset (CPUState *env);
1181 void ppc40x_system_reset (CPUState *env);
1182 /* */
1183 typedef struct ppc4xx_mmio_t ppc4xx_mmio_t;
1184 int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
1185                           uint32_t offset, uint32_t len,
1186                           CPUReadMemoryFunc **mem_read,
1187                           CPUWriteMemoryFunc **mem_write, void *opaque);
1188 ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, uint32_t base);
1189 /* PowerPC 4xx peripheral local bus arbitrer */
1190 void ppc4xx_plb_init (CPUState *env);
1191 /* PLB to OPB bridge */
1192 void ppc4xx_pob_init (CPUState *env);
1193 /* OPB arbitrer */
1194 void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio, uint32_t offset);
1195 /* PowerPC 4xx universal interrupt controller */
1196 enum {
1197     PPCUIC_OUTPUT_INT = 0,
1198     PPCUIC_OUTPUT_CINT = 1,
1199     PPCUIC_OUTPUT_NB,
1200 };
1201 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
1202                        uint32_t dcr_base, int has_ssr, int has_vr);
1203 /* SDRAM controller */
1204 void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
1205                         target_ulong *ram_bases, target_ulong *ram_sizes);
1206 /* Peripheral controller */
1207 void ppc405_ebc_init (CPUState *env);
1208 /* DMA controller */
1209 void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]);
1210 /* GPIO */
1211 void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio, uint32_t offset);
1212 /* Serial ports */
1213 void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
1214                          uint32_t offset, qemu_irq irq,
1215                          CharDriverState *chr);
1216 /* On Chip Memory */
1217 void ppc405_ocm_init (CPUState *env, unsigned long offset);
1218 /* I2C controller */
1219 void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio, uint32_t offset);
1220 /* PowerPC 405 microcontrollers */
1221 CPUState *ppc405cr_init (target_ulong ram_bases[4], target_ulong ram_sizes[4],
1222                          uint32_t sysclk, qemu_irq **picp,
1223                          ram_addr_t *offsetp);
1224 CPUState *ppc405ep_init (target_ulong ram_bases[2], target_ulong ram_sizes[2],
1225                          uint32_t sysclk, qemu_irq **picp,
1226                          ram_addr_t *offsetp);
1227 #endif
1228 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1229
1230 extern CPUWriteMemoryFunc *PPC_io_write[];
1231 extern CPUReadMemoryFunc *PPC_io_read[];
1232 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1233
1234 /* sun4m.c */
1235 extern QEMUMachine ss5_machine, ss10_machine;
1236
1237 /* iommu.c */
1238 void *iommu_init(uint32_t addr);
1239 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1240                                  uint8_t *buf, int len, int is_write);
1241 static inline void sparc_iommu_memory_read(void *opaque,
1242                                            target_phys_addr_t addr,
1243                                            uint8_t *buf, int len)
1244 {
1245     sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1246 }
1247
1248 static inline void sparc_iommu_memory_write(void *opaque,
1249                                             target_phys_addr_t addr,
1250                                             uint8_t *buf, int len)
1251 {
1252     sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1253 }
1254
1255 /* tcx.c */
1256 void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
1257                unsigned long vram_offset, int vram_size, int width, int height);
1258
1259 /* slavio_intctl.c */
1260 void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);
1261 void *slavio_intctl_init(uint32_t addr, uint32_t addrg,
1262                          const uint32_t *intbit_to_level,
1263                          qemu_irq **irq);
1264 void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);
1265 void slavio_pic_info(void *opaque);
1266 void slavio_irq_info(void *opaque);
1267
1268 /* loader.c */
1269 int get_image_size(const char *filename);
1270 int load_image(const char *filename, uint8_t *addr);
1271 int load_elf(const char *filename, int64_t virt_to_phys_addend,
1272              uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1273 int load_aout(const char *filename, uint8_t *addr);
1274 int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1275
1276 /* slavio_timer.c */
1277 void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu,
1278                        void *intctl);
1279
1280 /* slavio_serial.c */
1281 SerialState *slavio_serial_init(int base, qemu_irq irq, CharDriverState *chr1,
1282                                 CharDriverState *chr2);
1283 void slavio_serial_ms_kbd_init(int base, qemu_irq);
1284
1285 /* slavio_misc.c */
1286 void *slavio_misc_init(uint32_t base, qemu_irq irq);
1287 void slavio_set_power_fail(void *opaque, int power_failing);
1288
1289 /* esp.c */
1290 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1291 void *esp_init(BlockDriverState **bd, uint32_t espaddr, void *dma_opaque);
1292 void esp_reset(void *opaque);
1293
1294 /* sparc32_dma.c */
1295 void *sparc32_dma_init(uint32_t daddr, qemu_irq espirq, qemu_irq leirq,
1296                        void *iommu);
1297 void ledma_set_irq(void *opaque, int isr);
1298 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1299                        uint8_t *buf, int len, int do_bswap);
1300 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1301                         uint8_t *buf, int len, int do_bswap);
1302 void espdma_raise_irq(void *opaque);
1303 void espdma_clear_irq(void *opaque);
1304 void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1305 void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1306 void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque,
1307                                 void *lance_opaque);
1308
1309 /* cs4231.c */
1310 void cs_init(target_phys_addr_t base, int irq, void *intctl);
1311
1312 /* sun4u.c */
1313 extern QEMUMachine sun4u_machine;
1314
1315 /* NVRAM helpers */
1316 #include "hw/m48t59.h"
1317
1318 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1319 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1320 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1321 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1322 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1323 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1324 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1325                        const unsigned char *str, uint32_t max);
1326 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1327 void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1328                     uint32_t start, uint32_t count);
1329 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1330                           const unsigned char *arch,
1331                           uint32_t RAM_size, int boot_device,
1332                           uint32_t kernel_image, uint32_t kernel_size,
1333                           const char *cmdline,
1334                           uint32_t initrd_image, uint32_t initrd_size,
1335                           uint32_t NVRAM_image,
1336                           int width, int height, int depth);
1337
1338 /* adb.c */
1339
1340 #define MAX_ADB_DEVICES 16
1341
1342 #define ADB_MAX_OUT_LEN 16
1343
1344 typedef struct ADBDevice ADBDevice;
1345
1346 /* buf = NULL means polling */
1347 typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1348                               const uint8_t *buf, int len);
1349 typedef int ADBDeviceReset(ADBDevice *d);
1350
1351 struct ADBDevice {
1352     struct ADBBusState *bus;
1353     int devaddr;
1354     int handler;
1355     ADBDeviceRequest *devreq;
1356     ADBDeviceReset *devreset;
1357     void *opaque;
1358 };
1359
1360 typedef struct ADBBusState {
1361     ADBDevice devices[MAX_ADB_DEVICES];
1362     int nb_devices;
1363     int poll_index;
1364 } ADBBusState;
1365
1366 int adb_request(ADBBusState *s, uint8_t *buf_out,
1367                 const uint8_t *buf, int len);
1368 int adb_poll(ADBBusState *s, uint8_t *buf_out);
1369
1370 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1371                                ADBDeviceRequest *devreq,
1372                                ADBDeviceReset *devreset,
1373                                void *opaque);
1374 void adb_kbd_init(ADBBusState *bus);
1375 void adb_mouse_init(ADBBusState *bus);
1376
1377 /* cuda.c */
1378
1379 extern ADBBusState adb_bus;
1380 int cuda_init(qemu_irq irq);
1381
1382 #include "hw/usb.h"
1383
1384 /* usb ports of the VM */
1385
1386 void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1387                             usb_attachfn attach);
1388
1389 #define VM_USB_HUB_SIZE 8
1390
1391 void do_usb_add(const char *devname);
1392 void do_usb_del(const char *devname);
1393 void usb_info(void);
1394
1395 /* scsi-disk.c */
1396 enum scsi_reason {
1397     SCSI_REASON_DONE, /* Command complete.  */
1398     SCSI_REASON_DATA  /* Transfer complete, more data required.  */
1399 };
1400
1401 typedef struct SCSIDevice SCSIDevice;
1402 typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1403                                   uint32_t arg);
1404
1405 SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1406                            int tcq,
1407                            scsi_completionfn completion,
1408                            void *opaque);
1409 void scsi_disk_destroy(SCSIDevice *s);
1410
1411 int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1412 /* SCSI data transfers are asynchrnonous.  However, unlike the block IO
1413    layer the completion routine may be called directly by
1414    scsi_{read,write}_data.  */
1415 void scsi_read_data(SCSIDevice *s, uint32_t tag);
1416 int scsi_write_data(SCSIDevice *s, uint32_t tag);
1417 void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1418 uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1419
1420 /* lsi53c895a.c */
1421 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1422 void *lsi_scsi_init(PCIBus *bus, int devfn);
1423
1424 /* integratorcp.c */
1425 extern QEMUMachine integratorcp_machine;
1426
1427 /* versatilepb.c */
1428 extern QEMUMachine versatilepb_machine;
1429 extern QEMUMachine versatileab_machine;
1430
1431 /* realview.c */
1432 extern QEMUMachine realview_machine;
1433
1434 /* ps2.c */
1435 void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1436 void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1437 void ps2_write_mouse(void *, int val);
1438 void ps2_write_keyboard(void *, int val);
1439 uint32_t ps2_read_data(void *);
1440 void ps2_queue(void *, int b);
1441 void ps2_keyboard_set_translation(void *opaque, int mode);
1442 void ps2_mouse_fake_event(void *opaque);
1443
1444 /* smc91c111.c */
1445 void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1446
1447 /* pl110.c */
1448 void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1449
1450 /* pl011.c */
1451 void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1452
1453 /* pl050.c */
1454 void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1455
1456 /* pl080.c */
1457 void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1458
1459 /* pl181.c */
1460 void pl181_init(uint32_t base, BlockDriverState *bd,
1461                 qemu_irq irq0, qemu_irq irq1);
1462
1463 /* pl190.c */
1464 qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1465
1466 /* arm-timer.c */
1467 void sp804_init(uint32_t base, qemu_irq irq);
1468 void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1469
1470 /* arm_sysctl.c */
1471 void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1472
1473 /* arm_gic.c */
1474 qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1475
1476 /* arm_boot.c */
1477
1478 void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1479                      const char *kernel_cmdline, const char *initrd_filename,
1480                      int board_id);
1481
1482 /* sh7750.c */
1483 struct SH7750State;
1484
1485 struct SH7750State *sh7750_init(CPUState * cpu);
1486
1487 typedef struct {
1488     /* The callback will be triggered if any of the designated lines change */
1489     uint16_t portamask_trigger;
1490     uint16_t portbmask_trigger;
1491     /* Return 0 if no action was taken */
1492     int (*port_change_cb) (uint16_t porta, uint16_t portb,
1493                            uint16_t * periph_pdtra,
1494                            uint16_t * periph_portdira,
1495                            uint16_t * periph_pdtrb,
1496                            uint16_t * periph_portdirb);
1497 } sh7750_io_device;
1498
1499 int sh7750_register_io_device(struct SH7750State *s,
1500                               sh7750_io_device * device);
1501 /* tc58128.c */
1502 int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1503
1504 /* NOR flash devices */
1505 typedef struct pflash_t pflash_t;
1506
1507 pflash_t *pflash_register (target_ulong base, ram_addr_t off,
1508                            BlockDriverState *bs,
1509                            target_ulong sector_len, int nb_blocs, int width,
1510                            uint16_t id0, uint16_t id1,
1511                            uint16_t id2, uint16_t id3);
1512
1513 #include "gdbstub.h"
1514
1515 #endif /* defined(QEMU_TOOL) */
1516
1517 /* monitor.c */
1518 void monitor_init(CharDriverState *hd, int show_banner);
1519 void term_puts(const char *str);
1520 void term_vprintf(const char *fmt, va_list ap);
1521 void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1522 void term_print_filename(const char *filename);
1523 void term_flush(void);
1524 void term_print_help(void);
1525 void monitor_readline(const char *prompt, int is_password,
1526                       char *buf, int buf_size);
1527
1528 /* readline.c */
1529 typedef void ReadLineFunc(void *opaque, const char *str);
1530
1531 extern int completion_index;
1532 void add_completion(const char *str);
1533 void readline_handle_byte(int ch);
1534 void readline_find_completion(const char *cmdline);
1535 const char *readline_get_history(unsigned int index);
1536 void readline_start(const char *prompt, int is_password,
1537                     ReadLineFunc *readline_func, void *opaque);
1538
1539 void kqemu_record_dump(void);
1540
1541 #endif /* VL_H */