-
-PCIDevice *pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn)
-{
- PCNetState *d;
- uint8_t *pci_conf;
-
-#if 0
- printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
- sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
-#endif
-
- d = (PCNetState *)pci_register_device(bus, "PCNet", sizeof(PCNetState),
- devfn, NULL, NULL);
- if (!d)
- return NULL;
-
- d->dev.unregister = pci_pcnet_uninit;
-
- pci_conf = d->dev.config;
-
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_AMD);
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_AMD_LANCE);
- *(uint16_t *)&pci_conf[0x04] = cpu_to_le16(0x0007);
- *(uint16_t *)&pci_conf[0x06] = cpu_to_le16(0x0280);
- pci_conf[0x08] = 0x10;
- pci_conf[0x09] = 0x00;
- pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
- pci_conf[0x0e] = 0x00; // header_type
-
- *(uint32_t *)&pci_conf[0x10] = cpu_to_le32(0x00000001);
- *(uint32_t *)&pci_conf[0x14] = cpu_to_le32(0x00000000);
-
- pci_conf[0x3d] = 1; // interrupt pin 0
- pci_conf[0x3e] = 0x06;
- pci_conf[0x3f] = 0xff;
-
- /* Handler for memory-mapped I/O */
- d->mmio_index =
- cpu_register_io_memory(0, pcnet_mmio_read, pcnet_mmio_write, d);
-
- pci_register_io_region((PCIDevice *)d, 0, PCNET_IOPORT_SIZE,
- PCI_ADDRESS_SPACE_IO, pcnet_ioport_map);
-
- pci_register_io_region((PCIDevice *)d, 1, PCNET_PNPMMIO_SIZE,
- PCI_ADDRESS_SPACE_MEM, pcnet_mmio_map);
-
- d->irq = d->dev.irq[0];
- d->phys_mem_read = pci_physical_memory_read;
- d->phys_mem_write = pci_physical_memory_write;
- d->pci_dev = &d->dev;
-
- pcnet_common_init(d, nd, pci_pcnet_cleanup);
-
- return (PCIDevice *)d;
-}
-
-/* SPARC32 interface */
-
-#if defined (TARGET_SPARC) && !defined(TARGET_SPARC64) // Avoid compile failure
-#include "sun4m.h"
-
-static void parent_lance_reset(void *opaque, int irq, int level)
-{
- if (level)
- pcnet_h_reset(opaque);
-}
-
-static void lance_mem_writew(void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
-#ifdef PCNET_DEBUG_IO
- printf("lance_mem_writew addr=" TARGET_FMT_plx " val=0x%04x\n", addr,
- val & 0xffff);
-#endif
- pcnet_ioport_writew(opaque, addr, val & 0xffff);
-}
-
-static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
-{
- uint32_t val;
-
- val = pcnet_ioport_readw(opaque, addr);
-#ifdef PCNET_DEBUG_IO
- printf("lance_mem_readw addr=" TARGET_FMT_plx " val = 0x%04x\n", addr,
- val & 0xffff);
-#endif
-
- return val & 0xffff;
-}
-
-static CPUReadMemoryFunc *lance_mem_read[3] = {
- NULL,
- lance_mem_readw,
- NULL,
-};
-
-static CPUWriteMemoryFunc *lance_mem_write[3] = {
- NULL,
- lance_mem_writew,
- NULL,
-};
-
-static void lance_cleanup(VLANClientState *vc)
-{
- PCNetState *d = vc->opaque;
-
- pcnet_common_cleanup(d);
-
- qemu_free_irqs(d->reset_irq);
-
- cpu_unregister_io_memory(d->mmio_index);
-
- qemu_free(d);
-}
-
-void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
- qemu_irq irq, qemu_irq *reset)
-{
- PCNetState *d;
-
- qemu_check_nic_model(nd, "lance");
-
- d = qemu_mallocz(sizeof(PCNetState));
-
- d->mmio_index =
- cpu_register_io_memory(0, lance_mem_read, lance_mem_write, d);
-
- d->dma_opaque = dma_opaque;
-
- d->reset_irq = qemu_allocate_irqs(parent_lance_reset, d, 1);
- *reset = *d->reset_irq;
-
- cpu_register_physical_memory(leaddr, 4, d->mmio_index);
-
- d->irq = irq;
- d->phys_mem_read = ledma_memory_read;
- d->phys_mem_write = ledma_memory_write;
-
- pcnet_common_init(d, nd, lance_cleanup);
-}
-#endif /* TARGET_SPARC */