- PPC4xxPCIState *controller;
- int index;
- static int ppc4xx_pci_id;
- uint8_t *pci_conf;
-
- controller = g_malloc0(sizeof(PPC4xxPCIState));
-
- controller->pci_state.bus = pci_register_bus(NULL, "pci",
- ppc4xx_pci_set_irq,
- ppc4xx_pci_map_irq,
- pci_irqs,
- get_system_memory(),
- get_system_io(),
- 0, 4);
-
- controller->pci_dev = pci_register_device(controller->pci_state.bus,
- "host bridge", sizeof(PCIDevice),
- 0, NULL, NULL);
- pci_conf = controller->pci_dev->config;
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_440GX);
- pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
-
- /* CFGADDR */
- index = cpu_register_io_memory(pci4xx_cfgaddr_read,
- pci4xx_cfgaddr_write, controller,
- DEVICE_LITTLE_ENDIAN);
- if (index < 0)
- goto free;
- cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
-
- /* CFGDATA */
- memory_region_init_io(&controller->pci_state.data_mem,
- &pci_host_data_be_ops,
- &controller->pci_state, "pci-conf-data", 4);
- memory_region_add_subregion(get_system_memory(),
- config_space + PCIC0_CFGDATA,
- &controller->pci_state.data_mem);
-
- /* Internal registers */
- index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller,
- DEVICE_LITTLE_ENDIAN);
- if (index < 0)
- goto free;
- cpu_register_physical_memory(registers, PCI_REG_SIZE, index);
-
- qemu_register_reset(ppc4xx_pci_reset, controller);
-
- /* XXX load/save code not tested. */
- vmstate_register(&controller->pci_dev->qdev, ppc4xx_pci_id++,
- &vmstate_ppc4xx_pci, controller);
-
- return controller->pci_state.bus;
-
-free:
- printf("%s error\n", __func__);
- g_free(controller);
- return NULL;
+ PPC4xxPCIState *s;
+ PCIHostState *h;
+ PCIBus *b;
+ int i;
+
+ h = PCI_HOST_BRIDGE(dev);
+ s = PPC4xx_PCI_HOST_BRIDGE(dev);
+
+ for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
+ sysbus_init_irq(dev, &s->irq[i]);
+ }
+
+ b = pci_register_bus(DEVICE(dev), NULL, ppc4xx_pci_set_irq,
+ ppc4xx_pci_map_irq, s->irq, get_system_memory(),
+ get_system_io(), 0, 4);
+ h->bus = b;
+
+ pci_create_simple(b, 0, "ppc4xx-host-bridge");
+
+ /* XXX split into 2 memory regions, one for config space, one for regs */
+ memory_region_init(&s->container, "pci-container", PCI_ALL_SIZE);
+ memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops, h,
+ "pci-conf-idx", 4);
+ memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
+ "pci-conf-data", 4);
+ memory_region_init_io(&s->iomem, &pci_reg_ops, s,
+ "pci.reg", PCI_REG_SIZE);
+ memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
+ memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
+ memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
+ sysbus_init_mmio(dev, &s->container);
+ qemu_register_reset(ppc4xx_pci_reset, s);
+
+ return 0;