-#define MMU_KERNEL_IDX 0
-#define MMU_USER_IDX 3
-#define MMU_PHYS_IDX 4
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
-/* Hardware exceptions, interupts, faults, and traps. */
+#define MMU_ABS_W_IDX 6
+#define MMU_ABS_IDX 7
+#define MMU_KERNEL_IDX 8
+#define MMU_KERNEL_P_IDX 9
+#define MMU_PL1_IDX 10
+#define MMU_PL1_P_IDX 11
+#define MMU_PL2_IDX 12
+#define MMU_PL2_P_IDX 13
+#define MMU_USER_IDX 14
+#define MMU_USER_P_IDX 15
+
+#define MMU_IDX_MMU_DISABLED(MIDX) ((MIDX) < MMU_KERNEL_IDX)
+#define MMU_IDX_TO_PRIV(MIDX) (((MIDX) - MMU_KERNEL_IDX) / 2)
+#define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1)
+#define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX)
+
+#define TARGET_INSN_START_EXTRA_WORDS 2
+
+/* No need to flush MMU_ABS*_IDX */
+#define HPPA_MMU_FLUSH_MASK \
+ (1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX | \
+ 1 << MMU_PL1_IDX | 1 << MMU_PL1_P_IDX | \
+ 1 << MMU_PL2_IDX | 1 << MMU_PL2_P_IDX | \
+ 1 << MMU_USER_IDX | 1 << MMU_USER_P_IDX)
+
+/* Indices to flush for access_id changes. */
+#define HPPA_MMU_FLUSH_P_MASK \
+ (1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX | \
+ 1 << MMU_PL2_P_IDX | 1 << MMU_USER_P_IDX)
+
+/* Hardware exceptions, interrupts, faults, and traps. */