Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs

[mirror_ubuntu-bionic-kernel.git] / Documentation / devicetree / bindings / mmc / arasan,sdhci.txt

diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 31b35c3a5e478191cb5faa427b5aaec57ec87fff..476604e6ce2aa8c0bc43aef3321ee5c95b407ecb 100644 (file)
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -9,8 +9,12 @@ Device Tree Bindings for the Arasan SDHCI Controller
   [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
 
 Required Properties:
-  - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
-                'arasan,sdhci-4.9a' or 'arasan,sdhci-5.1'
+  - compatible: Compatibility string.  One of:
+    - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
+    - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
+    - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
+    - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
+      For this device it is strongly suggested to include arasan,soc-ctl-syscon.
   - reg: From mmc bindings: Register location and length.
   - clocks: From clock bindings: Handles to clock inputs.
   - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
@@ -22,6 +26,11 @@ Required Properties for "arasan,sdhci-5.1":
   - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
   - phy-names:  MUST be "phy_arasan".
 
+Optional Properties:
+  - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
+    used to access core corecfg registers.  Offsets of registers in this
+    syscon are determined based on the main compatible string for the device.
+
 Example:
        sdhci@e0100000 {
                compatible = "arasan,sdhci-8.9a";
@@ -42,3 +51,17 @@ Example:
                phys = <&emmc_phy>;
                phy-names = "phy_arasan";
        } ;
+
+       sdhci: sdhci@fe330000 {
+               compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
+               reg = <0x0 0xfe330000 0x0 0x10000>;
+               interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
+               clock-names = "clk_xin", "clk_ahb";
+               arasan,soc-ctl-syscon = <&grf>;
+               assigned-clocks = <&cru SCLK_EMMC>;
+               assigned-clock-rates = <200000000>;
+               phys = <&emmc_phy>;
+               phy-names = "phy_arasan";
+               status = "disabled";
+       };