LoongArch TCG CPUs
M: Song Gao <gaosong@loongson.cn>
-M: Xiaojuan Yang <yangxiaojuan@loongson.cn>
S: Maintained
F: target/loongarch/
F: tests/tcg/loongarch64/
R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
L: qemu-riscv@nongnu.org
S: Supported
+F: configs/targets/riscv*
+F: docs/system/target-riscv.rst
F: target/riscv/
F: hw/riscv/
+F: hw/intc/riscv*
F: include/hw/riscv/
F: linux-user/host/riscv32/
F: linux-user/host/riscv64/
S: Supported
F: target/riscv/insn_trans/trans_xthead.c.inc
F: target/riscv/xthead*.decode
+F: disas/riscv-xthead*
RISC-V XVentanaCondOps extension
M: Philipp Tomsich <philipp.tomsich@vrull.eu>
S: Maintained
F: target/riscv/XVentanaCondOps.decode
F: target/riscv/insn_trans/trans_xventanacondops.c.inc
+F: disas/riscv-xventana*
RENESAS RX CPUs
R: Yoshinori Sato <ysato@users.sourceforge.jp>
M: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
F: linux-headers/
+F: include/standard-headers/
F: scripts/update-linux-headers.sh
POSIX
L: qemu-arm@nongnu.org
S: Maintained
F: hw/arm/sbsa-ref.c
+F: hw/misc/sbsa_ec.c
+F: hw/watchdog/sbsa_gwdt.c
+F: include/hw/watchdog/sbsa_gwdt.h
F: docs/system/arm/sbsa.rst
F: tests/avocado/machine_aarch64_sbsaref.py
LoongArch Machines
------------------
Virt
-M: Xiaojuan Yang <yangxiaojuan@loongson.cn>
M: Song Gao <gaosong@loongson.cn>
S: Maintained
F: docs/system/loongarch/virt.rst
F: hw/nubus/*
F: hw/display/macfb.c
F: hw/block/swim.c
+F: hw/misc/djmemc.c
+F: hw/misc/iosb.c
+F: hw/audio/asc.c
F: hw/m68k/bootinfo.h
F: include/standard-headers/asm-m68k/bootinfo.h
F: include/standard-headers/asm-m68k/bootinfo-mac.h
F: include/hw/block/swim.h
F: include/hw/m68k/q800.h
F: include/hw/m68k/q800-glue.h
+F: include/hw/misc/djmemc.h
+F: include/hw/misc/iosb.h
+F: include/hw/audio/asc.h
virt
M: Laurent Vivier <laurent@vivier.eu>
R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Maintained
F: hw/mips/jazz.c
+F: hw/display/g364fb.c
F: hw/display/jazz_led.c
F: hw/dma/rc4030.c
+F: hw/nvram/ds1225y.c
Malta
M: Philippe Mathieu-Daudé <philmd@linaro.org>
M: Bin Meng <bin.meng@windriver.com>
L: qemu-riscv@nongnu.org
S: Supported
+F: docs/system/riscv/microchip-icicle-kit.rst
F: hw/riscv/microchip_pfsoc.c
F: hw/char/mchp_pfsoc_mmuart.c
F: hw/misc/mchp_pfsoc_dmc.c
M: Vijai Kumar K <vijai@behindbytes.com>
L: qemu-riscv@nongnu.org
S: Supported
+F: docs/system/riscv/shakti-c.rst
F: hw/riscv/shakti_c.c
F: hw/char/shakti_uart.c
F: include/hw/riscv/shakti_c.h
M: Palmer Dabbelt <palmer@dabbelt.com>
L: qemu-riscv@nongnu.org
S: Supported
+F: docs/system/riscv/sifive_u.rst
F: hw/*/*sifive*.c
F: include/hw/*/*sifive*.h
R: Paolo Bonzini <pbonzini@redhat.com>
S: Odd Fixes
F: hw/char/
+F: include/hw/char/
Network devices
M: Jason Wang <jasowang@redhat.com>
F: include/gdbstub/*
F: gdb-xml/
F: tests/tcg/multiarch/gdbstub/
-F: scripts/feature_to_c.sh
+F: scripts/feature_to_c.py
F: scripts/probe-gdb-support.py
Memory API
F: include/hw/mem/memory-device.h
F: include/hw/mem/nvdimm.h
F: include/hw/mem/pc-dimm.h
+F: stubs/memory_device.c
F: docs/nvdimm.txt
SPICE
R: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
F: system/qtest.c
+F: include/sysemu/qtest.h
F: accel/qtest/
F: tests/qtest/
F: docs/devel/qgraph.rst
S: Maintained
F: contrib/elf2dmp/
+Overall sensors
+M: Philippe Mathieu-Daudé <philmd@linaro.org>
+S: Odd Fixes
+F: hw/sensor
+F: include/hw/sensor
+
I2C and SMBus
M: Corey Minyard <cminyard@mvista.com>
S: Maintained
L: qemu-riscv@nongnu.org
S: Maintained
F: tcg/riscv/
-F: disas/riscv.c
+F: disas/riscv.[ch]
S390 TCG target
M: Richard Henderson <richard.henderson@linaro.org>
PVRDMA
M: Yuval Shaia <yuval.shaia.ml@gmail.com>
M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
-S: Maintained
+S: Odd Fixes
F: hw/rdma/*
F: hw/rdma/vmw/*
F: docs/pvrdma.txt
F: .gitlab-ci.yml
F: .gitlab-ci.d/
F: .travis.yml
+F: docs/devel/ci*
F: scripts/ci/
F: tests/docker/
F: tests/vm/