Merge tag 'late-mvebu-rebased' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...

[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / at91rm9200.dtsi

diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 222047f1ece9bfac7ed0562540bfaff483dc89e3..b0268a5f4b4e7f75387ad24f8a3f48b3f1f9d780 100644 (file)
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -29,6 +29,9 @@
                gpio3 = &pioD;
                tcb0 = &tcb0;
                tcb1 = &tcb1;
+               ssc0 = &ssc0;
+               ssc1 = &ssc1;
+               ssc2 = &ssc2;
        };
        cpus {
                cpu@0 {
@@ -88,6 +91,52 @@
                                interrupts = <20 4 0 21 4 0 22 4 0>;
                        };
 
+                       mmc0: mmc@fffb4000 {
+                               compatible = "atmel,hsmci";
+                               reg = <0xfffb4000 0x4000>;
+                               interrupts = <10 4 0>;
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       ssc0: ssc@fffd0000 {
+                               compatible = "atmel,at91rm9200-ssc";
+                               reg = <0xfffd0000 0x4000>;
+                               interrupts = <14 4 5>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+                               status = "disable";
+                       };
+
+                       ssc1: ssc@fffd4000 {
+                               compatible = "atmel,at91rm9200-ssc";
+                               reg = <0xfffd4000 0x4000>;
+                               interrupts = <15 4 5>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+                               status = "disable";
+                       };
+
+                       ssc2: ssc@fffd8000 {
+                               compatible = "atmel,at91rm9200-ssc";
+                               reg = <0xfffd8000 0x4000>;
+                               interrupts = <16 4 5>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
+                               status = "disable";
+                       };
+
+                       macb0: ethernet@fffbc000 {
+                               compatible = "cdns,at91rm9200-emac", "cdns,emac";
+                               reg = <0xfffbc000 0x4000>;
+                               interrupts = <24 4 3>;
+                               phy-mode = "rmii";
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&pinctrl_macb_rmii>;
+                               status = "disabled";
+                       };
+
                        pinctrl@fffff400 {
                                #address-cells = <1>;
                                #size-cells = <1>;
@@ -207,6 +256,115 @@
                                        };
                                };
 
+                               macb {
+                                       pinctrl_macb_rmii: macb_rmii-0 {
+                                               atmel,pins =
+                                                       <0 7 0x1 0x0    /* PA7 periph A */
+                                                        0 8 0x1 0x0    /* PA8 periph A */
+                                                        0 9 0x1 0x0    /* PA9 periph A */
+                                                        0 10 0x1 0x0   /* PA10 periph A */
+                                                        0 11 0x1 0x0   /* PA11 periph A */
+                                                        0 12 0x1 0x0   /* PA12 periph A */
+                                                        0 13 0x1 0x0   /* PA13 periph A */
+                                                        0 14 0x1 0x0   /* PA14 periph A */
+                                                        0 15 0x1 0x0   /* PA15 periph A */
+                                                        0 16 0x1 0x0>; /* PA16 periph A */
+                                       };
+
+                                       pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
+                                               atmel,pins =
+                                                       <1 12 0x2 0x0   /* PB12 periph B */
+                                                        1 13 0x2 0x0   /* PB13 periph B */
+                                                        1 14 0x2 0x0   /* PB14 periph B */
+                                                        1 15 0x2 0x0   /* PB15 periph B */
+                                                        1 16 0x2 0x0   /* PB16 periph B */
+                                                        1 17 0x2 0x0   /* PB17 periph B */
+                                                        1 18 0x2 0x0   /* PB18 periph B */
+                                                        1 19 0x2 0x0>; /* PB19 periph B */
+                                       };
+                               };
+
+                               mmc0 {
+                                       pinctrl_mmc0_clk: mmc0_clk-0 {
+                                               atmel,pins =
+                                                       <0 27 0x1 0x0>; /* PA27 periph A */
+                                       };
+
+                                       pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
+                                               atmel,pins =
+                                                       <0 28 0x1 0x1   /* PA28 periph A with pullup */
+                                                        0 29 0x1 0x1>; /* PA29 periph A with pullup */
+                                       };
+
+                                       pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
+                                               atmel,pins =
+                                                       <1 3 0x2 0x1    /* PB3 periph B with pullup */
+                                                        1 4 0x2 0x1    /* PB4 periph B with pullup */
+                                                        1 5 0x2 0x1>;  /* PB5 periph B with pullup */
+                                       };
+
+                                       pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
+                                               atmel,pins =
+                                                       <0 8 0x2 0x1    /* PA8 periph B with pullup */
+                                                        0 9 0x2 0x1>;  /* PA9 periph B with pullup */
+                                       };
+
+                                       pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
+                                               atmel,pins =
+                                                       <0 10 0x2 0x1   /* PA10 periph B with pullup */
+                                                        0 11 0x2 0x1   /* PA11 periph B with pullup */
+                                                        0 12 0x2 0x1>; /* PA12 periph B with pullup */
+                                       };
+                               };
+
+                               ssc0 {
+                                       pinctrl_ssc0_tx: ssc0_tx-0 {
+                                               atmel,pins =
+                                                       <1 0 0x1 0x0    /* PB0 periph A */
+                                                        1 1 0x1 0x0    /* PB1 periph A */
+                                                        1 2 0x1 0x0>;  /* PB2 periph A */
+                                       };
+
+                                       pinctrl_ssc0_rx: ssc0_rx-0 {
+                                               atmel,pins =
+                                                       <1 3 0x1 0x0    /* PB3 periph A */
+                                                        1 4 0x1 0x0    /* PB4 periph A */
+                                                        1 5 0x1 0x0>;  /* PB5 periph A */
+                                       };
+                               };
+
+                               ssc1 {
+                                       pinctrl_ssc1_tx: ssc1_tx-0 {
+                                               atmel,pins =
+                                                       <1 6 0x1 0x0    /* PB6 periph A */
+                                                        1 7 0x1 0x0    /* PB7 periph A */
+                                                        1 8 0x1 0x0>;  /* PB8 periph A */
+                                       };
+
+                                       pinctrl_ssc1_rx: ssc1_rx-0 {
+                                               atmel,pins =
+                                                       <1 9 0x1 0x0    /* PB9 periph A */
+                                                        1 10 0x1 0x0   /* PB10 periph A */
+                                                        1 11 0x1 0x0>; /* PB11 periph A */
+                                       };
+                               };
+
+                               ssc2 {
+                                       pinctrl_ssc2_tx: ssc2_tx-0 {
+                                               atmel,pins =
+                                                       <1 12 0x1 0x0   /* PB12 periph A */
+                                                        1 13 0x1 0x0   /* PB13 periph A */
+                                                        1 14 0x1 0x0>; /* PB14 periph A */
+                                       };
+
+                                       pinctrl_ssc2_rx: ssc2_rx-0 {
+                                               atmel,pins =
+                                                       <1 15 0x1 0x0   /* PB15 periph A */
+                                                        1 16 0x1 0x0   /* PB16 periph A */
+                                                        1 17 0x1 0x0>; /* PB17 periph A */
+                                       };
+                               };
+
                                pioA: gpio@fffff400 {
                                        compatible = "atmel,at91rm9200-gpio";
                                        reg = <0xfffff400 0x200>;