Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

[mirror_ubuntu-artful-kernel.git] / arch / arm / boot / dts / exynos4x12.dtsi

diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 8bc97c415c9a6f4dba7574b8adec446a172b23a5..f5e0ae780d6ce8dd25622abed741b03416570f03 100644 (file)
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -52,6 +52,7 @@
        pd_isp: isp-power-domain@10023CA0 {
                compatible = "samsung,exynos4210-pd";
                reg = <0x10023CA0 0x20>;
+               #power-domain-cells = <0>;
        };
 
        l2c: l2-cache-controller@10502000 {
@@ -209,7 +210,7 @@
                        compatible = "samsung,exynos4212-fimc-lite";
                        reg = <0x12390000 0x1000>;
                        interrupts = <0 105 0>;
-                       samsung,power-domain = <&pd_isp>;
+                       power-domains = <&pd_isp>;
                        clocks = <&clock CLK_FIMC_LITE0>;
                        clock-names = "flite";
                        status = "disabled";
@@ -219,7 +220,7 @@
                        compatible = "samsung,exynos4212-fimc-lite";
                        reg = <0x123A0000 0x1000>;
                        interrupts = <0 106 0>;
-                       samsung,power-domain = <&pd_isp>;
+                       power-domains = <&pd_isp>;
                        clocks = <&clock CLK_FIMC_LITE1>;
                        clock-names = "flite";
                        status = "disabled";
@@ -229,7 +230,7 @@
                        compatible = "samsung,exynos4212-fimc-is", "simple-bus";
                        reg = <0x12000000 0x260000>;
                        interrupts = <0 90 0>, <0 95 0>;
-                       samsung,power-domain = <&pd_isp>;
+                       power-domains = <&pd_isp>;
                        clocks = <&clock CLK_FIMC_LITE0>,
                                 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
                                 <&clock CLK_PPMUISPMX>,
@@ -239,7 +240,7 @@
                                 <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
                                 <&clock CLK_DIV_MCUISP0>,
                                 <&clock CLK_DIV_MCUISP1>,
-                                <&clock CLK_SCLK_UART_ISP>,
+                                <&clock CLK_UART_ISP_SCLK>,
                                 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
                                 <&clock CLK_ACLK400_MCUISP>,
                                 <&clock CLK_DIV_ACLK400_MCUISP>;