Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / r8a7792.dtsi

diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 6e1f61f65d292b0bea394ff3e36d4feaf8330839..6ced3c1ec3770c70c53d6d0e0cacf43788fb7e23 100644 (file)
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -26,6 +26,8 @@
                i2c4 = &i2c4;
                i2c5 = &i2c5;
                spi0 = &qspi;
+               spi1 = &msiof0;
+               spi2 = &msiof1;
                vin0 = &vin0;
                vin1 = &vin1;
                vin2 = &vin2;
@@ -123,6 +125,11 @@
                        reg = <0 0xe6160000 0 0x0100>;
                };
 
+               prr: chipid@ff000044 {
+                       compatible = "renesas,prr";
+                       reg = <0 0xff000044 0 4>;
+               };
+
                sysc: system-controller@e6180000 {
                        compatible = "renesas,r8a7792-sysc";
                        reg = <0 0xe6180000 0 0x0200>;
@@ -577,6 +584,34 @@
                        status = "disabled";
                };
 
+               msiof0: spi@e6e20000 {
+                       compatible = "renesas,msiof-r8a7792";
+                       reg = <0 0xe6e20000 0 0x0064>;
+                       interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&mstp0_clks R8A7792_CLK_MSIOF0>;
+                       dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+                              <&dmac1 0x51>, <&dmac1 0x52>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               msiof1: spi@e6e10000 {
+                       compatible = "renesas,msiof-r8a7792";
+                       reg = <0 0xe6e10000 0 0x0064>;
+                       interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&mstp2_clks R8A7792_CLK_MSIOF1>;
+                       dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+                              <&dmac1 0x55>, <&dmac1 0x56>;
+                       dma-names = "tx", "rx", "tx", "rx";
+                       power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                du: display@feb00000 {
                        compatible = "renesas,du-r8a7792";
                        reg = <0 0xfeb00000 0 0x40000>;
@@ -768,6 +803,13 @@
                        clock-div = <48>;
                        clock-mult = <1>;
                };
+               mp_clk: mp {
+                       compatible = "fixed-factor-clock";
+                       clocks = <&pll1_div2_clk>;
+                       #clock-cells = <0>;
+                       clock-div = <15>;
+                       clock-mult = <1>;
+               };
                m2_clk: m2 {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
@@ -798,6 +840,15 @@
                };
 
                /* Gate clocks */
+               mstp0_clks: mstp0_clks@e6150130 {
+                       compatible = "renesas,r8a7792-mstp-clocks",
+                                    "renesas,cpg-mstp-clocks";
+                       reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+                       clocks = <&mp_clk>;
+                       #clock-cells = <1>;
+                       clock-indices = <R8A7792_CLK_MSIOF0>;
+                       clock-output-names = "msiof0";
+               };
                mstp1_clks: mstp1_clks@e6150134 {
                        compatible = "renesas,r8a7792-mstp-clocks",
                                     "renesas,cpg-mstp-clocks";
@@ -816,12 +867,13 @@
                        compatible = "renesas,r8a7792-mstp-clocks",
                                     "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
-                       clocks = <&zs_clk>, <&zs_clk>;
+                       clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>;
                        #clock-cells = <1>;
                        clock-indices = <
+                               R8A7792_CLK_MSIOF1
                                R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
                        >;
-                       clock-output-names = "sys-dmac1", "sys-dmac0";
+                       clock-output-names = "msiof1", "sys-dmac1", "sys-dmac0";
                };
                mstp3_clks: mstp3_clks@e615013c {
                        compatible = "renesas,r8a7792-mstp-clocks",