ARM: tegra: add DT entry for KBC controller

[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / tegra30.dtsi

diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 529fdb82dfdb9683405a02c86e42e0850590f633..ff4a0ca459831256bdf9c57000d8776399353f6d 100644 (file)
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,11 +4,20 @@
        compatible = "nvidia,tegra30";
        interrupt-parent = <&intc>;
 
+       aliases {
+               serial0 = &uarta;
+               serial1 = &uartb;
+               serial2 = &uartc;
+               serial3 = &uartd;
+               serial4 = &uarte;
+       };
+
        host1x {
                compatible = "nvidia,tegra30-host1x", "simple-bus";
                reg = <0x50000000 0x00024000>;
                interrupts = <0 65 0x04   /* mpcore syncpt */
                              0 67 0x04>; /* mpcore general */
+               clocks = <&tegra_car 28>;
 
                #address-cells = <1>;
                #size-cells = <1>;
@@ -19,41 +28,50 @@
                        compatible = "nvidia,tegra30-mpe";
                        reg = <0x54040000 0x00040000>;
                        interrupts = <0 68 0x04>;
+                       clocks = <&tegra_car 60>;
                };
 
                vi {
                        compatible = "nvidia,tegra30-vi";
                        reg = <0x54080000 0x00040000>;
                        interrupts = <0 69 0x04>;
+                       clocks = <&tegra_car 164>;
                };
 
                epp {
                        compatible = "nvidia,tegra30-epp";
                        reg = <0x540c0000 0x00040000>;
                        interrupts = <0 70 0x04>;
+                       clocks = <&tegra_car 19>;
                };
 
                isp {
                        compatible = "nvidia,tegra30-isp";
                        reg = <0x54100000 0x00040000>;
                        interrupts = <0 71 0x04>;
+                       clocks = <&tegra_car 23>;
                };
 
                gr2d {
                        compatible = "nvidia,tegra30-gr2d";
                        reg = <0x54140000 0x00040000>;
                        interrupts = <0 72 0x04>;
+                       clocks = <&tegra_car 21>;
                };
 
                gr3d {
                        compatible = "nvidia,tegra30-gr3d";
                        reg = <0x54180000 0x00040000>;
+                       clocks = <&tegra_car 24 &tegra_car 98>;
+                       clock-names = "3d", "3d2";
                };
 
                dc@54200000 {
                        compatible = "nvidia,tegra30-dc";
                        reg = <0x54200000 0x00040000>;
                        interrupts = <0 73 0x04>;
+                       clocks = <&tegra_car 27>, <&tegra_car 179>;
+                       clock-names = "disp1", "parent";
 
                        rgb {
                                status = "disabled";
@@ -64,6 +82,8 @@
                        compatible = "nvidia,tegra30-dc";
                        reg = <0x54240000 0x00040000>;
                        interrupts = <0 74 0x04>;
+                       clocks = <&tegra_car 26>, <&tegra_car 179>;
+                       clock-names = "disp2", "parent";
 
                        rgb {
                                status = "disabled";
@@ -74,6 +94,8 @@
                        compatible = "nvidia,tegra30-hdmi";
                        reg = <0x54280000 0x00040000>;
                        interrupts = <0 75 0x04>;
+                       clocks = <&tegra_car 51>, <&tegra_car 189>;
+                       clock-names = "hdmi", "parent";
                        status = "disabled";
                };
 
@@ -81,12 +103,14 @@
                        compatible = "nvidia,tegra30-tvo";
                        reg = <0x542c0000 0x00040000>;
                        interrupts = <0 76 0x04>;
+                       clocks = <&tegra_car 169>;
                        status = "disabled";
                };
 
                dsi {
                        compatible = "nvidia,tegra30-dsi";
                        reg = <0x54300000 0x00040000>;
+                       clocks = <&tegra_car 48>;
                        status = "disabled";
                };
        };
@@ -97,15 +121,6 @@
                interrupts = <1 13 0xf04>;
        };
 
-       cache-controller@50043000 {
-               compatible = "arm,pl310-cache";
-               reg = <0x50043000 0x1000>;
-               arm,data-latency = <6 6 2>;
-               arm,tag-latency = <5 5 2>;
-               cache-unified;
-               cache-level = <2>;
-       };
-
        intc: interrupt-controller {
                compatible = "arm,cortex-a9-gic";
                reg = <0x50041000 0x1000
@@ -114,6 +129,15 @@
                #interrupt-cells = <3>;
        };
 
+       cache-controller {
+               compatible = "arm,pl310-cache";
+               reg = <0x50043000 0x1000>;
+               arm,data-latency = <6 6 2>;
+               arm,tag-latency = <5 5 2>;
+               cache-unified;
+               cache-level = <2>;
+       };
+
        timer@60005000 {
                compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
                reg = <0x60005000 0x400>;
@@ -125,6 +149,12 @@
                              0 122 0x04>;
        };
 
+       tegra_car: clock {
+               compatible = "nvidia,tegra30-car";
+               reg = <0x60006000 0x1000>;
+               #clock-cells = <1>;
+       };
+
        apbdma: dma {
                compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
                reg = <0x6000a000 0x1400>;
@@ -160,6 +190,7 @@
                              0 141 0x04
                              0 142 0x04
                              0 143 0x04>;
+               clocks = <&tegra_car 34>;
        };
 
        ahb: ahb {
@@ -168,7 +199,7 @@
        };
 
        gpio: gpio {
-               compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
+               compatible = "nvidia,tegra30-gpio";
                reg = <0x6000d000 0x1000>;
                interrupts = <0 32 0x04
                              0 33 0x04
@@ -190,43 +221,61 @@
                       0x70003000 0x3e4>; /* Mux registers */
        };
 
-       serial@70006000 {
+       /*
+        * There are two serial driver i.e. 8250 based simple serial
+        * driver and APB DMA based serial driver for higher baudrate
+        * and performace. To enable the 8250 based driver, the compatible
+        * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
+        * the APB DMA based serial driver, the comptible is
+        * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
+        */
+       uarta: serial@70006000 {
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006000 0x40>;
                reg-shift = <2>;
                interrupts = <0 36 0x04>;
+               nvidia,dma-request-selector = <&apbdma 8>;
+               clocks = <&tegra_car 6>;
                status = "disabled";
        };
 
-       serial@70006040 {
+       uartb: serial@70006040 {
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006040 0x40>;
                reg-shift = <2>;
                interrupts = <0 37 0x04>;
+               nvidia,dma-request-selector = <&apbdma 9>;
+               clocks = <&tegra_car 160>;
                status = "disabled";
        };
 
-       serial@70006200 {
+       uartc: serial@70006200 {
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006200 0x100>;
                reg-shift = <2>;
                interrupts = <0 46 0x04>;
+               nvidia,dma-request-selector = <&apbdma 10>;
+               clocks = <&tegra_car 55>;
                status = "disabled";
        };
 
-       serial@70006300 {
+       uartd: serial@70006300 {
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006300 0x100>;
                reg-shift = <2>;
                interrupts = <0 90 0x04>;
+               nvidia,dma-request-selector = <&apbdma 19>;
+               clocks = <&tegra_car 65>;
                status = "disabled";
        };
 
-       serial@70006400 {
+       uarte: serial@70006400 {
                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                reg = <0x70006400 0x100>;
                reg-shift = <2>;
                interrupts = <0 91 0x04>;
+               nvidia,dma-request-selector = <&apbdma 20>;
+               clocks = <&tegra_car 66>;
                status = "disabled";
        };
 
@@ -234,6 +283,7 @@
                compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
                reg = <0x7000a000 0x100>;
                #pwm-cells = <2>;
+               clocks = <&tegra_car 17>;
        };
 
        rtc {
@@ -248,6 +298,8 @@
                interrupts = <0 38 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
+               clocks = <&tegra_car 12>, <&tegra_car 182>;
+               clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
 
@@ -257,6 +309,8 @@
                interrupts = <0 84 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
+               clocks = <&tegra_car 54>, <&tegra_car 182>;
+               clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
 
@@ -266,6 +320,8 @@
                interrupts = <0 92 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
+               clocks = <&tegra_car 67>, <&tegra_car 182>;
+               clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
 
@@ -275,6 +331,8 @@
                interrupts = <0 120 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
+               clocks = <&tegra_car 103>, <&tegra_car 182>;
+               clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
 
@@ -284,6 +342,8 @@
                interrupts = <0 53 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
+               clocks = <&tegra_car 47>, <&tegra_car 182>;
+               clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
 
@@ -294,6 +354,7 @@
                nvidia,dma-request-selector = <&apbdma 15>;
                #address-cells = <1>;
                #size-cells = <0>;
+               clocks = <&tegra_car 41>;
                status = "disabled";
        };
 
@@ -304,6 +365,7 @@
                nvidia,dma-request-selector = <&apbdma 16>;
                #address-cells = <1>;
                #size-cells = <0>;
+               clocks = <&tegra_car 44>;
                status = "disabled";
        };
 
@@ -314,6 +376,7 @@
                nvidia,dma-request-selector = <&apbdma 17>;
                #address-cells = <1>;
                #size-cells = <0>;
+               clocks = <&tegra_car 46>;
                status = "disabled";
        };
 
@@ -324,6 +387,7 @@
                nvidia,dma-request-selector = <&apbdma 18>;
                #address-cells = <1>;
                #size-cells = <0>;
+               clocks = <&tegra_car 68>;
                status = "disabled";
        };
 
@@ -334,6 +398,7 @@
                nvidia,dma-request-selector = <&apbdma 27>;
                #address-cells = <1>;
                #size-cells = <0>;
+               clocks = <&tegra_car 104>;
                status = "disabled";
        };
 
@@ -344,6 +409,15 @@
                nvidia,dma-request-selector = <&apbdma 28>;
                #address-cells = <1>;
                #size-cells = <0>;
+               clocks = <&tegra_car 105>;
+               status = "disabled";
+       };
+
+       kbc {
+               compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
+               reg = <0x7000e200 0x100>;
+               interrupts = <0 85 0x04>;
+               clocks = <&tegra_car 36>;
                status = "disabled";
        };
 
@@ -377,7 +451,13 @@
                       0x70080200 0x100>;
                interrupts = <0 103 0x04>;
                nvidia,dma-request-selector = <&apbdma 1>;
-
+               clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
+                        <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
+                        <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
+                        <&tegra_car 110>, <&tegra_car 162>;
+               clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+                             "i2s3", "i2s4", "dam0", "dam1", "dam2",
+                             "spdif_in";
                ranges;
                #address-cells = <1>;
                #size-cells = <1>;
@@ -386,6 +466,7 @@
                        compatible = "nvidia,tegra30-i2s";
                        reg = <0x70080300 0x100>;
                        nvidia,ahub-cif-ids = <4 4>;
+                       clocks = <&tegra_car 30>;
                        status = "disabled";
                };
 
@@ -393,6 +474,7 @@
                        compatible = "nvidia,tegra30-i2s";
                        reg = <0x70080400 0x100>;
                        nvidia,ahub-cif-ids = <5 5>;
+                       clocks = <&tegra_car 11>;
                        status = "disabled";
                };
 
@@ -400,6 +482,7 @@
                        compatible = "nvidia,tegra30-i2s";
                        reg = <0x70080500 0x100>;
                        nvidia,ahub-cif-ids = <6 6>;
+                       clocks = <&tegra_car 18>;
                        status = "disabled";
                };
 
@@ -407,6 +490,7 @@
                        compatible = "nvidia,tegra30-i2s";
                        reg = <0x70080600 0x100>;
                        nvidia,ahub-cif-ids = <7 7>;
+                       clocks = <&tegra_car 101>;
                        status = "disabled";
                };
 
@@ -414,6 +498,7 @@
                        compatible = "nvidia,tegra30-i2s";
                        reg = <0x70080700 0x100>;
                        nvidia,ahub-cif-ids = <8 8>;
+                       clocks = <&tegra_car 102>;
                        status = "disabled";
                };
        };
@@ -422,6 +507,7 @@
                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                reg = <0x78000000 0x200>;
                interrupts = <0 14 0x04>;
+               clocks = <&tegra_car 14>;
                status = "disabled";
        };
 
@@ -429,6 +515,7 @@
                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                reg = <0x78000200 0x200>;
                interrupts = <0 15 0x04>;
+               clocks = <&tegra_car 9>;
                status = "disabled";
        };
 
@@ -436,6 +523,7 @@
                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                reg = <0x78000400 0x200>;
                interrupts = <0 19 0x04>;
+               clocks = <&tegra_car 69>;
                status = "disabled";
        };
 
@@ -443,9 +531,39 @@
                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                reg = <0x78000600 0x200>;
                interrupts = <0 31 0x04>;
+               clocks = <&tegra_car 15>;
                status = "disabled";
        };
 
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <0>;
+               };
+
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <1>;
+               };
+
+               cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <2>;
+               };
+
+               cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <3>;
+               };
+       };
+
        pmu {
                compatible = "arm,cortex-a9-pmu";
                interrupts = <0 144 0x04