Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

[mirror_ubuntu-zesty-kernel.git] / arch / arm64 / boot / dts / rockchip / rk3399.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 1e24e455700b116c0e74186a6872e445ed2f50a1..c928015d39a213f9911c48a2a6312774a397d725 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -236,7 +236,7 @@
                             "rockchip,rk3288-dw-mshc";
                reg = <0x0 0xfe310000 0x0 0x4000>;
                interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
-               clock-freq-min-max = <400000 150000000>;
+               max-frequency = <150000000>;
                clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
                         <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
                clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
@@ -249,11 +249,12 @@
                             "rockchip,rk3288-dw-mshc";
                reg = <0x0 0xfe320000 0x0 0x4000>;
                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
-               clock-freq-min-max = <400000 150000000>;
+               max-frequency = <150000000>;
                clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
                         <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
                clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
                fifo-depth = <0x100>;
+               power-domains = <&power RK3399_PD_SD>;
                status = "disabled";
        };
 
@@ -270,6 +271,7 @@
                #clock-cells = <0>;
                phys = <&emmc_phy>;
                phy-names = "phy_arasan";
+               power-domains = <&power RK3399_PD_EMMC>;
                status = "disabled";
        };
 
@@ -694,6 +696,16 @@
                status = "disabled";
        };
 
+       qos_sd: qos@ffa74000 {
+               compatible = "syscon";
+               reg = <0x0 0xffa74000 0x0 0x20>;
+       };
+
+       qos_emmc: qos@ffa58000 {
+               compatible = "syscon";
+               reg = <0x0 0xffa58000 0x0 0x20>;
+       };
+
        qos_gmac: qos@ffa5c000 {
                compatible = "syscon";
                reg = <0x0 0xffa5c000 0x0 0x20>;
@@ -827,11 +839,23 @@
                        };
 
                        /* These power domains are grouped by VD_LOGIC */
+                       pd_emmc@RK3399_PD_EMMC {
+                               reg = <RK3399_PD_EMMC>;
+                               clocks = <&cru ACLK_EMMC>;
+                               pm_qos = <&qos_emmc>;
+                       };
                        pd_gmac@RK3399_PD_GMAC {
                                reg = <RK3399_PD_GMAC>;
-                               clocks = <&cru ACLK_GMAC>;
+                               clocks = <&cru ACLK_GMAC>,
+                                        <&cru PCLK_GMAC>;
                                pm_qos = <&qos_gmac>;
                        };
+                       pd_sd@RK3399_PD_SD {
+                               reg = <RK3399_PD_SD>;
+                               clocks = <&cru HCLK_SDMMC>,
+                                        <&cru SCLK_SDMMC>;
+                               pm_qos = <&qos_sd>;
+                       };
                        pd_vio@RK3399_PD_VIO {
                                reg = <RK3399_PD_VIO>;
                                #address-cells = <1>;
@@ -1027,6 +1051,9 @@
                clock-names = "pclk_efuse";
 
                /* Data cells */
+               cpu_id: cpu-id@7 {
+                       reg = <0x07 0x10>;
+               };
                cpub_leakage: cpu-leakage@17 {
                        reg = <0x17 0x1>;
                };
@@ -1105,6 +1132,16 @@
                                interrupt-names = "linestate";
                                status = "disabled";
                        };
+
+                       u2phy0_otg: otg-port {
+                               #phy-cells = <0>;
+                               interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
+                                            <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
+                                            <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
+                               interrupt-names = "otg-bvalid", "otg-id",
+                                                 "linestate";
+                               status = "disabled";
+                       };
                };
 
                u2phy1: usb2-phy@e460 {
@@ -1122,6 +1159,16 @@
                                interrupt-names = "linestate";
                                status = "disabled";
                        };
+
+                       u2phy1_otg: otg-port {
+                               #phy-cells = <0>;
+                               interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
+                                            <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
+                                            <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
+                               interrupt-names = "otg-bvalid", "otg-id",
+                                                 "linestate";
+                               status = "disabled";
+                       };
                };
 
                emmc_phy: phy@f780 {
@@ -1152,6 +1199,7 @@
                clock-names = "tcpdcore", "tcpdphy-ref";
                assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
                assigned-clock-rates = <50000000>;
+               power-domains = <&power RK3399_PD_TCPD0>;
                resets = <&cru SRST_UPHY0>,
                         <&cru SRST_UPHY0_PIPE_L00>,
                         <&cru SRST_P_UPHY0_TCPHY>;
@@ -1180,6 +1228,7 @@
                clock-names = "tcpdcore", "tcpdphy-ref";
                assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
                assigned-clock-rates = <50000000>;
+               power-domains = <&power RK3399_PD_TCPD1>;
                resets = <&cru SRST_UPHY1>,
                         <&cru SRST_UPHY1_PIPE_L00>,
                         <&cru SRST_P_UPHY1_TCPHY>;