MIPS: Loongson1B: Some fixes/updates for LS1B

[mirror_ubuntu-zesty-kernel.git] / arch / mips / include / asm / mach-loongson1 / regs-clk.h

diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h
index fb6a3ff9318fe5ef6d38154ecd14e26c258bb5b6..ee2445b10fc38535a7f478566724583601851191 100644 (file)
--- a/arch/mips/include/asm/mach-loongson1/regs-clk.h
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -20,15 +20,32 @@
 
 /* Clock PLL Divisor Register Bits */
 #define DIV_DC_EN                      (0x1 << 31)
+#define DIV_DC_RST                     (0x1 << 30)
 #define DIV_CPU_EN                     (0x1 << 25)
+#define DIV_CPU_RST                    (0x1 << 24)
 #define DIV_DDR_EN                     (0x1 << 19)
+#define DIV_DDR_RST                    (0x1 << 18)
+#define RST_DC_EN                      (0x1 << 5)
+#define RST_DC                         (0x1 << 4)
+#define RST_DDR_EN                     (0x1 << 3)
+#define RST_DDR                                (0x1 << 2)
+#define RST_CPU_EN                     (0x1 << 1)
+#define RST_CPU                                0x1
 
 #define DIV_DC_SHIFT                   26
 #define DIV_CPU_SHIFT                  20
 #define DIV_DDR_SHIFT                  14
 
-#define DIV_DC_WIDTH                   5
-#define DIV_CPU_WIDTH                  5
-#define DIV_DDR_WIDTH                  5
+#define DIV_DC_WIDTH                   4
+#define DIV_CPU_WIDTH                  4
+#define DIV_DDR_WIDTH                  4
+
+#define BYPASS_DC_SHIFT                        12
+#define BYPASS_DDR_SHIFT               10
+#define BYPASS_CPU_SHIFT               8
+
+#define BYPASS_DC_WIDTH                        1
+#define BYPASS_DDR_WIDTH               1
+#define BYPASS_CPU_WIDTH               1
 
 #endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */