MIPS: Prevent user from setting FCSR cause bits

[mirror_ubuntu-artful-kernel.git] / arch / mips / kernel / ptrace.c

diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index f639ccd5060c18d85f33a33f2cc4bce81605ae3b..3a7f7dd610fd087446d3bb1dbd8ebd1d4afd0374 100644 (file)
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -151,6 +151,7 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
        }
 
        __get_user(child->thread.fpu.fcr31, data + 64);
+       child->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
 
        /* FIR may not be written.  */
 
@@ -565,7 +566,7 @@ long arch_ptrace(struct task_struct *child, long request,
                        break;
 #endif
                case FPC_CSR:
-                       child->thread.fpu.fcr31 = data;
+                       child->thread.fpu.fcr31 = data & ~FPU_CSR_ALL_X;
                        break;
                case DSP_BASE ... DSP_BASE + 5: {
                        dspreg_t *dregs;