[MIPS] Add support for MIPS CMP platform.

[mirror_ubuntu-zesty-kernel.git] / arch / mips / mips-boards / generic / init.c

diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index 88e9c2a7a2f9a4b86b3eaa10c62db17c9471cb1d..852b19492d8c43e765b9ccdf830eead70ea48f2e 100644 (file)
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -57,7 +57,8 @@ int *_prom_argv, *_prom_envp;
 
 int init_debug = 0;
 
-unsigned int mips_revision_corid;
+int mips_revision_corid;
+int mips_revision_sconid;
 
 /* Bonito64 system controller register base. */
 unsigned long _pcictrl_bonito;
@@ -165,15 +166,15 @@ static void __init console_config(void)
                        bits = '8';
                if (flow == '\0')
                        flow = 'r';
-               sprintf (console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow);
-               strcat (prom_getcmdline(), console_string);
+               sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow);
+               strcat(prom_getcmdline(), console_string);
                pr_info("Config serial console:%s\n", console_string);
        }
 }
 #endif
 
 #ifdef CONFIG_KGDB
-void __init kgdb_config (void)
+void __init kgdb_config(void)
 {
        extern int (*generic_putDebugChar)(char);
        extern char (*generic_getDebugChar)(void);
@@ -217,7 +218,7 @@ void __init kgdb_config (void)
                {
                        char *s;
                        for (s = "Please connect GDB to this port\r\n"; *s; )
-                               generic_putDebugChar (*s++);
+                               generic_putDebugChar(*s++);
                }
 
                /* Breakpoint is invoked after interrupts are initialised */
@@ -225,7 +226,7 @@ void __init kgdb_config (void)
 }
 #endif
 
-void __init mips_nmi_setup (void)
+void __init mips_nmi_setup(void)
 {
        void *base;
        extern char except_vec_nmi;
@@ -237,7 +238,7 @@ void __init mips_nmi_setup (void)
        flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
 }
 
-void __init mips_ejtag_setup (void)
+void __init mips_ejtag_setup(void)
 {
        void *base;
        extern char except_vec_ejtag_debug;
@@ -249,6 +250,8 @@ void __init mips_ejtag_setup (void)
        flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
 }
 
+extern struct plat_smp_ops msmtc_smp_ops;
+
 void __init prom_init(void)
 {
        prom_argc = fw_arg0;
@@ -275,13 +278,45 @@ void __init prom_init(void)
                else
                        mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC;
        }
-       switch(mips_revision_corid) {
+
+       mips_revision_sconid = MIPS_REVISION_SCONID;
+       if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) {
+               switch (mips_revision_corid) {
+               case MIPS_REVISION_CORID_QED_RM5261:
+               case MIPS_REVISION_CORID_CORE_LV:
+               case MIPS_REVISION_CORID_CORE_FPGA:
+               case MIPS_REVISION_CORID_CORE_FPGAR2:
+                       mips_revision_sconid = MIPS_REVISION_SCON_GT64120;
+                       break;
+               case MIPS_REVISION_CORID_CORE_EMUL_BON:
+               case MIPS_REVISION_CORID_BONITO64:
+               case MIPS_REVISION_CORID_CORE_20K:
+                       mips_revision_sconid = MIPS_REVISION_SCON_BONITO;
+                       break;
+               case MIPS_REVISION_CORID_CORE_MSC:
+               case MIPS_REVISION_CORID_CORE_FPGA2:
+               case MIPS_REVISION_CORID_CORE_24K:
+                       /*
+                        * SOCit/ROCit support is essentially identical
+                        * but make an attempt to distinguish them
+                        */
+                       mips_revision_sconid = MIPS_REVISION_SCON_SOCIT;
+                       break;
+               case MIPS_REVISION_CORID_CORE_FPGA3:
+               case MIPS_REVISION_CORID_CORE_FPGA4:
+               case MIPS_REVISION_CORID_CORE_FPGA5:
+               case MIPS_REVISION_CORID_CORE_EMUL_MSC:
+               default:
+                       /* See above */
+                       mips_revision_sconid = MIPS_REVISION_SCON_ROCIT;
+                       break;
+               }
+       }
+
+       switch (mips_revision_sconid) {
                u32 start, map, mask, data;
 
-       case MIPS_REVISION_CORID_QED_RM5261:
-       case MIPS_REVISION_CORID_CORE_LV:
-       case MIPS_REVISION_CORID_CORE_FPGA:
-       case MIPS_REVISION_CORID_CORE_FPGAR2:
+       case MIPS_REVISION_SCON_GT64120:
                /*
                 * Setup the North bridge to do Master byte-lane swapping
                 * when running in bigendian.
@@ -305,9 +340,7 @@ void __init prom_init(void)
                set_io_port_base(MALTA_GT_PORT_BASE);
                break;
 
-       case MIPS_REVISION_CORID_CORE_EMUL_BON:
-       case MIPS_REVISION_CORID_BONITO64:
-       case MIPS_REVISION_CORID_CORE_20K:
+       case MIPS_REVISION_SCON_BONITO:
                _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE);
 
                /*
@@ -334,13 +367,10 @@ void __init prom_init(void)
                set_io_port_base(MALTA_BONITO_PORT_BASE);
                break;
 
-       case MIPS_REVISION_CORID_CORE_MSC:
-       case MIPS_REVISION_CORID_CORE_FPGA2:
-       case MIPS_REVISION_CORID_CORE_FPGA3:
-       case MIPS_REVISION_CORID_CORE_24K:
-       case MIPS_REVISION_CORID_CORE_EMUL_MSC:
+       case MIPS_REVISION_SCON_SOCIT:
+       case MIPS_REVISION_SCON_ROCIT:
                _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
-
+       mips_pci_controller:
                mb();
                MSC_READ(MSC01_PCI_CFG, data);
                MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
@@ -374,10 +404,15 @@ void __init prom_init(void)
                set_io_port_base(MALTA_MSC_PORT_BASE);
                break;
 
+       case MIPS_REVISION_SCON_SOCITSC:
+       case MIPS_REVISION_SCON_SOCITSCP:
+               _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000);
+               goto mips_pci_controller;
+
        default:
-               /* Unknown Core card */
-               mips_display_message("CC Error");
-               while(1);   /* We die here... */
+               /* Unknown system controller */
+               mips_display_message("SC Error");
+               while (1);   /* We die here... */
        }
 #endif
        board_nmi_handler_setup = mips_nmi_setup;
@@ -389,4 +424,13 @@ void __init prom_init(void)
 #ifdef CONFIG_SERIAL_8250_CONSOLE
        console_config();
 #endif
+#ifdef CONFIG_MIPS_CMP
+       register_smp_ops(&cmp_smp_ops);
+#endif
+#ifdef CONFIG_MIPS_MT_SMP
+       register_smp_ops(&vsmp_smp_ops);
+#endif
+#ifdef CONFIG_MIPS_MT_SMTC
+       register_smp_ops(&msmtc_smp_ops);
+#endif
 }