perf/x86/msr: Add AMD PTSC (Performance Time-Stamp Counter) support

[mirror_ubuntu-artful-kernel.git] / arch / x86 / events / msr.c

diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index ec863b9a9f780c7507634353d64f9c2f76f1a0e1..6f6772f273aa936a0eaff0ed1250ebecc213ed48 100644 (file)
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -6,6 +6,7 @@ enum perf_msr_id {
        PERF_MSR_MPERF                  = 2,
        PERF_MSR_PPERF                  = 3,
        PERF_MSR_SMI                    = 4,
+       PERF_MSR_PTSC                   = 5,
 
        PERF_MSR_EVENT_MAX,
 };
@@ -15,6 +16,11 @@ static bool test_aperfmperf(int idx)
        return boot_cpu_has(X86_FEATURE_APERFMPERF);
 }
 
+static bool test_ptsc(int idx)
+{
+       return boot_cpu_has(X86_FEATURE_PTSC);
+}
+
 static bool test_intel(int idx)
 {
        if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
@@ -74,6 +80,7 @@ PMU_EVENT_ATTR_STRING(aperf, evattr_aperf, "event=0x01");
 PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02");
 PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03");
 PMU_EVENT_ATTR_STRING(smi,   evattr_smi,   "event=0x04");
+PMU_EVENT_ATTR_STRING(ptsc,  evattr_ptsc,  "event=0x05");
 
 static struct perf_msr msr[] = {
        [PERF_MSR_TSC]   = { 0,                 &evattr_tsc,    NULL,            },
@@ -81,6 +88,7 @@ static struct perf_msr msr[] = {
        [PERF_MSR_MPERF] = { MSR_IA32_MPERF,    &evattr_mperf,  test_aperfmperf, },
        [PERF_MSR_PPERF] = { MSR_PPERF,         &evattr_pperf,  test_intel,      },
        [PERF_MSR_SMI]   = { MSR_SMI_COUNT,     &evattr_smi,    test_intel,      },
+       [PERF_MSR_PTSC]   = { MSR_F15H_PTSC,    &evattr_ptsc,   test_ptsc,       },
 };
 
 static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {