x86/cpu/bugs: Use __initconst for 'const' init data

[mirror_ubuntu-bionic-kernel.git] / arch / x86 / include / asm / msr-index.h

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index ea3ad052ee95bad9cb8bb4d5a22fafc775299c1c..43414fb05f66b989e5866a431ce713b2b27f8412 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -2,6 +2,8 @@
 #ifndef _ASM_X86_MSR_INDEX_H
 #define _ASM_X86_MSR_INDEX_H
 
+#include <linux/bits.h>
+
 /*
  * CPU model specific register (MSR) numbers.
  *
@@ -40,13 +42,14 @@
 /* Intel MSRs. Some also available on other CPUs */
 
 #define MSR_IA32_SPEC_CTRL             0x00000048 /* Speculation Control */
-#define SPEC_CTRL_IBRS                 (1 << 0)   /* Indirect Branch Restricted Speculation */
-#define SPEC_CTRL_STIBP                        (1 << 1)   /* Single Thread Indirect Branch Predictors */
+#define SPEC_CTRL_IBRS                 BIT(0)     /* Indirect Branch Restricted Speculation */
+#define SPEC_CTRL_STIBP_SHIFT          1          /* Single Thread Indirect Branch Predictor (STIBP) bit */
+#define SPEC_CTRL_STIBP                        BIT(SPEC_CTRL_STIBP_SHIFT)      /* STIBP mask */
 #define SPEC_CTRL_SSBD_SHIFT           2          /* Speculative Store Bypass Disable bit */
-#define SPEC_CTRL_SSBD                 (1 << SPEC_CTRL_SSBD_SHIFT)   /* Speculative Store Bypass Disable */
+#define SPEC_CTRL_SSBD                 BIT(SPEC_CTRL_SSBD_SHIFT)       /* Speculative Store Bypass Disable */
 
 #define MSR_IA32_PRED_CMD              0x00000049 /* Prediction Command */
-#define PRED_CMD_IBPB                  (1 << 0)   /* Indirect Branch Prediction Barrier */
+#define PRED_CMD_IBPB                  BIT(0)     /* Indirect Branch Prediction Barrier */
 
 #define MSR_PPIN_CTL                   0x0000004e
 #define MSR_PPIN                       0x0000004f
@@ -68,19 +71,25 @@
 #define MSR_MTRRcap                    0x000000fe
 
 #define MSR_IA32_ARCH_CAPABILITIES     0x0000010a
-#define ARCH_CAP_RDCL_NO               (1 << 0)   /* Not susceptible to Meltdown */
-#define ARCH_CAP_IBRS_ALL              (1 << 1)   /* Enhanced IBRS support */
-#define ARCH_CAP_SSB_NO                        (1 << 4)   /*
-                                                   * Not susceptible to Speculative Store Bypass
-                                                   * attack, so no Speculative Store Bypass
-                                                   * control required.
-                                                   */
+#define ARCH_CAP_RDCL_NO               BIT(0)  /* Not susceptible to Meltdown */
+#define ARCH_CAP_IBRS_ALL              BIT(1)  /* Enhanced IBRS support */
+#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3)  /* Skip L1D flush on vmentry */
+#define ARCH_CAP_SSB_NO                        BIT(4)  /*
+                                                * Not susceptible to Speculative Store Bypass
+                                                * attack, so no Speculative Store Bypass
+                                                * control required.
+                                                */
+#define ARCH_CAP_MDS_NO                        BIT(5)   /*
+                                                 * Not susceptible to
+                                                 * Microarchitectural Data
+                                                 * Sampling (MDS) vulnerabilities.
+                                                 */
 
 #define MSR_IA32_FLUSH_CMD             0x0000010b
-#define L1D_FLUSH                      (1 << 0)   /*
-                                                   * Writeback and invalidate the
-                                                   * L1 data cache.
-                                                   */
+#define L1D_FLUSH                      BIT(0)  /*
+                                                * Writeback and invalidate the
+                                                * L1 data cache.
+                                                */
 
 #define MSR_IA32_BBL_CR_CTL            0x00000119
 #define MSR_IA32_BBL_CR_CTL3           0x0000011e
@@ -373,6 +382,7 @@
 #define MSR_F15H_NB_PERF_CTR           0xc0010241
 #define MSR_F15H_PTSC                  0xc0010280
 #define MSR_F15H_IC_CFG                        0xc0011021
+#define MSR_F15H_EX_CFG                        0xc001102c
 
 /* Fam 10h MSRs */
 #define MSR_FAM10H_MMIO_CONF_BASE      0xc0010058
@@ -610,6 +620,12 @@
 
 #define MSR_IA32_TSC_DEADLINE          0x000006E0
 
+
+#define MSR_TSX_FORCE_ABORT            0x0000010F
+
+#define MSR_TFA_RTM_FORCE_ABORT_BIT    0
+#define MSR_TFA_RTM_FORCE_ABORT                BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)
+
 /* P4/Xeon+ specific */
 #define MSR_IA32_MCG_EAX               0x00000180
 #define MSR_IA32_MCG_EBX               0x00000181