KVM: x86/speculation: Disable Fill buffer clear within guests

[mirror_ubuntu-jammy-kernel.git] / arch / x86 / include / asm / msr-index.h

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index a7c413432b33d85a081dbb227a799035221fb256..4aa9701e0018f1ce73413175c14ba2f81b74a0b6 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -114,6 +114,30 @@
                                                 * Not susceptible to
                                                 * TSX Async Abort (TAA) vulnerabilities.
                                                 */
+#define ARCH_CAP_SBDR_SSDP_NO          BIT(13) /*
+                                                * Not susceptible to SBDR and SSDP
+                                                * variants of Processor MMIO stale data
+                                                * vulnerabilities.
+                                                */
+#define ARCH_CAP_FBSDP_NO              BIT(14) /*
+                                                * Not susceptible to FBSDP variant of
+                                                * Processor MMIO stale data
+                                                * vulnerabilities.
+                                                */
+#define ARCH_CAP_PSDP_NO               BIT(15) /*
+                                                * Not susceptible to PSDP variant of
+                                                * Processor MMIO stale data
+                                                * vulnerabilities.
+                                                */
+#define ARCH_CAP_FB_CLEAR              BIT(17) /*
+                                                * VERW clears CPU fill buffer
+                                                * even on MDS_NO CPUs.
+                                                */
+#define ARCH_CAP_FB_CLEAR_CTRL         BIT(18) /*
+                                                * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]
+                                                * bit available to control VERW
+                                                * behavior.
+                                                */
 
 #define MSR_IA32_FLUSH_CMD             0x0000010b
 #define L1D_FLUSH                      BIT(0)  /*
@@ -128,9 +152,10 @@
 #define TSX_CTRL_RTM_DISABLE           BIT(0)  /* Disable RTM feature */
 #define TSX_CTRL_CPUID_CLEAR           BIT(1)  /* Disable TSX enumeration */
 
-/* SRBDS support */
 #define MSR_IA32_MCU_OPT_CTRL          0x00000123
-#define RNGDS_MITG_DIS                 BIT(0)
+#define RNGDS_MITG_DIS                 BIT(0)  /* SRBDS support */
+#define RTM_ALLOW                      BIT(1)  /* TSX development mode */
+#define FB_CLEAR_DIS                   BIT(3)  /* CPU Fill buffer clear disable */
 
 #define MSR_IA32_SYSENTER_CS           0x00000174
 #define MSR_IA32_SYSENTER_ESP          0x00000175
@@ -486,6 +511,23 @@
 
 #define MSR_AMD64_VIRT_SPEC_CTRL       0xc001011f
 
+/* AMD Collaborative Processor Performance Control MSRs */
+#define MSR_AMD_CPPC_CAP1              0xc00102b0
+#define MSR_AMD_CPPC_ENABLE            0xc00102b1
+#define MSR_AMD_CPPC_CAP2              0xc00102b2
+#define MSR_AMD_CPPC_REQ               0xc00102b3
+#define MSR_AMD_CPPC_STATUS            0xc00102b4
+
+#define AMD_CPPC_LOWEST_PERF(x)                (((x) >> 0) & 0xff)
+#define AMD_CPPC_LOWNONLIN_PERF(x)     (((x) >> 8) & 0xff)
+#define AMD_CPPC_NOMINAL_PERF(x)       (((x) >> 16) & 0xff)
+#define AMD_CPPC_HIGHEST_PERF(x)       (((x) >> 24) & 0xff)
+
+#define AMD_CPPC_MAX_PERF(x)           (((x) & 0xff) << 0)
+#define AMD_CPPC_MIN_PERF(x)           (((x) & 0xff) << 8)
+#define AMD_CPPC_DES_PERF(x)           (((x) & 0xff) << 16)
+#define AMD_CPPC_ENERGY_PERF_PREF(x)   (((x) & 0xff) << 24)
+
 /* Fam 17h MSRs */
 #define MSR_F17H_IRPERF                        0xc00000e9
 
@@ -625,6 +667,8 @@
 
 #define MSR_IA32_BNDCFGS_RSVD          0x00000ffc
 
+#define MSR_IA32_XFD                   0x000001c4
+#define MSR_IA32_XFD_ERR               0x000001c5
 #define MSR_IA32_XSS                   0x00000da0
 
 #define MSR_IA32_APICBASE              0x0000001b